Another round of aesthetic improvements to the VHDL code for ADC5G.
Added a special case to the MMCM-parameter generator code for D=3 or D=3.

When Fin > 350 MHz the Xilinx tools do not allow the DIVCLK_DIVIDE parameter
to be 3 or 4, to get around this both M and D must be doubled.
See: http://www.xilinx.com/support/answers/38133.htm
The ADC5G SPI interface now initial sets the ADC in Gray code mode.

This has been shown to reduced glitches significantly.
The ROACH 2 SPI interface now also uses Gray code.

I forgot to make the same changes from the last commit to the ROACH2
opb_adc5g pcore.
Added the Gray code to binary decoder.

The fact that the ADC uses Gray code should now be transparent to the user.
On ROACH2, the ADC5G board is now reset simultaneously with the MMCM.

This fixes an issue where the "sync" line into the e2v chip was not being
driven by the FPGA and could therefore float to a logic high, thus keeping
the chip in reset and preventing it from outputting a clock to the fabric.

Fix for ROACH coming soon.
Merge remote branch 'ska-sa/master'
Merge remote branch 'casper/master'
Added a clock-domain crossing FIFO to the ROACH2 8-bit ADC5G pcore.

This uses CORE generator to generate the netlist for the FIFO.
Added pcores needed to work with 13.x toolflow on ROACH2.
For 'Block Memory Generator' to work with 13.x you need a NEWPROJECT line in the TCL script.
Some changes to ADC5G's gen_ucf.m file to make meeting timing easier on ROACH2.

These involve placing the register's close to ZDOK0's 1 input pin (which is placed
on the opposite side of the chip on rev. 1 as the other pins) physically close to
the input pin.
Merge branch 'fifo'
Modified the extract_entity script slightly to allow black-boxing in 13.x.

For some reason in the newer tools, 13.x, if there's no architecture block in
the HDL wrapper the block box is not properly recognized. It doesn't give an
error but the block-box is somehow never inserted.
Ported the KAT ADC's OPB/SPI controller to the ADC5G for ROACH2.

The KATADC controller only needed some minor modifications to work
with the E2V chip's SPI (see the Verilog file for details). Now all of
the writable registers on the chip can be set using 'adc5g_controller'
within BORPH.
Added 'gcb' as a parameter to adc5g_init.m save/same_state calls.

This means that if the top model file changes names the ADC5G's
internal gateway blocks also appropriately change their names on
the next update diagram.
Some changes to help meet timing when using the 11.x tools with ADC5G on ROACH2.

Change MAP and PAR options to try less hard (not sure why this works).

Also, added two stages of buffers on the inputs to the FIFO and manually
placed certain buffers in pcore ISD_1 (which was tightened up a bit). This
helps to position the FD's attached to the one input pad for ZDOK0 which
was accidentally placed on the other side of the chip than the others.
This will be uneccessary for the next ROACH2 rev. and this commit will
likely be reverted at that point.
Added read capability to the ADC5G, ROACH2 OPB core.
Added a testbench for ADC5G SPI logic based on the KATADC testbench code.

This proved very useful in getting the SPI read logic to work!
Merge branch 'spiread'