Move [get|set]BasePtrStackAdjustment() from MachineFrameInfo to
X86MachineFunctionInfo as this is currently only used by X86. If this ever
becomes an issue on another arch (e.g., ARM) then we can hoist it back out.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160009 91177308-0d34-0410-b5e6-96231b3b80d8
Run early if-conversion in domtree post-order.

This ordering allows nested if-conversion without using a work list, and
it makes it possible to update the dominator tree on the fly as well.

Any erased basic blocks will always be dominated by the current
post-order position, so the domtree can be pruned without invalidating
the iterator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160025 91177308-0d34-0410-b5e6-96231b3b80d8
Teach the LiveInterval::join function to use the fast merge algorithm,
generalizing its implementation sufficiently to support this value
number scenario as well.

This cuts out another significant performance hit in large functions
(over 10k basic blocks, etc), especially those with "natural" CFG
structures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160026 91177308-0d34-0410-b5e6-96231b3b80d8
Require and preserve LoopInfo for early if-conversion.

It will surely be needed by heuristics.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160027 91177308-0d34-0410-b5e6-96231b3b80d8
   Mips specific inline asm operand modifier 'L'.
   
   Low order register of a double word register operand. Operands 
   are defined by the name of the variable they are marked with in
   the inline assembler code. This is a way to specify that the 
   operand just refers to the low order register for that variable.
   
   It is the opposite of modifier 'D' which specifies the high order
   register.
   
   Example:
   
 main()
{

    long long ll_input = 0x1111222233334444LL;
    long long ll_val = 3;
    int i_result = 0;

    __asm__ __volatile__( 
		   "or	%0, %L1, %2"
	     : "=r" (i_result) 
	     : "r" (ll_input), "r" (ll_val)); 
}

   Which results in:
   
   	lui	$2, %hi(_gp_disp)
	addiu	$2, $2, %lo(_gp_disp)
	addiu	$sp, $sp, -8
	addu	$2, $2, $25
	sw	$2, 0($sp)
	lui	$2, 13107
	ori	$3, $2, 17476     <-- Low 32 bits of ll_input
	lui	$2, 4369
	ori	$4, $2, 8738      <-- High 32 bits of ll_input
	addiu	$5, $zero, 3  <-- Low 32 bits of ll_val
	addiu	$2, $zero, 0  <-- High 32 bits of ll_val
	#APP
	or	$3, $4, $5        <-- or i_result, high 32 ll_input, low 32 of ll_val
	#NO_APP
	addiu	$sp, $sp, 8
	jr	$ra

If not direction is done for the long long for 32 bit variables results
in using the low 32 bits as ll_val shows.

There is an existing bug if 'L' or 'D' is used for the destination register
for 32 bit long longs in that the target value will be updated incorrectly
for the non-specified part unless explicitly set within the inline asm code.




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160028 91177308-0d34-0410-b5e6-96231b3b80d8
Lower RETURNADDR node in Mips backend.

Patch by Sasa Stankovic.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160031 91177308-0d34-0410-b5e6-96231b3b80d8
Only apply the SETCC+SITOFP -> SELECTCC optimization when the SETCC returns an MVT::i1, i.e. before type legalization.
This is a speculative fix for a problem on Mips reported by Akira Hatanaka.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160036 91177308-0d34-0410-b5e6-96231b3b80d8
Refactor the DAG Legalizer by extracting the legalization of
Load and Store nodes into their own functions.
No functional change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160037 91177308-0d34-0410-b5e6-96231b3b80d8
Remove unused variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160040 91177308-0d34-0410-b5e6-96231b3b80d8
Rename many of the Tmp1, Tmp2, Tmp3 variables to names such as Chain, Value, Ptr, etc.
No functionality change.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160042 91177308-0d34-0410-b5e6-96231b3b80d8

When ext-loading and trunc-storing vectors to memory, on x86 32bit systems, allow loads/stores of 64bit values from xmm registers.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160044 91177308-0d34-0410-b5e6-96231b3b80d8
[x86 fast-isel] Rather then call llvm_unreachable() have fast-isel fall back
to Selection DAG isel.  Patch by Andrew Kaylor <andrew.kaylor@intel.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160055 91177308-0d34-0410-b5e6-96231b3b80d8
test commit

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160056 91177308-0d34-0410-b5e6-96231b3b80d8
PR13326: Fix a subtle edge case in the udiv -> magic multiply generator.

This caused 6 of 65k possible 8 bit udivs to be wrong.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160058 91177308-0d34-0410-b5e6-96231b3b80d8
InstrEmitter::EmitSubregNode() optimize extract_subreg in this case:

r1025 = s/zext r1024, 4
r1026 = extract_subreg r1025, 4

to a copy:
r1026 = copy r1024

This is correct. However it uses TII->isCoalescableExtInstr() which can return
true for instructions which essentially does a sext_in_reg so this can end up
with an illegal copy where the source and destination register classes do not
match. Add a check to avoid it. Sorry, no test case possible at this time.

rdar://11849816


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160059 91177308-0d34-0410-b5e6-96231b3b80d8
Implement MipsTargetLowering::LowerSELECT_CC to custom lower SELECT_CC.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160064 91177308-0d34-0410-b5e6-96231b3b80d8
X86: Update to peephole optimization to move Movr0 before (Sub, Cmp) pair.

When Movr0 is between sub and cmp, we move Movr0 before sub if it enables
removal of Cmp.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160066 91177308-0d34-0410-b5e6-96231b3b80d8
Test case for r160036.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160067 91177308-0d34-0410-b5e6-96231b3b80d8
[x86 fast-isel] Per discussion with Eric, add all cases to switch with verbose
comments.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160069 91177308-0d34-0410-b5e6-96231b3b80d8
In register classes in MipsRegisterInfo.td, list the registers in ascending
order of binary encoding.

Patch by Vladimir Medic.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160073 91177308-0d34-0410-b5e6-96231b3b80d8