cpu-tegra: ISO C90 forbids mixed declarations and code
Revert "Ondemand from my omap repository."

This reverts commit d96d747718a2e712c5d88ebf8a558edd20df7ab2.
Add fix for the system not to forget min/max clocks on hotplug.
Enable ARCH_POWER to use arm_cpu_topology power management features.
cleanup: remove htc added tegra sleep stats
Revert "Add fix for the system not to forget min/max clocks on hotplug."

This reverts commit a1e25fb835780255e8d34795b99835d14e3b86ae.
ARM: tegra: emc: Reduce DDR3 min rate to 25.5MHz. - from NVIDIA
ARM: tegra3: enable cpu auto_hotplug. - from NVIDIA
Revert "ARM: tegra3: enable cpu auto_hotplug. - from NVIDIA"

This reverts commit 593b3c72e500c5658099980e45e6fa8565a62050.
Revert "ARM: tegra: power: Trim Tegra3 hotplug timings"

This reverts commit 22f5ad8d6101d98c09d1256f43955cca84e61d5e.
ARM: tegra3: Fine tune hotplug driver. - from NVIDIA
ARM: tegra: power: Trim Tegra3 hotplug timings

Bug 945921
Reduce delays in going LP->G and G->Gn

Change-Id: I326bec8c9c190268c422ea43e98a90f73d9b4ba7
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/86692
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Satya Popuri <spopuri@nvidia.com>
(cherry picked from commit 51b7022f328d955cc4dbbf47b35403ea9c5e3a7b)

Conflicts:
	arch/arm/mach-tegra/cpu-tegra3.c

ARM: tegra: power: Update Tegra3 auto-hotplug states

Updated Tegra3 auto-hotplug state machine:

- no longer enter down state on LP CPU (there is no down path on LP)
- no longer enter idle state on G CPU (since load distribution between
G cores may change without CPU frequency change, continue polling)
- allow only disabled or idle state to be set via auto-hotplug sysfs
node, and synchronize with cpufreq governor in the latter case

Change-Id: Ibb93ddca852bbe1341fc5c52b0c83c16e9963e9d
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/71584
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
(cherry picked from commit 13c1254e722d27d2eb336c527d1a8a82b024698c)

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Change-Id: I7c23b13d3ecfcab2f01a14c6cf629afd361f13b6
Reviewed-on: http://git-master/r/97866
Reviewed-by: Allen Martin <amartin@nvidia.com>
ARM: tegra: power: Don't enter LP2 if not in NOHZ mode

Prevent Tegra3 secondary CPU entry to LP2 state when scheduler tick
is not switched to NOHZ mode, yet.

Bug 945658

Change-Id: I31e43f7890f09af269beda768e848b3e0fb4b313
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/87474
Reviewed-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Tested-by: Hyungwoo Yang <hyungwooy@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 1c348149ae3bb07c52a53f8600813d6c85277dfc)

ARM: tegra: power: Fix Tegra3 LP2 stats

Fixed Tegra3 LP2 stats to account for total completed and interrupted
LP2 time (interrupted LP2 time was missed).

(cherry picked from commit 4207244f6fc25544315fe5aaf067ea7684731d9d)

Change-Id: I3b87819d56e3a700f7e0858fa124b0fdfabe8295
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/73902
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit ee2dd3a57c91ba63728e78b8d0f9b735fa0b9df1)

ARM: tegra: power: Don't over-sleep LP2 on secondary CPUs

Adjust Tegra3 secondary CPU LP2 time for exit latency to avoid
scheduler event over-sleep.

Change-Id: I33aa7566eb8763099ae2fc2dc7b3f42a752352f4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/78635
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 433a3e356a0281efb1caf9b78bb1576008a58ed2)

ARM: tegra: power: Separate lp2 latency for secondary CPUs

Do not use common lp2 exit latency for Tegra3 secondary CPUs in
G mode. Separately measure and adjust latency on each slave CPU;
use per-cpu latency to determine target residency threshold for
entering lp2 on each CPU.

Change-Id: I4470d1b4814d8f12129e21105dd952a903084f1e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/78375
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
(cherry picked from commit cfba9ceaae3be7fca988b2b460b655144e66c2b2)

ARM: tegra: power: Separate lp2 latency for G/LP CPU modes

Do not use common lp2 exit latency for Tegra3 CPU G and CPU LP modes.
Separately measure and adjust latency in each mode; restart calculation
after mode switch from the last measured latency in the target mode.

Change-Id: I54803c6abf4107a578aa1fed8feaa4a419a9c07f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/78344
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
(cherry picked from commit 45986459144b6af477fec937b627f55bf517b92e)

ARM: tegra: power: Re-factor Tegra3 secondary CPU LP2 entry

When Tegra3 secondary CPU is entering LP2, read TWD timer state
into context structure, rather than separate local variables.

Change-Id: I237eafc50a11d535b94f334631d039ba9c4bf44b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/77957
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
(cherry picked from commit eccb57527e305ec8d1ac4e472d891a2e0d5baf34)

Signed-off-by: Joseph Lo <josephl@nvidia.com>
Change-Id: I099efb047698ce4b4b6d53341be151dee2419a4d
Reviewed-on: http://git-master/r/97868
Reviewed-by: Allen Martin <amartin@nvidia.com>
tegra:cpuidle:remove flow-controller programming

bug 937980

Remove some legacy flow-controller programming from LP3 entry and exit
paths. Also remove data synchronization barrier instruction after wfi
to improve scaling across cores.

Change-Id: I7e9e8e7106e77d2abf93a716426930c224d877ed
Signed-off-by: satya popuri <spopuri@nvidia.com>
Reviewed-on: http://git-master/r/86451
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit f88ee65418126365fc10af3d3771bba5d2e41d57)

ARM: tegra: power: Report LP3 state if LP2 is not allowed

Properly report LP3 state to idle governor when LP2 entry is not
allowed and LP2 request is redirected to LP3.

Change-Id: If4bdf6b635d7b40a8958dc5357903c4ea563d112
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/77956
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 4cf479b35d5314b81becdfbf4cc8d4b1224dcb94)

Change-Id: I85ba0e786f22b914ed03df085b521a2579ff576d
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Reviewed-on: http://git-master/r/98176
Reviewed-by: Allen Martin <amartin@nvidia.com>
ARM: tegra: dvfs: Relax Tegra3 lower speedo limits

Bug 817679
Bug 841336

Change-Id: Icd6652b44ac4fd337a25b4c12b6e25ebac1579f8
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/84705
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 44e7c117b3188bdd45a6e7dae31e8d3ea78c5d98)

ARM: tegra: dvfs: Update Tegra3 speedo thresholds

Bug 817679
Bug 841336

Change-Id: I1033c34eb879bdabc659d17a5a28149869e6b862
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/82606
Reviewed-by: Daniel Solomon <daniels@nvidia.com>
Tested-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
(cherry picked from commit a4f6d43aa692586654ebb441246f0509fce7fa58)

ARM: tegra: dvfs: Update T30L and T30SL Vcore min values.

Update T30L and T30SL values Vcore min voltage is now
1.2V when Vcpu >= 1.1V. Old setting was 1.3V.

Bug 841336
Signed-off-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-on: http://git-master/r/86912
(cherry picked from commit 00dbc09e7b65aaeb8e80224ab263e0c9b166a95e)

Change-Id: Ib214682c5a11a47c3ac955df0e537e9294edf7ac
Reviewed-on: http://git-master/r/87516
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Gaurav Sarode <gsarode@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
(cherry picked from commit 51e04ace158d95d40b7dde428a807adddd2ab142)

ARM: tegra: dvfs: correct LCD frequency for 1V

Bug 841336
Bug 817697

Change-Id: Ibd5f1d5f5e2c87fad579a48c951c9a45ef9d5e33
Reviewed-on: http://git-master/r/82996
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 5850c8f4968fd7acbb22e377a56a476e37ac5117)

ARM: tegra: dvfs: Fix Tegra3 cbus limit at 1.35V

Change-Id: Ibf8a6f3f51cf47f98b46bace3eaf3bd79ca522b0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/79915
Reviewed-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit e031d09197f7b4214ad035b1acf7d6c39049021e)

ARM: tegra: dvfs: Expand Tegra3 cpu dvfs tables

Expand Tegra3 cpu dvfs tables to add characterization results
for 800mV VDD_CPU.

Bug 817679
Bug 841336

Change-Id: I1867b2ec1b87b0db620c68deca9d2dbfc013deaa
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/77936
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit f5b488019895c83e05ded8a8912cf3eb4eea5686)

ARM: tegra: dvfs: Add Tegra3 x7 detection

- Detect T37 and AP37 SKUs.
- Created a new threshold for T37

Bug 841336

Change-Id: I78a6875058ebd6bc5e70042aec020c259de0976c
Signed-off-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-on: http://git-master/r/77661
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit b4bee7487a94ccd3456d39254d6699db7396ab61)

arm: tegra3: dvfs: update tegra3 speedo thresholds

bug 921903

Change-Id: I8932dbde45cb0b025ba8a537b528ebec82c3424e
Signed-off-by: Ken Chang <kenc@nvidia.com>
Reviewed-on: http://git-master/r/75130
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit e4b7c2cb3595c66c4feadace670e88e41f241549)

ARM: tegra: dvfs: Add Tegra3 x7 core dvfs

- Added Tegra3 x7 core dvfs entries
- Increased EMC, graphics, and UART clocks maximum limits
- Updated PLLC configuration table

Bug 841336

Change-Id: Ifa235e60d66d959ad589574c5ebde90eb0b65385
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/76942
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Daniel Solomon <daniels@nvidia.com>
Tested-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 8d43a2394fb439dd9a59da7908f6cbda4dd66a4e)

ARM: tegra: clock: Add support for Tegra3 MSelect clock

Added clock for memory path selection module (MSelect) to Tegra3
peripheral clocks. Initialized MSelect clock rate to 102MHz.

Change-Id: I73676882d8e6805445985b23257bcf6410e8c3e0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/76484
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
(cherry picked from commit 35b59755650c35008a19d0fdc25a44fed2046ff8)

tegra3: clock: Support for divisor 15.1

Uart clock source has divisor of 16 bits where
LSB is 0.5.
Adding support for divisor 15.1 and configuring uart
for use the 15.1 type divisor.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>

Change-Id: Ifdd77041e7abb43026bbfb273f6e12923d64d607
Reviewed-on: http://git-master/r/70324
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Tested-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
(cherry picked from commit ff8a68234313a2822cbb91f5faba946fe5dc3a85)

ARM: tegra: dvfs: Add Tegra3 x7 CPU dvfs entries

Bug 841336

Change-Id: I2806c8e4f08af49edf57f00a43438b1503d6aedb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/76912
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Daniel Solomon <daniels@nvidia.com>
Tested-by: Daniel Solomon <daniels@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 31565f1a616cabedc6b2b8a071cbaa893d56bf80)

ARM: tegra: clock: Add Tegra3 0.95V core voltage step

- Expanded Tegra3 DVFS tables with 0.95V core voltage step
- Updated cbus minimum rate calculation, since cbus can not
  run at 0.95V
- Updated PLLM dvfs initialization, since PLLM can no longer
  be voltage independent, even when its usage is restricted.

Bug 817679
Bug 841336

Change-Id: I4973dc19d351ce237f2b249ebf75a79abf3afef4
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/74141
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit a47d0348be01e20b991467afd4234c4f0605dbf4)

Conflicts:

	arch/arm/mach-tegra/tegra3_clocks.c

ARM: tegra: dvfs: Add cold zone Tegra3 CPU dvfs limits

Added alternative frequency limits for Tegra3 CPU. These limits are
applied only in the lowest CPU EDP temperature zone, and the offset
from regular Tegra3 dvfs frequencies is set at -50MHz at all scaling
voltage steps. Offset values as well as temperature threshold are to
be updated per characterization.

Bug 913884

Change-Id: Ia420f54b4c9fdc966e44d0269d45d9164d751b5f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/70189
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
(cherry picked from commit e45f2206cf3af012cacf928c3aa7807e2c1f8ac0)

ARM: tegra: dvfs: Add alternative dvfs frequency limits

Added an option to specify alternative dvfs frequency limits for each
tegra clock domain. These alternative limits can be applied in some
particularly extreme (e.g., slow) corner of process-temperature space
with no effect on regular limits for the rest of the space.

Bug 913884

Change-Id: I05e319b60f6dc6f4e7f15c7e677e5a3bce77f201
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/70188
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
(cherry picked from commit 84fa2824e920b7766eea5c5e459dc4f4b9f50efd)

ARM: tegra: dvfs: Update Tegra3 vdd_core floor

To properly account for voltage steps with 12.5mV resolution, moved
up by 25mV all thresholds in vdd_core floor calculation function, and
replaced "less than or equal" comparison with "less than".

Change-Id: I869ecabf4e25a268fbe279e54026d4fd1bf25db6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/73903
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit a3b30f2b835c9c83f8b31f3955c20034d44de0e5)

ARM: tegra: dvfs: Update Tegra3 CPU DVFS tables

Bug 817679
Bug 841336

Change-Id: I9a9d9e7a03b64774b1d2ebd8533be85582827515
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/71755
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
(cherry picked from commit d68761232abc36de938d1a7b7f2e87b4731451c2)

ARM: tegra: dvfs: Re-arrange Tegra3 scaling voltages

Removed 925mV and 950mV steps / added 1.175mV and 1.212mV Tegra3 CPU
voltage scaling steps.

Bug 841336

Change-Id: I51f91df857ab3df7d66fcee4cda21318cd3b23eb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/71738
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 17bf67cdbe05a2e6d01da1f5cae9e4c0b46bdf78)

ARM: tegra3: dvfs: Added DVFS entries

Added dvfs entries for automotive skus

Bug 883565, 882186

Change-Id: I6186b682fa82e24c3062bcbf5c2e5580fdf80562
Signed-off-by: Mohit Kataria<mkataria@nvidia.com>
Reviewed-on: http://git-master/r/70292
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
(cherry picked from commit 8a153df3004edf036ae72bf3704ea5b8df487cf9)

ARM: tegra: dvfs: Update Tegra3 xL speedo/nominal voltage

Updated Tegra3 xL core speedo and nominal voltage settings.
Re-factored nominal voltage selection, since new data introduced
dependency of core voltage on both CPU and core speedo id.

Bug 841336

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 3330ce743434866502fd6b33d7d1718ec4ab4675)
(cherry picked from commit a9fb4cbc865e78706c72186ebac286506cd5b301)

Change-Id: I244df08153a6a275a2fe331c72e03d03f18a8ea1
Reviewed-on: http://git-master/r/67014
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit 8b124e9e7d161dfcea6e1278cb9784b4244287b8)

ARM: tegra: dvfs: Tegra3 xL support - SKUs and speedos

Bug 841336

Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 92a342487a7bfe68d3c3366bbcd74c44a59f94d6)
(cherry picked from commit 5f0a23567f1acfd07325f324d41cea50eab84d80)

Change-Id: I793e427c7f738722786c6dd3d29411c75be50f93
Reviewed-on: http://git-master/r/67013
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
(cherry picked from commit b1ec9a21ece6b8d4e7eb95407eeb7b8d22f42f4b)

ARM: tegra: dvfs: Update Tegra3 x3 speedo thresholds

Bug 841336

Reviewed-on: http://git-master/r/64931
(cherry picked from commit 1333406b624bd876cd31cada142d234f4e18b303)
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>

Change-Id: Id62e0264962cd7511fc97e3c865f105ca10c65f0
Reviewed-on: http://git-master/r/65908
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 843d016218ff10ac4afe1f2895433a43c9ed117c)

ARM: tegra: dvfs: Update Tegra3 AP33 speedo thresholds

bugid 841336

Reviewed-on: http://git-master/r/62768
(cherry picked from commit 3784f31955117064d84868f8ade148ceffa32c3d)

Change-Id: Ic1759b2a18aa960f46767538c0fb7860cd40e422
Reviewed-on: http://git-master/r/64214
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Tested-by: Diwakar Tundlam <dtundlam@nvidia.com>
(cherry picked from commit 55f89ed3efa5e22a8a0a64c4653c9334c01107dc)

ARM: tegra: dvfs: Add Tegra3 xL CPU DVFS tables

Bug 841336

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit d98da0dcb175787a6c6a26c87b6f5ad84ab3da8b)
(cherry picked from commit 865746e6c5938db1d7517eca916033ee13e2d290)

Change-Id: Ie26a1ccafcf8455a9d4d93d0d4e2fc330f5162f6
Reviewed-on: http://git-master/r/66514
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
(cherry picked from commit 2853b4b1a517cadc9ada1acc86cd94579d1e2727)

ARM: tegra: dvfs: Update Tegra3 x3 CPU DVFS tables

Bug 841336

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 459a539b413bc34fa6bed54cc363b4a6ffbaff59)
(cherry picked from commit 470c3c4fad40a570dedfd51a52577fd4c91c5269)

Change-Id: I63214eaa437345bf7657f4c53a6dd73473e1e532
Reviewed-on: http://git-master/r/66513
Tested-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
(cherry picked from commit e68ded9f4238d8e3ae7d39ecd8b690b74bf5fad3)

ARM: tegra: dvfs: Add Tegra3 AP33 dvfs tables

Bug 841336

(cherry picked from commit b4cd14d5b9d1b2011a7752b6c52b3b64eb227cdb)
(cherry picked from commit 24cefb5d699db0a53b9fb3dd7cbe41de93c44e8e)

Change-Id: I080b04577697f31d9f9d4e96213630a28844a7db
Reviewed-on: http://git-master/r/63358
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
(cherry picked from commit 5450aae8c276aa237c859198d33ad613a1013b90)

ARM: tegra: clock: Support restricted PLLM usage

Added configuration option TEGRA_PLLM_RESTRICTED - when enabled,
PLLM - memory PLL - usage may be restricted to modules with dividers
capable of dividing maximum PLLM frequency at minimum voltage. When
disabled, PLLM is available as a clock source with no restrictions
(current configuration), which may effectively increase lower limit
for core voltage if high grade SDRAM is used.

Implemented PLLM restrictions in Tegra3 clock framework and DVFS, but
keep them disabled by default.

Bug 884419

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 5313ebcae92839146870d5865bc0f4cd08b35c61)
(cherry picked from commit 634647a9d2a8c1e03c8d98d0b2199950c947acc3)

Change-Id: I012452d92830ad6b63ec407350568b8c316b3caa
Reviewed-on: http://git-master/r/66512
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
(cherry picked from commit d55f645eb036427b04447964f82474502e257b58)

Conflicts:

	arch/arm/mach-tegra/Kconfig
	arch/arm/mach-tegra/tegra3_clocks.c

arm: tegra: power: Updated EDP table to latest spec

(see bug for Excel with the new spec)
Bug 844268

Change-Id: I7a3bdd674b987c2edd540de7764e01338f66c0ac
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/74094
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
(cherry picked from commit ab5e257a3f1a6af820b0942d1d3a152180ea6b17)

arm: tegra: power: Updated EDP table to latest spec

Changed 20C to 23C to account for hysteresis effect
Bug 844268

Change-Id: I11fca162db737e8cf81c31bf38575ecc42a730df
Signed-off-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-on: http://git-master/r/75049
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
(cherry picked from commit ccf0300d53b97fa9397f50c9ba1203d700e847de)

Change-Id: I1e30f731031831829e40df17ba388117fd5a184b
Signed-off-by: Danny Huang <dahuang@nvidia.com>
Reviewed-on: http://git-master/r/98195
Reviewed-by: Allen Martin <amartin@nvidia.com>

Conflicts:

	arch/arm/mach-tegra/Kconfig
	arch/arm/mach-tegra/board-cardhu.c
	arch/arm/mach-tegra/board-enterprise.c
	arch/arm/mach-tegra/cpu-tegra.c
	arch/arm/mach-tegra/edp.c
	arch/arm/mach-tegra/fuse.h
	arch/arm/mach-tegra/tegra3_clocks.c
	arch/arm/mach-tegra/tegra3_dvfs.c
	arch/arm/mach-tegra/tegra3_speedo.c
Revert "ARM: tegra: dvfs: Relax Tegra3 lower speedo limits"

This reverts commit 13af9b984539b6c5d4ae47e616bbcb78889e8969.
ARM: tegra: dvfs: Expand Tegra3 cpu dvfs tables

Expand Tegra3 cpu dvfs tables to add characterization results
for 800mV VDD_CPU.

Bug 817679
Bug 841336

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/77936
(cherry picked from commit f5b488019895c83e05ded8a8912cf3eb4eea5686)

Change-Id: Id7e5a46c96c67ca80f552b742cf3cf341bb8e1f0
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/80000
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>

Conflicts:

	arch/arm/mach-tegra/tegra3_dvfs.c
ARM: tegra: dvfs: Update Tegra3 CPU DVFS tables

Bug 817679
Bug 841336

Change-Id: I9a9d9e7a03b64774b1d2ebd8533be85582827515
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/71755
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>

Conflicts:

	arch/arm/mach-tegra/tegra3_clocks.c
	arch/arm/mach-tegra/tegra3_dvfs.c
ARM: tegra: dvfs: Update Tegra3 vdd_core floor

To properly account for voltage steps with 12.5mV resolution, moved
up by 25mV all thresholds in vdd_core floor calculation function, and
replaced "less than or equal" comparison with "less than".

Change-Id: I869ecabf4e25a268fbe279e54026d4fd1bf25db6
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/73903
Reviewed-by: Diwakar Tundlam <dtundlam@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-on: http://git-master/r/74558
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
Tested-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User

Conflicts:

	arch/arm/mach-tegra/tegra3_dvfs.c
ARM: tegra: dvfs: Add Tegra3 x7 CPU dvfs entries

Bug 841336
Reviewed-on: http://git-master/r/76912

Change-Id: I2806c8e4f08af49edf57f00a43438b1503d6aedb
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78706
Reviewed-by: Automatic_Commit_Validation_User

Conflicts:

	arch/arm/mach-tegra/tegra3_dvfs.c