i965: create code path to handle primitive restart in hardware

For newer hardware we disable the VBO module's software handling
of primitive restart. We now handle primitive restarts in
brw_handle_primitive_restart.

The initial version of brw_handle_primitive_restart simply calls
vbo_sw_primitive_restart, and therefore still uses the VBO
module software primitive restart support.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
i965: add flag to enable cut_index

When brw->prim_restart.enable_cut_index is set, the cut index
will be enabled when uploading index_buffer commands.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
i965: use cut index to handle primitive restart when possible

If the primitive restart index and the primitive type can
be handled by the cut index feature, then use the hardware
to handle the primitive restart feature.

The VBO module's software handling of primitive restart is
used as a fall back.

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
mesa: Remove the OES_draw_texture extension from ES2.

This extension appears to be written against ES 1.0.
In ES 2.0, you really want to be using FBOs instead.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
i965: Gut the separate OpenGL ES extension enabling.

We should just set the bits of functionality that we support; the
GL/ES1/ES2 flags in extensions.c will take care of advertising the
appropriate extensions for the current API.

This enables the GL_EXT_texture_compression_dxt1 extension on ES1/ES2
when libtxc_dxtn is installed or the force_s3tc driconf option is set.
The main extension code set this up properly, but the ES-specific code
failed to do so.

Otherwise, the extension strings reported by es1_info, es2_info, and
glxinfo all remain the same.

This patch manually disables the ARB_framebuffer_object bit on ES
to preserve the behavior of 1c0f5d8324c4db2720247989ddc4a45315b55a85.

v2: Rebase, fix the i915 Makefile, and unconditionally set the
    OES_draw_texture bit as core Mesa will only apply it to ES1 now.

Tested-by: Daniel Charles <daniel.charles@intel.com> [v1]
Reviewed-by: Chad Versace <chad.versace@linux.intel.com> [v1]
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
tgsi: Initialize Padding struct fields.

Fix uninitialized scalar variable defects report by Coverity.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
i965/msaa: Expand odd-sized MSAA surfaces to account for interleaving pattern.

Gen6 MSAA buffers (and Gen7 MSAA depth/stencil buffers) interleave
MSAA samples in a complex pattern that repeats every 2x2 pixel block.
Therefore, when allocating an MSAA buffer, we need to make sure to
allocate an integer number of 2x2 blocks; if we don't, then some of
the samples in the last row and column will be cut off.

Fixes piglit tests "EXT_framebuffer_multisample/unaligned-blit {2,4}
color msaa" on i965/Gen6.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
i965/blorp: Generalize sampling code in preparation for Gen7

This patch generalizes the function
brw_blorp_blit_program::texture_lookup() so that it prepares the
arguments to the sampler message based on a caller-provided array
rather than assuming the argument order is always (u, v).

This paves the way for the messages we will need to use in Gen7, which
use argument orders (u, lod, v) and (si, u, v) (si=sample index).

It will also will allow us to read from arbitrary sample indices on
Gen6, by supplying the arguments (u, v, r, lod, si) to the SAMPLE_LD
message instead of just (u, v).

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/blorp: Emit sample index in SAMPLE_LD message when necessary

This patch modifies the function brw_blorp_blit_program::texel_fetch()
to emit the SI (sample index) argument to the SAMPLE_LD message when
reading from a sample index other than zero.

Previously we were using the ugly hack of configuring multisampled
source surfaces as single-sampled, and accessing sample indices other
than zero by swizzling the texture coordinates in the WM program.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/blorp: Use MSDISPMODE_PERSAMPLE rendering when necessary

This patch modifies the "blorp" WM program so that it can be run in
MSDISPMODE_PERSAMPLE (which means that every single sample of a
multisampled render target is dispatched to the WM program, not just
every pixel).

Previously we were using the ugly hack of configuring multisampled
destination surfaces as single-sampled, and generating sample indices
other than zero by swizzling the pixel coordinates in the WM program.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
i965/blorp: Factor gen6_blorp_emit_batch_head into separate functions.

This patch separates out the portions of gen6_blorp_emit_batch_head()
that emit 3DSTATE_MULTISAMPLE, 3DSTATE_SAMPLE_MASK, and
STATE_BASE_ADDRESS.  This paves the way for making the blorp code work
on Gen7, where additional command packets
(3DSTATE_PUSH_CONSTANT_ALLOC_VS and 3DSTATE_PUSH_CONSTANT_ALLOC_PS)
need to be emitted before 3DSTATE_MULTISAMPLE.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/blorp: Set the dynamic state upper bound.

We know from previous bug fixes (commits
c25e5300cba7628b58df93ead14ebc3cc32f338c and
b2ace06cbbbb1021e2d7ace12a985c6406821939) that texture border color
doesn't work if the dynamic state upper bound is set to 0.  Although
the blorp engine doesn't make use of texture borders, it seems like we
ought to err on the safe side and set this value properly.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/blorp: Allocate space for push constants on Gen7.

On Gen7, push constants for shader programs are stored in the URB, so
blorp code needs to set aside space for them.  This was previously
unnecessary because blorp code was based on HiZ operations, which
don't require any shaders.

This patch adds a call from gen7_blorp_exec() to
gen7_allocate_push_constants(), to ensure that push constants are
assigned the correct location in the URB.  It also extracts a new
function gen7_emit_urb_state() from gen7_upload_urb(), which is
re-used by gen7_blorp_emit_urb_config() to ensure that the URB regions
used by all the pipeline stages leave room for the push constants.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/blorp: Use 16 pixel dispatch on Gen7.

Gen7 hardware requires us to enable at least one WM dispatch mode,
even if there is no program being dispatched to.  When this code was
only used for HiZ operations (which don't use a WM program), we used
32-pixel dispatch, because it didn't matter.  But blit programs are
compiled for 16-pixel dispatch.  So just enable 16-wide dispatch
unconditionally.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

v2: Enable 16-wide dispatch unconditionally rather than add the
unnecessary complication of using 32-wide dispatch when there is no WM
program.
i965/blorp: Implement proper texel fetch messages for Gen7.

On Gen6, texel fetch is always accomplished using the SAMPLE_LD
message, which accepts arguments (u, v, r, lod, si).  On Gen7, there
are two* texel fetch messages: SAMPLE_LD for non-MSAA surfaces, taking
arguments (u, lod, v), and SAMPLE_LD2DSS for MSAA surfaces, taking
arguments (si, u, v).

*Technically, there are other texel fetch messages, but they are used
for "compressed" MSAA surfaces, which we don't yet support.

This patch adds the proper message types and argument orderings for
Gen7.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/blorp: Enable blorp blits on Gen7.

Gen7 support for blorp (blits using the render bath) now works for
non-MSAA purposes.  This patch enables it.

Since blorp operations re-use the logic for HiZ ops, this required
adding a case to the switch statement in gen7_blorp_emit_wm_config(),
to allow for the case where no HiZ op is being performed.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/msaa: Add defines for Gen7.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/msaa: Properly handle sliced layout for Gen7.

Starting in Gen7, there are two possible layouts for MSAA surfaces:

- Interleaved, in which additional samples are accommodated by scaling
  up the width and height of the surface.  This is the only layout
  available in Gen6.  On Gen7 it is used for depth and stencil
  surfaces only.

- Sliced, in which the surface is stored as a 2D array, with array
  slice n containing all pixel data for sample n.  On Gen7 this layout
  is used for color surfaces.

The "Sliced" layout has an additional requirement: it must be used in
ARYSPC_LOD0 mode, which means that the surface doesn't leave any extra
room between array slices for miplevels other than 0.

This patch modifies the surface allocation functions to use the
correct layout when allocating MSAA surfaces in Gen7, and to set the
array offsets properly when using ARYSPC_LOD0 mode.  It also modifies
the code that populates SURFACE_STATE structures to ensure that
ARYSPC_LOD0 mode is selected in the appropriate circumstances.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/msaa: Validate Gen7 surface state constraints.

When a Gen7 SURFACE_STATE is configured for MSAA, a number of
additional constaints come in to play.  This patch adds a function
gen7_check_surface_setup() which verifies that all of those
constraints are met.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/msaa: Modify blorp code to account for Gen7 MSAA layouts.

Since blorp uses color textures and render targets to do all its work
(even when blitting stencil and depth data), it always has to
configure the Gen7 GPU to use the new "sliced" MSAA layout.  However,
when blitting stencil or depth data, the actual MSAA layout is
interleaved (as in Gen6).  Therefore, blorp has to do extra coordinate
transformation work to account for the interleaving manually.

This patch causes blorp to perform the necessary extra coordinate
transformations.

It also modifies the blorp SURFACE_STATE setup code for Gen7, so that
it does not try to correct the surface width and height to account for
MSAA, since "sliced" MSAA layout doesn't affect the surface width or
height.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>