RT78940 Changes CONFIG_HOSTNAME to a2f-som for the SmartFusion SOM.
RT78988. k70-som: Support MT46H32M16LFBF-6 LPDDR part

Modify timings to support -6 LPDDR parts along with -5 parts.
RT #74765. Minor comment update.
RT #74766. Moved local MCG definitions from clock.c to kinetis.h since they
 are used in cmd_somtest.c module.
RT #79065. Fixed u-boot.hex build procedure for LPC178X targets.
RT77788. k70-som: Add build-time parameters CONFIG_KINETIS_{K61,K70} to define MCU family

These strings will follow the selection of CONFIG_KINETIS_K61 or
CONFIG_KINETIS_K70:
 1. Hostname;
 2. U-Boot prompt;
 3. `platform_kinetis=[...]` in kernel parameters line;
 4. Board name.
RT77788. k70-som: Limit NFC clock rate to 19.23MHz

Increase NFC clock divider to put the NFC clock below rate limit.

The maximum NFC clock rate (19.23MHz) was calculated as follows:

 1. Assume we do not use NFC fractional divider, for simplicity.

 2. Look at the "RANDOM DATA READ" diagram on page 86 of the NAND flash
datasheet 5277m68a_1gb_nand.pdf and find out that data appear tREA
nanoseconds after RE# goes low. tREA is 16ns, according to the Table 23:
AC Characteristics: Norman Operation (3.3V) from page 78 of the NAND
flash datasheet 5277m68a_1gb_nand.pdf .

 3. Look at "Figure 14. Read data latch cycle timing in non-fast mode"
on page 42 of the MCU datasheet K70P256M120SF3.pdf and find out that
RE# must go high no later than
tIS nanoseconds after the data has appeared. tIS is 11ns for both
120MHz- and 150MHz-limited K70 MCUs, see NFC specifications in the MCU
datasheets: K70P256M120SF3.pdf and K70P256M150SF3.pdf.

 4. Therefore the minimum RE# low pulse width is tREA + tIS = 16ns +
11ns = 27ns.

 5. From the table Table 24. NFC specifications from the MCU datasheet
K70P256M150SF3.pdf we can calculate the minimum
T_L: NFC_RE# pulse width minimum value is T_L + 1 and is also 27ns, as
already calculated. Therefore minimum T_L is 26ns.

 6. Since we assume the NFC clock divider to be integer, the NFC clock
duty cycle is 50%, therefore T_L is half of the clock cycle. Maximum NFC
clock rate is therefore 1.0/2/26ns = 0.01923 GHz = 19.23 MHz.
RT77788. k70-som: Do not initialize LCD clock on Kinetis K61

Kinetis K61 does not have an LCD controller.
RT77788. k70-som: Support both 120MHz and 150MHz K61/K70 MCUs

 * Add build-time U-Boot option CONFIG_KINETIS_120MHZ or
CONFIG_KINETIS_150MHZ to define the maximum core clock rate of the MCU.
 * Use different PLL configurations to reach to maximum clock rates and
performance.
 * Use different LPDDR timings depending on the clock rate.
 * Use different clock dividers for internal flash and external NAND
flash, as required by the respective datasheets.
RT77788: twr-k70f120m: Fix build (define build-time parameter CONFIG_KINETIS_120MHZ)

Either CONFIG_KINETIS_120MHZ or CONFIG_KINETIS_150MHZ must be defined.
The TWR-K70F120M board has a 120MHz K70 MCU.
RT79078. kinetis: Use external oscillator for PLL clock source on K70-SOM

 * Use external oscillator at EXTAL1/XTAL1 as clock source for the main
PLL on K70-SOM.
 * Do not change clock configuration for TWR-K70F120M.
RT79078. k70-som: Enable and use the RTC clock for FLL when switching to FBE mode

 * In order to switch the MCG to the PLL Engaged External mode (PEE
mode), it must pass the FLL Bypassed External mode (FBE mode) as an
intermediate step. See section `25.4.1 MCG Mode State Diagram` on page
656 of the K70 Reference Manual.
 * Enable and use the RTC clock for FLL when switching to the
FLL Bypassed External mode (FBE mode). We do this in `clock_fei_to_fbe()`
in `u-boot/cpu/arm_cortexm3/kinetis/clock.c` before switching to
the FBE mode. This is required, because:
   * In order to switch to the PLL Engaged External mode (PEE mode), we
must pass the FLL Bypassed External mode (FBE mode).
   * This FBE mode requires that there is a working FLL reference clock.
   * Only OSC0 clock (clock or oscillator at EXTAL0/XTAL0) or RTC clock
(oscillator at EXTAL32/XTAL32) can be used as reference clock for FLL.
   * In the K**-SOM/DNI-ETH configuration, nothing is connected to
EXTAL0, therefore we have to use the RTC clock as reference clock
for FLL in the FBE mode.
 * Use RTC for FLL reference clock only on K**-SOMs, but not for
TWR-K70F120M. To do that, we add a new U-Boot configuration option
`KINETIS_FLLREF_RTC` that will control usage of RTC for FLL reference
clock and define this configuration option only in
`u-boot/include/configs/k70-som.h`.
 * Use in-MCU 20pF oscillator load.