Belatedly address some code review from Chris.

As a side note, I really dislike array_pod_sort... Do we really still
care about any STL implementations that get this so wrong? Does libc++?

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153834 91177308-0d34-0410-b5e6-96231b3b80d8
Emit the LLVM<->DWARF register mapping as a sorted table and use binary search to do the lookup.

This also avoids emitting the information twice, which led to code bloat. On i386-linux-Release+Asserts
with all targets built this change shaves a whopping 1.3 MB off clang. The number is probably exaggerated
by recent inliner changes but the methods were already enormous with the old inline cost computation.

The DWARF reg -> LLVM reg mapping doesn't seem to have holes in it, so it could be a simple lookup table.
I didn't implement that optimization yet to avoid potentially changing functionality.

There is still some duplication both in tablegen and the generated code that should be cleaned up eventually.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153837 91177308-0d34-0410-b5e6-96231b3b80d8
Use SequenceToOffsetTable to create instruction name table. Saves space particularly on X86 where AVX instructions just add a 'v' to the front of other instructions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153841 91177308-0d34-0410-b5e6-96231b3b80d8
Add instruction itinerary for the PPC64 A2 core.

This adds a full itinerary for IBM's PPC64 A2 embedded core. These
cores form the basis for the CPUs in the new IBM BG/Q supercomputer.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153842 91177308-0d34-0410-b5e6-96231b3b80d8
Use full anti-dep. breaking with post-ra sched. on the embedded ppc cores.

Post-RA scheduling gives a significant performance improvement on
the embedded cores, so turn it on. Using full anti-dep. breaking is
important for FP-intensive blocks, so turn it on (just on the
embedded cores for now; this should also be good on the 970s because
post-ra scheduling is all that we have for now, but that should have
more testing first).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153843 91177308-0d34-0410-b5e6-96231b3b80d8
Add ppc440 itin. entries for LdStSTD*

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153844 91177308-0d34-0410-b5e6-96231b3b80d8
Set the default PPC node scheduling preference to ILP (for the embedded cores).

The 440 and A2 cores have detailed itineraries, and this allows them to be
fully used to maximize throughput.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153845 91177308-0d34-0410-b5e6-96231b3b80d8
Fix typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153846 91177308-0d34-0410-b5e6-96231b3b80d8
This commit contains a few changes that had to go in together.

1. Simplify xor/and/or (bitcast(A), bitcast(B)) -> bitcast(op (A,B))
   (and also scalar_to_vector).

2. Xor/and/or are indifferent to the swizzle operation (shuffle of one src).
   Simplify xor/and/or (shuff(A), shuff(B)) -> shuff(op (A, B))

3. Optimize swizzles of shuffles:  shuff(shuff(x, y), undef) -> shuff(x, y).

4. Fix an X86ISelLowering optimization which was very bitcast-sensitive.

Code which was previously compiled to this:

movd    (%rsi), %xmm0
movdqa  .LCPI0_0(%rip), %xmm2
pshufb  %xmm2, %xmm0
movd    (%rdi), %xmm1
pshufb  %xmm2, %xmm1
pxor    %xmm0, %xmm1
pshufb  .LCPI0_1(%rip), %xmm1
movd    %xmm1, (%rdi)
ret

Now compiles to this:

movl    (%rsi), %eax
xorl    %eax, (%rdi)
ret




git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153848 91177308-0d34-0410-b5e6-96231b3b80d8
Add LdStSTD* itin. for the PPC64 A2 core.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153850 91177308-0d34-0410-b5e6-96231b3b80d8
Enable prefetch generation on PPC64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153851 91177308-0d34-0410-b5e6-96231b3b80d8
Fix some 80-col. violations I introduced with the A2 PPC64 core.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153852 91177308-0d34-0410-b5e6-96231b3b80d8
Start cleaning up the InlineCost class. This switches to sentinel values
rather than a bitfield, a great suggestion by Chris during code review.

There is still quite a bit of cruft in the interface, but that requires
sorting out some awkward uses of the cost inside the actual inliner.

No functionality changed intended here.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153853 91177308-0d34-0410-b5e6-96231b3b80d8
Use SequenceToOffsetTable to generate instruction name table for AsmWriter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153857 91177308-0d34-0410-b5e6-96231b3b80d8
It could come about that we parse the inline ASM before we get a potential
definition for it. In that case, we want to wait for the potential definition
before we create a symbol for it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153859 91177308-0d34-0410-b5e6-96231b3b80d8
Make MCInstrInfo available to the MCInstPrinter. This will be used to remove getInstructionName and the static data it contains since the same tables are already in MCInstrInfo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153860 91177308-0d34-0410-b5e6-96231b3b80d8
Fix CXXFLAGS for huge_val.m4.

Patch by Jeremy Huddleston!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153862 91177308-0d34-0410-b5e6-96231b3b80d8
Remove getInstructionName from MCInstPrinter implementations in favor of using the instruction name table from MCInstrInfo. Reduces static data in the InstPrinter implementations.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153863 91177308-0d34-0410-b5e6-96231b3b80d8
Optimizing swizzles of complex shuffles may generate additional complex shuffles.

Do not try to optimize swizzles of shuffles if the source shuffle has more than
a single user, except when the source shuffle is also a swizzle.






git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153864 91177308-0d34-0410-b5e6-96231b3b80d8
Reorder fields in MatchEntry and OperandMatchEntry to reduce padding. A bit tricky due to the target specific sizes for some of the fields so the ordering is only optimal for the targets in the tree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153865 91177308-0d34-0410-b5e6-96231b3b80d8