Cleaned up imports and language extensions.
Updated cabal file.

No versions included on added libraries for now.
(BROKEN HERE) Redesigned structure of RTL.

(Due to a large amount of interdependency between the latest changes
I have ended up implementing them in the working directory. In order
to avoid a huge commit, I will make a series of partial (broken)
commits.)

- Reseparated wires. Merging blocks was a good idea, but combs
  make more sense as a separate concept.
- Removed blocking assign from Block, and restructured conditional
  updates to use hierarchical Maps.
Added Monoid instance for RTL.
Removed emptyRTL, since RTL is now a Monoid.
Made Circuit a newtype Monad.

- This allows it to be used with mtl Monad transformers without
  conflicts.
Changed interface to match the new RTL structure.

- newVariable replaced with newRef, which just generates a unique reference.
- newWire no longer binds an expression at creation. This avoids dealing
  with an unnecessay Maybe value in RTL. (Binding will be readded later)
- newReg just fixed to work with the Circuit newtype.
Replaced addStmt with Statement monad, and onTrigger.

The Statement monad is just a Writer of RTL's Block type. This allows
nested conditional blocks of multiple updates to be composed easily.
onTrigger then composes this block with any existing one at the same
Trigger.
NOTE: Write conflicts are not currently checked for in any way.
Removed always Trigger, since combs are no longer Blocks.
Replaced Logic newtype with Readable typeclass.

Readable has one method read, which returns an Expr. This name conflicts
with Prelude.read, but for now I don't see a better alternative.
The class is defined with multiple parameters in order to support some
more complex types it is defined for later, which don't have Kind *->*

readWire and readReg (and rd) are replaced by Readable instances.

(comb is only removed here for structural reasons, it is redefined
later in the finished file)
Added Bindable class for binding Wires.

Operator name (=:) may be changed.
Added Writable typeclass for writing to registers.
Added Signal newtype to wrap raw Exprs for type safety.

This gives functions which compose Readable values a read only phantom
typed wrapper to return their results inside.

Readable may be changed to access a Signal in future, as the untyped
Expr sometimes causes type inference problems.

readSignal exists to avoid these problems in some places.
Added Constant newtype and readInteger to support literals.

fromInteger converts literals to BitVectors and wraps them in the
Constant newtype. This allows them to be Readable while also allowing
functions that want to take numeric values to use them.

TODO: This should probably be replaced with (Integral i => Readable i i).
Fixed literal, binOp and unOp to use Readable.
Modified Boolean functions to use Readable.

Since we want to be able to compose Readable values which may not be the
same type, the types provided by Boolean are no longer appropriate, and
have been replaced.
Replaced Num instance with a new class Arith.

We want to be able to compose Readable values of different types, but
the signature of Num does not allow this. Additionally, we would like
better control over what types can be added, and how.

The default implementations assume the wires carry twos-complement
integers and can be added directly in Verilog.

An instance for Int is included.
Readded comb, fixed to use Readable.
Added iff function for creating conditional Statments.

This should really be in Logic, but Readable is not defined there, this
likely means some restructuring will need to be done soon.
Added Readable and Bindable instances for InputWire/OutputWire.

These instances are what restrict their relevant actions to the
appropriate side of an interface.