Revert "arm: tegra3: change min_rate for clocks"

This reverts commit 5dc206986103aaa443fa6b0ef6fef20bcb35d299 because
it causes noisy audio playback on Tegra3 platforms with secure-os.

Bug 939415

Change-Id: Ib19962dd57a2560945d1c0ed49b3eade2c751446
Signed-off-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-on: http://git-master/r/98986
Reviewed-by: Automatic_Commit_Validation_User
arm: tegra: Update pinmux setting for nct alert

Set KB_ROW11 pin to default PULL_UP to fix
the excessive interrupts from nct alert.

Bug 973536

Change-Id: Idab3769f3fe1945f5e0f487f7bd23a7c0b58d5d1
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/99339
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
Tested-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Hunk Lin <hulin@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
GVS: Gerrit_Virtual_Submit
ARM: tegra: clock: Add DSI implicit dependency on PLLP

Added dsi fixed clock entry derived from PLLP_OUT3. This would allow
DC driver to properly ref-count implicit dependency of DSI operations
on PLLP_OUT3 clock.

Bug 933653

Change-Id: I71e6ada13f9d231c5a4924f345cdbf7cf05cd59e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/98103
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
video: tegra: dsi: Ref-count pllp_out3 clock in DSI.

Bug 933653

Change-Id: If7ce4dc5129782a7e3487028d2dba01c9380ba90
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Reviewed-on: http://git-master/r/98256
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Reviewed-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
gpio: tegra: implement gpio_request and gpio_free.

Recent pinctrl discussions concluded that gpiolib APIs
should in fact do whatever is required to mux a GPIO onto
pins.
This change is based on the work done by Stephen Warren in mainline
kernel.
-----
commit 3e215d0a19c2a0c389bd9117573b6dd8e46f96a8

    gpio: tegra: Hide tegra_gpio_enable/disable()

    Recent pinctrl discussions concluded that gpiolib APIs should in fact do
    whatever is required to mux a GPIO onto pins, by calling pinctrl APIs if
    required. This change implements this for the Tegra GPIO driver, and removes
    calls to the Tegra-specific APIs from drivers and board files.
----

Change-Id: I482ea5c177cf2ee6fa06ddac48b556f1508efacb
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/98466
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
arm: tegra: enterprise: Set gpio LCD_D8 to tristate

LCD_D8 used for BAT_REMOVAL staus from PMU to be
programmed as input/tristate to in line with hardware
schematics. It is connected VIO_IN

Bug 955519
(Cherry picked from I692d8d805c54da3996c33b9837b197a6995689c8)
Change-Id: I68e6566249675cd5fce8aa954983478e4fc29a4c
Reviewed-On: http://git-master/r/#change,91589
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
Reviewed-on: http://git-master/r/99742
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
ARM: tegra: power: Enforce CPU rate range in min cpu notifier

On Tegra3 make sure cpu rate is within G-mode range before LP to G
mode switch triggered by minimum CPUs notifier.

Bug 964208

Change-Id: Ic4ee6bc7eca5ad0902da4907e4702f296a155280
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/99834
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Revert "video: tegra: dc: Set default videomode"

This reverts commit 9349cedf17f9b3c10760c8d48f831473f87a3a15.

It is reviewed on http://git-master/r/99635
It will cause HDMI power ON and emc clock bump up to 667Mhz
after resume from LP0.

bug 930136

Change-Id: I130494fdb381b3d322ac0e3fc8be2e44f2c2d7a7
Signed-off-by: Hunk Lin <hulin@nvidia.com>
Reviewed-on: http://git-master/r/100202
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
ARM: tegra: whistler: Add slave address for i2c driver

Configuring all i2c controller to have slave addresss to 0xFC
(unused slave address) to avoid responding the slave with general
call address.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/91951

Change-Id: Id1a45f46cfc5ffa3a48b01c0bae71c4ee9ab699b
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/100259
Reviewed-by: Automatic_Commit_Validation_User
ARM: tegra: ventana: Set drive strength to max for all i2c pins

Setting drive strength to maiximum for all i2c pins.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/91952

Change-Id: I8882dd238af34e06c924f2e160d0897111e8103d
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/100260
Reviewed-by: Automatic_Commit_Validation_User
ARM: tegra: whistler: Set I2c pin drive strength to max

Setting i2c drive strenth to maximum and pulling all pins
to high.
bug 951052
bug 958415
bug 927583

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/91805

Change-Id: Ia2bf4ccba6d4c47411e59fb9567dc4e3c2db76ae
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/100261
Reviewed-by: Automatic_Commit_Validation_User
ARM: tegra: enterprise: register supply regulator before child regulator

LDO3 has the input from the VIO output and hence VIO should be
register before LDO3 for regulator registration.

bug 976254

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/99446

Change-Id: I6771af3e7eb93886e974695ab3550cdf8ebc52c4
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/100262
Reviewed-by: Automatic_Commit_Validation_User
mfd: tps80031: fix missed irq issue

We found missed irq could be happened if clear all INT_STS_x register in one time.
Shadow register pushes the irq status after the first byte of INT_STS_x was cleared
The proposed way to clear interrupt is to write only one INT_STS_x register.
It will also clear the other two ones.

Bug 952476

Reviewed-on: http://git-master/r/93453
Signed-off-by: Steve Kuo <stevek@nvidia.com>

(cherry picked from commit 0c92f32e9e03defaeac991518b26134e59ef4db6)

Change-Id: I76179be4847f59a1687926b9b0dde6ebd3f58aa4
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-on: http://git-master/r/100306
ARM: tegra2: clock: Put Tegra2 clocks to known states

Add TEGRA_PREINIT_CLOCKS option to put host1x, disp1, and video clocks
into known state, so that L4T Ventana/Harmony works on u-boot.

bug 967065

Change-Id: If7637b13e0daf1823fa0fe694a87870f4601e4df
Signed-off-by: Jong Kim <jongk@nvidia.com>
Reviewed-on: http://git-master/r/95734
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
dmaengine/dma_slave: fix merge issue.

Change-Id: I0931f4ef7a5464dd32d8c703288a137fc77857ce
Signed-off-by: Linqiang Pu <dpu@nvidia.com>
Reviewed-on: http://git-master/r/100090
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
arm: tegra: Implement safe option for T30 pinmux

Bug 950086

Change-Id: I2eb129566bfea83b9a73d29f0c6443bdab087b65
Signed-off-by: Ashwini Ghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/95518
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Andy Park <andyp@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
ARM: errata: 716044: an uncacheable load multiple can cause a deadlock.

Under some rare circumstances, an uncacheable load multiple
instruction (LDRD, LDM, VLDM, VLD1, VLD2, VLD3, VLD4) can cause
a processor deadlock.

Change-Id: Ibd79aa8182dce37d0be9892f2310735e1123618a
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/95914
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
ARM: tegra: Enable ARM errata 716044 for Tegra2.

Change-Id: Id71da6f6371f337f913d981f6d121c3fb2561a41
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/95915
Reviewed-by: Varun Colbert <vcolbert@nvidia.com>
Tested-by: Varun Colbert <vcolbert@nvidia.com>
media: video: tegra: ov5650: read sensor fuse id

The sequence of read fuse id is:

1. write to OTP index register 0x3d00.
2. read out byte from ox3d04.
3. repeat step 1 to the next byte with its index respectively.

also fixed ov5650_read_reg always fail issue.

bug 957657

Change-Id: I649a7765320d0d4be8111a7f523d8487b872b620
Signed-off-by: Charlie Huang <chahuang@nvidia.com>
Reviewed-on: http://git-master/r/98330
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Wei Chen <wechen@nvidia.com>
Reviewed-by: Frank Chen <frankc@nvidia.com>
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
ARM: tegra: enterprise: Limit holdoff set for 533MHz

Bug 935079

Signed-off-by: Ray Poudrier <rapoudrier@nvidia.com>
Reviewed-on: http://git-master/r/86009
(cherry picked from commit 83eb3734f76e598d570dd9624e7e06f8b3e05afe)

Change-Id: I5911670e7c1e8dd5fc4e89d4be21b9dcbc4c9085
Reviewed-on: http://git-master/r/98535
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Raymond Poudrier <rapoudrier@nvidia.com>
Tested-by: Raymond Poudrier <rapoudrier@nvidia.com>