Temporarily turn off anti-dependency checking
during Post RA scheduling in X86,
until the X86 target is changed to properly set up
post RA liveness.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154874 91177308-0d34-0410-b5e6-96231b3b80d8
ARM two-operand forms for vhadd and vhsub instructions.

rdar://11252521

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154875 91177308-0d34-0410-b5e6-96231b3b80d8
Disable the atom scheduling test after r154874 broke it.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154877 91177308-0d34-0410-b5e6-96231b3b80d8
Make comment here more clear.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154878 91177308-0d34-0410-b5e6-96231b3b80d8
Typo.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154879 91177308-0d34-0410-b5e6-96231b3b80d8
Tidy up. 80 columns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154881 91177308-0d34-0410-b5e6-96231b3b80d8

temporarily XFAIL this test until post RA
live-ins is properly enabled.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154882 91177308-0d34-0410-b5e6-96231b3b80d8
Fix ARM disassembly of VLD2 (single 2-element structure to all lanes)
instructions with writebacks. And add test a case for all opcodes handed by
DecodeVLD2DupInstruction() in ARMDisassembler.cpp .


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154884 91177308-0d34-0410-b5e6-96231b3b80d8
Don't tag libcxx and libcxxabi since we don't release them just yet.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154889 91177308-0d34-0410-b5e6-96231b3b80d8
Add a stub for block placement pass. This needs fleshing out w/ details
about what folks should expect w.r.t. the new algorithm.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154891 91177308-0d34-0410-b5e6-96231b3b80d8
Add a stub about the inline cost rewrite.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154892 91177308-0d34-0410-b5e6-96231b3b80d8
Update woefully stale credits entry. Everything listed there had been
re-done by wiser souls.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154894 91177308-0d34-0410-b5e6-96231b3b80d8
Typo in an unused field.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154895 91177308-0d34-0410-b5e6-96231b3b80d8
SlotIndexes used to store the index list in a crufty custom linked-list. I can't
for the life of me remember why I wrote it this way, but I can't see any good
reason for it now. This patch replaces the custom linked list with an ilist.

This change should preserve the existing numberings exactly, so no generated code
should change (if it does, file a bug!).



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154904 91177308-0d34-0410-b5e6-96231b3b80d8
Download and build the compiler-rt project.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154905 91177308-0d34-0410-b5e6-96231b3b80d8
Don't decode vperm2i128 or vperm2f128 into a shuffle if bit 3 or 7 of the immediate is set.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154907 91177308-0d34-0410-b5e6-96231b3b80d8
Test cases that assume layout should use -disable-code-place.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154908 91177308-0d34-0410-b5e6-96231b3b80d8
Revert "SCEV: When expanding a GEP the final addition to the base pointer has NUW but not NSW."

This isn't right either, reverting for now.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154910 91177308-0d34-0410-b5e6-96231b3b80d8
Fix bad EXTRACT_SUBREG in instruction selection for extending-loads on NEON.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154915 91177308-0d34-0410-b5e6-96231b3b80d8
Unbreak the MSVC build, that next() thing again.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@154916 91177308-0d34-0410-b5e6-96231b3b80d8