Remove expired dns cache entries before removing oldest

A suggestion how to make a smarter delete function when the cache
is full. First look through the entire cache and remove all entries
which have expired. If none use the old solution and just remove
the last entry in the MRU list.

Change-Id: I5f997ab35290a55dc6e1ddf37d725759edf83d36
Update s_fabsl.c to upstream head.

Bug: http://code.google.com/p/android/issues/detail?id=29539
Change-Id: I843dcfcbfe49e8e9f43c49aae6ade1edb57a3053
Merge "Update s_fabsl.c to upstream head."
MIPS support to libm, libdl and libthread_db

Change-Id: I9106721af7fe0cd45df82976250db0d300a20117
Signed-off-by: Raghu Gandham <raghu@mips.com>
Merge "MIPS support to libm, libdl and libthread_db"
Adjust memcpy for ARM Cortex A9 cache line size

ARM Cortex A8 use 64 bytes and ARM Cortex A9 use 32 bytes cache line
size.

The following patch:
  Adds code to adjust memcpy cache line size to match A9 cache line
  size.
  Adds a flag to select between 32 bytes and 64 bytes cache line
  size.

  Copyright (C) ST-Ericsson SA 2010
    Modified neon implementation to fit Cortex A9 cache line size
    Author: Henrik Smiding henrik.smiding@stericsson.com for
            ST-Ericsson.

Change-Id: I8a55946bfb074e6ec0a14805ed65f73fcd0984a3
Signed-off-by: Christian Bejram <christian.bejram@stericsson.com>
Merge "Adjust memcpy for ARM Cortex A9 cache line size"
Merge "Remove expired dns cache entries before removing oldest"
bionic: fix integer overflows in chk_malloc(), leak_malloc(), and leak_memalign()

The allocation size in chk_malloc(), leak_malloc(), and leak_memalign()
functions may be rounded up to a small value, leading to buffer overflows.
The code only runs in debugging mode.

This patch complements commit 6f04a0f4 (CVE-2009-0607).

Change-Id: Id899bcd2bcd2ea2205e5753c433390710032dc83
Signed-off-by: Xi Wang <xi.wang@gmail.com>
Merge "bionic: fix integer overflows in chk_malloc(), leak_malloc(), and leak_memalign()"
Let pthread_create fail if schedparam can't be set

The creation of a thread succeeds even if the requested scheduling
parameters can not be set. This is not POSIX compliant, and even
worse, it leads to a wrong behavior. Let pthread_create() fail in this
case.

Change-Id: Ice66e2a720975c6bde9fe86c2cf8f649533a169c
Signed-off-by: Christian Bejram <christian.bejram@stericsson.com>
Merge "Let pthread_create fail if schedparam can't be set"
Cherry-pick "generate PIC code".

Change-Id: I7d5f2e5663df263493f65e364c959e663fc4d13a
Merge "Cherry-pick "generate PIC code"."
bionic/x86: Optimization for memcpy

Signed-off-by: Liubov Dmitrieva <liubov.dmitrieva@intel.com>
Signed-off-by: H.J. Lu <hongjiu.lu@intel.com>
Signed-off-by: Wei A Jin <wei.a.jin@intel.com>
Signed-off-by: Jack Ren <jack.ren@intel.com>
Signed-off-by: Bruce Beare <bruce.j.beare@intel.com>

Conflicts:

	libc/arch-x86/string/ssse3-memcpy5.S

Change-Id: I41e70d1d19d5457e65c89b64da452fbdaf3a00a7
Implement the "abort" stub in assembly for ARM.

So that we can always get the full stack trace regardless of gcc's handling
of the "noreturn" attribute associated with abort().

(Cherry pick of Id264a5167e7cabbf11515fbc48f5469c527e34d4.)

Bug: 6455193

Conflicts:

	libc/Android.mk

Change-Id: I568fc5303fd1d747075ca933355f914122f94dac
Merge "Implement the "abort" stub in assembly for ARM."
pthread: Invalidate stale stack pointers on pthread_exit()

A call to pthread_key_delete() after pthread_exit() have unmapped the stack of a thread
but before the ongoing pthread_join() have finished executing will result in an access
to unmapped memory.
Avoid this by invalidating the stack_base and tls pointers during pthread_exit().

This is based on the investigation and proprosed solution by
Srinavasa Nagaraju <srinavasa.x.nagaraju@sonyericsson.com>

Change-Id: I145fb5d57930e91b00f1609d7b2cd16a55d5b3a9
Merge "pthread: Invalidate stale stack pointers on pthread_exit()"
bionic: allow the board to customize MALLOC_ALIGNMENT

Currently the dlmalloc allocates the memory with 8-byte alignment.
According to the com.aurorasoftworks.quadrant.ui.professional benchmark data:
We can get much better memory performance if we change it to be 16-byte aligned.
For example, On Nexus-S:
8-byte aligned :
    1378 1070  1142 1665 1765  1163 1179  1263  1404 avg: 1336.555555556
16-byte aligned:
    1691 1731  1780 1691 1671  1678 1802  1758  1780 avg: 1731.333333333
                                                    gain: 29.53%

That patch provides flexibity to customize the MALLOC_ALIGNMENT from the
board config.The macro MALLOC_ALIGNMENT defaults to 8.
To change it, please define BOARD_MALLOC_ALIGNMENT in the BoardConfig.mk:
BOARD_MALLOC_ALIGNMENT := <whatever>

Change-Id: I8da0376944a0bbcef1d0fc026bfb6d9125db9739
Signed-off-by: Jin Wei <wei.a.jin@intel.com>
Signed-off-by: Jack Ren <jack.ren@intel.com>
Signed-off-by: Beare, Bruce J <bruce.j.beare@intel.com>