Move the capture analysis from MemoryDependencyAnalysis to a more general place
so that it can be reused in MemCpyOptimizer.  This analysis is needed to remove
an unnecessary memcpy when returning a struct into a local variable.
rdar://11341081
PR12686


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156776 91177308-0d34-0410-b5e6-96231b3b80d8
Fix PR12821.

RAFast must add an <imp-def> operand when it is rewriting a sub-register
def that isn't a read-modify-write.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156777 91177308-0d34-0410-b5e6-96231b3b80d8
Don't access MO reference after invalidating operand list.

This should unbreak llvm-x86_64-linux.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156778 91177308-0d34-0410-b5e6-96231b3b80d8
Fix use of uninitialized variable.

Found by GCC's maybe-uninitialized.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156780 91177308-0d34-0410-b5e6-96231b3b80d8
[Support/COFF] Make the order of members in symbol match the standard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156785 91177308-0d34-0410-b5e6-96231b3b80d8
[Support/YAMLParser] Use rtrim on plain scalars.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156787 91177308-0d34-0410-b5e6-96231b3b80d8
Add a command line option to skip the delay slot filler pass entirely for Mips.

The purpose of this option is to silence error messages issued by machine
verifier passes and enable them to run to the end. If this option is not
provided, -verify-machineinstrs complains when it discovers there is a
non-terminator instruction (an instruction that is in a delay slot) after the
first terminator in a basic block.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156790 91177308-0d34-0410-b5e6-96231b3b80d8
Remove extraneous ';'.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156791 91177308-0d34-0410-b5e6-96231b3b80d8
Create a struct representing register units in TableGen.

Besides the weight, we also want to store up to two root registers per
unit. Most units will have a single root, the leaf register they
represent. Units created for ad hoc aliasing get two roots: The two
aliasing registers.

The root registers can be used to compute the set of overlapping
registers.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156792 91177308-0d34-0410-b5e6-96231b3b80d8
Temporarily disable anti-dependence breaking for Mips until bug 12829 is
resolved.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156801 91177308-0d34-0410-b5e6-96231b3b80d8
SelectionDAGBuilder::Clusterify : main functinality was replaced with CRSBuilder::optimize, so big part of Clusterify's code was reduced.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156804 91177308-0d34-0410-b5e6-96231b3b80d8
Rejected r156804 due to buildbots failures.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156808 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed one small stupid, but critical bug.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156810 91177308-0d34-0410-b5e6-96231b3b80d8
Remove warning about testing unsigned int with int.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156812 91177308-0d34-0410-b5e6-96231b3b80d8
Teach SimplifyLibCalls about stpcpy.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156815 91177308-0d34-0410-b5e6-96231b3b80d8
Add some release notes about compiler-rt and libc++



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156819 91177308-0d34-0410-b5e6-96231b3b80d8
minor simplification to code: Ty is already a SCEV type; don't need to run getEffectiveSCEVType() twice

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156823 91177308-0d34-0410-b5e6-96231b3b80d8
Enable all Hexagon tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156824 91177308-0d34-0410-b5e6-96231b3b80d8
Allow MCCodeEmitter access to the target MCRegisterInfo.

Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156828 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen'erate mapping physical registers to encoding values.

Many targets always use the same bitwise encoding value for physical
registers in all (or most) instructions. Add this mapping to the
.td files and TableGen'erate the information and expose an accessor
in MCRegisterInfo.

patch by Tom Stellard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156829 91177308-0d34-0410-b5e6-96231b3b80d8