Small optimization for OP_AND on ARM

Especially with 64bit operators the CG sometimes generates:
and r0, r1, #0
Which just clears r0 and is equivalent with
mov r0, #0

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22032 3ad0048d-3df7-0310-abae-a5850022a9f2
Small improvement to InterlockedExchange on ARM

Use movs instead of mov when setting the result in r0. This way the Z
flag will be set for the calling function which might allow some smaller
optimizations later on. It does not affect current code in any way,
because flags are not expected to be used across function calls.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22033 3ad0048d-3df7-0310-abae-a5850022a9f2
Assembly version of fpc_ansistr_decr_ref for ARM

As fpc_ansistr_decr_ref is a very often called procedure in typical
pascal programs this optimized version will shave off some cycles
compared to the generic one.

It tries to avoid load latencies as much as possible and also uses the
new Z-flag functionality of the InterlockedDecrement from the previous
patch. Also FreeMem is called as a tail-function.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22034 3ad0048d-3df7-0310-abae-a5850022a9f2
Assembly version of fpc_ansistr_incr_ref for ARM

Optimized to minimize load latency and icache usage. Together with the
previous fpc_ansistr_decr_ref optimization this little test programm
runs about 40% faster.

  program stringspeed;

  procedure test(s:string);
  begin
  end;

  var
    s:string;
    i: cardinal;
  begin
    s:='abcd';
    for i:=0 to $FFFFFF do
      test(s);
  end.

Even with s:='' it's about 30% faster.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22035 3ad0048d-3df7-0310-abae-a5850022a9f2
* disable reg. allocator optimization introduced in r21812 for now because it caused some trouble, see #22405

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22036 3ad0048d-3df7-0310-abae-a5850022a9f2
* removed wrong -N switch (switch is not used) description

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22037 3ad0048d-3df7-0310-abae-a5850022a9f2
* the reference counter offset depends only on the current rtl, not the compiler version, so no ifdef needed


git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22038 3ad0048d-3df7-0310-abae-a5850022a9f2
* msg files regenerated

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22039 3ad0048d-3df7-0310-abae-a5850022a9f2
+ introduce -Oofastmath
* limit the application of the tree transformation introduced in r21986 to safe cases and -Oofastmath

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22040 3ad0048d-3df7-0310-abae-a5850022a9f2
* the transformation (a or/and b) or/and c into a or/and (b or/and c) can be applied for booleans as well

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22041 3ad0048d-3df7-0310-abae-a5850022a9f2
* Set errno using a call to seterrno, like it is done for i386 target. This removes most of assembler code together with PIC hacks and makes this part independent of threadvar implementation details.


git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22042 3ad0048d-3df7-0310-abae-a5850022a9f2
* Fixed register rsi being overwritten. It is used to pass argc into libc_start_main.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22043 3ad0048d-3df7-0310-abae-a5850022a9f2
- Do not create any default object sections. On targets with section-based smartlink these sections remain empty and only cause linker to do useless job of removing them. The same happens when loading object files because duplicate section names are allowed at that time. On targets without smartlink they don't stay empty, but the internal assembler creates sections when required, so not creating initial sections effectively doesn't change anything.

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22049 3ad0048d-3df7-0310-abae-a5850022a9f2
    * -O4 switch for optimizations which are correct but which might have unexpected effects
      like field reordering (possible problems cracker classes) or using ebp as normal register (broken
      stack traces from dump_stack)

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22050 3ad0048d-3df7-0310-abae-a5850022a9f2
* Case statement labels are now expressions

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22051 3ad0048d-3df7-0310-abae-a5850022a9f2
* Case statement tests

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22052 3ad0048d-3df7-0310-abae-a5850022a9f2
* Fixed to take expressions into account

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22053 3ad0048d-3df7-0310-abae-a5850022a9f2
* updated comments to reflect latest changes to cse

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22054 3ad0048d-3df7-0310-abae-a5850022a9f2
* better naming of CPU flag strings

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22055 3ad0048d-3df7-0310-abae-a5850022a9f2
* inherit modification flag from load nodes when creating temp nodes when inlining, dfa/cse need this information

git-svn-id: http://svn.freepascal.org/svn/fpc/trunk@22056 3ad0048d-3df7-0310-abae-a5850022a9f2