minor simplification to code: Ty is already a SCEV type; don't need to run getEffectiveSCEVType() twice

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156823 91177308-0d34-0410-b5e6-96231b3b80d8
Enable all Hexagon tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156824 91177308-0d34-0410-b5e6-96231b3b80d8
Allow MCCodeEmitter access to the target MCRegisterInfo.

Add the MCRegisterInfo to the factories and constructors.

Patch by Tom Stellard <Tom.Stellard@amd.com>.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156828 91177308-0d34-0410-b5e6-96231b3b80d8
TableGen'erate mapping physical registers to encoding values.

Many targets always use the same bitwise encoding value for physical
registers in all (or most) instructions. Add this mapping to the
.td files and TableGen'erate the information and expose an accessor
in MCRegisterInfo.

patch by Tom Stellard.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156829 91177308-0d34-0410-b5e6-96231b3b80d8
[utils] Fix Get{RepositoryPath,SourceVersion} to have a more robust is-git-svn
check.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156836 91177308-0d34-0410-b5e6-96231b3b80d8
llvm-build: Don't emit library information for disabled targets.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156837 91177308-0d34-0410-b5e6-96231b3b80d8
llvm-build: Add support for non-installed libraries (e.g., gtest).
 - These libraries are only reported by llvm-config when run from a development
   tree.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156838 91177308-0d34-0410-b5e6-96231b3b80d8
Fixed a bug in llvm-objdump when disassembling using -macho option for a binary
that has more than one symbol.  The last symbol was not being disassembled to
the end of the section.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156840 91177308-0d34-0410-b5e6-96231b3b80d8
Add -enable-aa-sched-mi, off by default, for AliasAnalysis inside MachineScheduler.

This feature avoids creating edges in the scheduler's dependence graph
for non-aliasing memory operations according to whichever alias
analysis is available. It has been fully tested in Hexagon. Before
making this default, it needs to be extended to handle multiple
MachineMemOperands, compile time needs more evaluation, and
benchmarking on X86 and ARM is needed.

Patch by Sergei Larin!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156842 91177308-0d34-0410-b5e6-96231b3b80d8
Update MIPS' section in the release notes. Patch by Simon Atanasyan.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156847 91177308-0d34-0410-b5e6-96231b3b80d8
Extend the CoalescerPair interface to handle symmetric sub-register copies.

Now both SrcReg and DstReg can be sub-registers of the final coalesced
register.

CoalescerPair::setRegisters still rejects such copies because
RegisterCoalescer doesn't yet handle them.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156848 91177308-0d34-0410-b5e6-96231b3b80d8
reuse the result of some expensive computations in getSignExtendExpr() and getZeroExtendExpr()
this gives a speedup of > 80 in a debug build in the test case of PR12825 (php_sha512_crypt_r)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156849 91177308-0d34-0410-b5e6-96231b3b80d8
Add a test case for r156840, a fix to llvm-objdump when disassembling using
-macho to disassemble the last symbol to the end of the section.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156850 91177308-0d34-0410-b5e6-96231b3b80d8
Add blurb for Crack.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156852 91177308-0d34-0410-b5e6-96231b3b80d8
[docs] Remove unsupported references to ExtraSource variable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@156857 91177308-0d34-0410-b5e6-96231b3b80d8