Make x86 REP_MOV* and REP_STO instructions use the correct operand sizes in 64-bit mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153680 91177308-0d34-0410-b5e6-96231b3b80d8
Drop O4 from the llc manpage, it was removed in r70445.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153684 91177308-0d34-0410-b5e6-96231b3b80d8
Handle register copies for the new ARM register classes.

ARM recently gained DPair, DTriple, and DQuad register classes.
Update copyPhysReg() to handle copies in these register classes.

No test case, it is difficult to make the register allocator emit the
odd copies reliably. The missing DPair copy caused a failure on
partialsums in the nightly test suite.

<rdar://problem/11147997>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153686 91177308-0d34-0410-b5e6-96231b3b80d8
The shuffle scheduler is only available in asserts build - make misched-new.ll
testcase require asserts.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153687 91177308-0d34-0410-b5e6-96231b3b80d8
ARM assembly 'cmp lr, #0' should not encode using 'cmn'.

The CMP->CMN alias was matching for an immediate of zero when it
should only match for negative values.

rdar://11129224

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153689 91177308-0d34-0410-b5e6-96231b3b80d8
Lowercase the tag name to match the rest of dwarf.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153691 91177308-0d34-0410-b5e6-96231b3b80d8
Re-factored RuntimeDyld.
Added ExecutionEngine/MCJIT tests.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153694 91177308-0d34-0410-b5e6-96231b3b80d8
Try using vmov.i32 to materialize FP32 constants that can't be materialized by
vmov.f32.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153696 91177308-0d34-0410-b5e6-96231b3b80d8
Filecheck-ize this test so that it actually tests something reasonable.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153697 91177308-0d34-0410-b5e6-96231b3b80d8
Prefer even-odd D-register pairs.

We are sometimes allocatinog from the DPair register class which
contains odd-even pairs in addition to the Q registers.

Place the Q registers first in the DPair allocation order as they can be
copied with a single instruction. The odd-even pairs should only be
allocated as a last resort.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153699 91177308-0d34-0410-b5e6-96231b3b80d8
Invalidate liveness in ARMConstantIslandPass.

This pass splits basic blocks to insert constant islands, and it
doesn't recompute the live-in lists. No later passes depend on accurate
liveness information.

This fixes PR12410 where the machine code verifier was complaining.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153700 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r153694. It was causing failures in the buildbots.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153701 91177308-0d34-0410-b5e6-96231b3b80d8
Change the constant in this testcase so that it results in a constant pool
load.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153704 91177308-0d34-0410-b5e6-96231b3b80d8
If we have a VLA that has a "use" in a metadata node that's then used
here but it has no other uses, then we have a problem. E.g.,

  int foo (const int *x) {
    char a[*x];
    return 0;
  }

If we assign 'a' a vreg and fast isel later on has to use the selection
DAG isel, it will want to copy the value to the vreg. However, there are
no uses, which goes counter to what selection DAG isel expects.
<rdar://problem/11134152>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153705 91177308-0d34-0410-b5e6-96231b3b80d8
Add testcase for r153705

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153706 91177308-0d34-0410-b5e6-96231b3b80d8
Testcase for r153710.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153711 91177308-0d34-0410-b5e6-96231b3b80d8
ARM target should allow codegenprep to duplicate ret instructions to enable tailcall opt. rdar://11140249

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153717 91177308-0d34-0410-b5e6-96231b3b80d8
Ensure conditional BL instructions for ARM are given the fixup fixup_arm_condbranch.

Patch by Tim Northover!



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153737 91177308-0d34-0410-b5e6-96231b3b80d8
Cleanup whitespace. Doxygenize comments. And indent to llvm coding standards.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153740 91177308-0d34-0410-b5e6-96231b3b80d8
Add a note about a missed cmov -> sbb opportunity.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@153741 91177308-0d34-0410-b5e6-96231b3b80d8