cpufreq: ondemand: Tweak settings
makefile: vectorize for quadword registers
GCC does not support vectorization with varying vector sizes.
By default, it vectorizes for doubleword registers only.
netfilter: xt_log.h: fix warning: value computed is not used
kgsl: 3D: increase bandwidth to avoid bottlenecking the gpu
kgsl: 2D: increase bandwidth to avoid bottlenecking the gpu
Revert "kgsl: increase max allowed power levels"

This reverts commit 236b090fed5f82054feada81b1e21ba63655cfc9.
msm: deactivate notification led timeout
Make vfs_cache_pressure configurable
sched: disable GENTLTE_FAIR_SLEEPERS for better performance on Android
base: genlock: Remove genlock_release_lock and associated ioctl

Allowing a lock to be asynchronously released while a handle
was still active turned out to be too dangerous to use in a
multi-threaded environment and it served no pratical
purpose anyway.  Handles now hold an attached lock until they
are destroyed.

CRs-fixed: 333141
Change-Id: Ic0dedbad8050ff01927ddb165c65a939bf297c10
Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
lib/memcopy: use glibc version

the kernel's memcpy and memmove is very inefficient. But the glibc version is
quite fast, in some cases it is 10 times faster than the kernel version. So I
introduce some memory copy macros and functions of the glibc to improve the
kernel version's performance.

The strategy of the memory functions is:
1. Copy bytes until the destination pointer is aligned.
2. Copy words in unrolled loops.  If the source and destination are not
   aligned in the same way, use word memory operations, but shift and merge
   two read words before writing.
3. Copy the few remaining bytes.

Signed-off-by: Miao Xie <miaox*******>
ARM: entry: no need to increase preempt count for IRQ handlers

From: Russell King <rmk+kernel@arm.linux.org.uk>
Date: Sat, 25 Jun 2011 09:57:57 +0000 (+0100)
Subject: ARM: entry: no need to increase preempt count for IRQ handlers
X-Git-Tag: v3.1-rc1~258^2~1^3~16
X-Git-Url: http://git.kernel.org/?p=linux%2Fkernel%2Fgit%2Ftorvalds%2Flinux-2.6.git;a=commitdiff_plain;h=1613cc1119ecdb1bdb950da53065e615e4c4b8db

irq_enter() and irq_exit() already take care of the preempt_count
handling for interrupts, which increment and decrement the hardirq
bits of the preempt count.  So we can remove the preempt count handing
in our IRQ entry/exit assembly, like x86 did some 9 years ago.

Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
lib/string: use glibc version

the performance of memcpy and memmove of the general version is very
inefficient, this patch improved them.

Signed-off-by: Miao Xie <miaox*******>
Optimized ARM RWSEM algorithm

RWSEM implementation for ARM using atomic functions.
Heavily based on arch/sh/include/asm/rwsem.h

Signed-off-by: Ashwin Chaugule <ashwinc@codeaurora.org>
ARM: net: JIT compiler for packet filters

based of Matt Evans's PPC64 implementation.

The compiler generates ARM instructions but interworking is
supported for Thumb2 kernels.

Supports both little and big endian. Unaligned loads are emitted
for ARMv6+. Not all the BPF opcodes that deal with ancillary data
are supported. The scratch memory of the filter lives on the stack.
Hardware integer division is used if it is available.

Enabled in the same way as for x86-64 and PPC64:

	echo 1 > /proc/sys/net/core/bpf_jit_enable

A value greater than 1 enables opcode output.

Signed-off-by: Mircea Gherzan <mgherzan@xxxxxxxxx>
---

Changes in v7:
 * fix the intruction generation for LDX_MSH, OR_X, LSH_K,
   RSH_K and JMP_JA
 * fix the condition for saving the A register
 * use fls() instead of the compiler builtin
 * punt to the interpreter on absolute loads with K < 0
 * check for invalid data references
 * support the NEG opcode
 * clear X in the prologue based on a context flag
 * simplify the conditional jumps

Changes in v6:
 * fix the code generation for the ANC_CPU opcode

Changes in v5:
 * replace SEEN_LEN with SEEN_SKB
 * set ctx->seen when handling some ancillary data opcodes

Changes in v4:
 * first check if the JIT compiler is enabled
 * fix the code generation for the LDX_MSH opcode

Changes in v3:
 * no longer depend on EABI and !Thumb2
 * add BLX "emulation" for ARMv4 without Thumb
 * use the integer divide instruction on Cortex-A15
 * fix the handling of the DIV_K opcode
 * use a C wrapper for __aeabi_uidiv
 * fix the generation of the epilogue (non-FP case)

Changes in v2:
 * enable the compiler only for ARMv5+ because of the BLX instruction
 * use the same comparison for the ARM version checks
 * use misaligned accesses on ARMv6
 * fix the SEEN_MEM
 * fix the mem_words_used()
msm: kgsl: Allow device attributes to be re-created

Leave the attributes initialized so that removing and
restoring policies doesn't result in a kernel panic.

Change-Id: I9724ebf94e3845b6cbaea18abf49d1813043eb52
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>
msm: kgsl: fix infinite loop in adreno_find_region()

If postmortem dump tried to parse a context switch
buffer for any context except the current context
this function would never return.

Change-Id: I19f2fe7afda5796180cdf5f81c17fad960e84f05
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
msm: kgsl: adreno_isidle shouldn't BUG()

If the ringbuffer isn't idle, the GPU is probably in
SLUMBER or SUSPEND which are very idle states. This
function probably still shouldn't be called, so WARN
instead.

Change-Id: Ia49a819d935d6dce9cae2c193aff8e9de87d8af6
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
msm: kgsl: in postmortem, log powerstate before changing it

Change-Id: I9b6533acbe99c5094d51ac4fb12a23a280cc07c7
Signed-off-by: Jeremy Gebben <jgebben@codeaurora.org>
msm: kgsl: Eventually transition to SLUMBER

Even if a core is ACTIVE during an early_suspend call make
sure it switches off eventually with lack of use.

Change-Id: I476e8a14a0d7e90a8ed8b8c05d0cf5ed88632cad
Signed-off-by: Lucille Sylvester <lsylvest@codeaurora.org>