Blackfin: easylogo: add lzma logos

The bf527-ezkit boards are getting too big to fit into their reserved
flash space, so we need to use a lzma compressed logo.

Since the video driver code is very similar, add lzma compressed support
to all of the Blackfin video drivers.

Signed-off-by: Mike Frysinger <vapier@gentoo.org>
common lcd: minor coding style changes

No functional changes

Signed-off-by: Nikita Kiryanov <nikita@compulab.co.il>
Signed-off-by: Igor Grinberg <grinberg@compulab.co.il>
mx6: Allow mx6 to access the IPUv3 registers

Adjust the IPUv3 registers, so that the IPUv3 driver can be extended for mx6 as well.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
video: Rename CONFIG_VIDEO_MX5

Rename CONFIG_VIDEO_MX5 as this driver can also be used on mx6.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
ipu_common: Only apply the erratum to MX51

The following erratum :

"ENGcm08316
IPU: Clarification regarding the bypass mode registers setup for
display and camera interfaces"

only applies to mx51, so restrict its usage for this SoC only.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
ipu_common: Let clk_ipu_enable/disable only run on MX51 and MX53

The registers accessed inside clk_ipu_enable/disable are not present on MX6,
so make sure they only run on MX51 and MX53.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
ipu_common: Rename MXC_CCM_BASE

Rename MXC_CCM_BASE to CCM_BASE_ADDR as this is already defined for MX6.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
ipu_common: Do not hardcode the ipu_clk frequency

Do not hardcode the ipu_clk frequency and let the board file pass this value.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
ipu_common: Add ldb_clk for use in parenting the pixel clock

Add ldb_clk for use in parenting the pixel clock.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
i.MX: fsl_esdhc: allow use with cache enabled.

Signed-off-by: Eric Nelson <eric.nelson@boundarydevices.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
mmc: remove the hard setting for tran_speed

mmc_set_clock is set to the hard-coding.
But i think good that use the tran_speed value.

Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
mmc:fix Call mmc_init() when executing mmc_get_dev()

This code adds call to mmc_init(), for partition related commands (e.g.
fatls, fatinfo etc.).

It is safe to call mmc_init() multiple times since mmc->has_init flag
prevents from multiple initialization.

The FAT related code calls get_dev high level method and then uses
elements from mmc->block_dev, which is uninitialized until the mmc_init
(and thereof mmc_startup) is called.

This problem appears on boards, which don't use mmc as the default
place for envs

Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Cc: Andy Fleming <afleming@gmail.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
SD/MMC: check the card status during erase operation

Use the function 'mmc_send_status' to check the card status.
only when the card is ready, driver can send the next erase command
to the card, otherwise, the erase will failed:
=> mmc erase 0 1
MMC erase: dev # 0, block # 0, count 1 ... 1 blocks erase: OK
=> mmc erase 0 2
MMC erase: dev # 0, block # 0, count 2 ... mmc erase failed
1 blocks erase: ERROR
=> mmc erase 0 4
MMC erase: dev # 0, block # 0, count 4 ... mmc erase failed
1 blocks erase: ERROR

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Andy Fleming <afleming@gmail.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Andy Fleming <afleming@freescale.com>
FSL/eSDHC: enable the clock to detect the SD card

For FSL low-end processors (VVN2.2), in order to detect the SD card,
we should enable PEREN, HCKEN and IPGEN to enable the clock.
Otherwise, after booting the u-boot, and then inserting the SD card,
the SD card can't be detected.
For SDHC VVN2.3 IP, these bits are reserved, and SDCLKEN is used.
And when accessing to these reserved bit, no any impact happened.

Signed-off-by: Jerry Huang <Chang-Ming.Huang@freescale.com>
CC: Andy Fleming <afleming@gmail.com>
CC: Marek Vasut <marex@denx.de>
Signed-off-by: Andy Fleming <afleming@freescale.com>
nios2: move gd and bd into BSS

As suggested by Graeme Russ, move gd and bd data structrures
to BSS instead of calculating the locations around the stack
and heap.

Signed-off-by: Thomas Chou <thomas@wytron.com.tw>
Acked-by: Mike Frysinger <vapier@gentoo.org>
ehci-omap: Do not call dcache_off from omap_ehci_hcd_init

This has never been completely sufficient and now happens too late to
paper over the cache coherency problems with the current USB stack.

Cc: Marek Vasut <marex@denx.de>
Signed-off-by: Tom Rini <trini@ti.com>
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
common.h: Introduce DEFINE_CACHE_ALIGN_BUFFER

This is the out-of-function-scope counterpart of
ALLOC_CACHE_ALIGN_BUFFER.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Tom Rini <trini@ti.com>
[ilya.yanok]: added missing <linux/compiler.h> include and
{DEFINE,ALLOC}_ALIGN_BUFFER macros allowing explicit alignment
specification.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
ehci-hcd: program asynclistaddr before every transfer

Move or_asynclistaddr programming to ehci_submit_async()
function to make sure queue head is properly programmed
before every transfer. This solves the problem with changing
qh address.

Also remove unneeded qh_list->qh_link reprogramming at the
end of transfer.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
ehci-hcd.c, musb_core, usb.h: Add USB_DMA_MINALIGN define for cache alignment

The USB spec says that 32 bytes is the minimum required alignment.
However on some platforms we have a larger minimum requirement for cache
coherency.  In those cases, use that value rather than the USB spec
minimum.  We add a cpp check to <usb.h> to define USB_DMA_MINALIGN and
make use of it in ehci-hcd.c and musb_core.h.  We cannot use MAX() here
as we are not allowed to have tests inside of align(...).

Signed-off-by: Tom Rini <trini@ti.com>
[marek.vasut]: introduce some crazy macro voodoo
Signed-off-by: Marek Vasut <marex@denx.de>
[ilya.yanok]: moved external buffer fixes to separate patch,
we use {ALLOC,DEFINE}_ALIGN_BUFFER macros with alignment of USB_DMA_MINALIGN
for qh_list, qh and qtd structures to make sure they are proper aligned
for both controller and cache operations.
Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>
ehci-hcd: fix external buffer cache handling

Buffer coming from upper layers should be cacheline aligned/padded
to perform safe cache operations. For now we don't do bounce
buffering so getting unaligned buffer is an upper layer error.
We can't check if the buffer is properly padded with current
interface so just assume it is (consider changing with in the
future). The following changes are done:

1. Remove useless length alignment check. We get actual transfer
length not the size of the underlying buffer so it's perfectly
valid for it to be unaligned.
2. Move flush_dcache_range() out of while loop or it will
flush too much.
3. Don't try to fix buffer address before calling invalidate:
if it's unaligned it's an error anyway so let cache subsystem
cry about that.
4. Fix end buffer address to be cacheline aligned assuming upper
layer reserved enough space. This is potentially dangerous
operation so upper layers should be careful about that.

Signed-off-by: Ilya Yanok <ilya.yanok@cogentembedded.com>