mpc85xx: Initial SP alignment is wrong.

PowerPC mandates SP to be 16 bytes aligned.
Furthermore, a stack frame is added, pointing to the reset vector
which may in the way when gdb is walking the stack because
the reset vector may not accessible depending on emulator settings.
Also use a temp register so gdb doesn't pick up intermediate values.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Acked-by: Kumar Gala <galak@kernel.crashing.org>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc: Stack Pointer not properly aligned

The code first aligns the SP to 16 then subtract 8, making it
8 bytes aligned. Furthermore the initial stack frame not
quite correct either.

Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
Signed-off-by: Andy Fleming <afleming@freescale.com>
nand/fsl_elbc: shrink SPL a bit by converting out_be32() to __raw_writel()

This is needed to make room for a bugfix on p1_p2_rdb_pc.  A sync is used
before the final write to LSOR that initiates the transaction, to ensure
all the other set up has been completed.

Signed-off-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/mpc85xx: Make NMG_CPU_A011 workaround conditional

This erratum applies to the following SoCs:
P4080 rev 1.0, 2.0, fixed in rev 3.0
P2041 rev 1.0, 1.1, fixed in rev 2.0
P3041 rev 1.0, 1.1, fixed in rev 2.0.

Workaround for erratum NMG_CPU_A011 is enabled by default. This workaround
may degrade performance. P4080 erratum CPU22 shares the same workaround.
So it is always enabled for P4080. For other SoCs, it can be disabled by
hwconfig with syntax:

fsl_cpu_a011:disable

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/corenet_ds: Update README.srio-boot-corenet

Update some descriptions due to the implementation changes:

For master:
	Get rid of the SRIOBOOT_MASTER build target, and to support
	for serving as a SRIO boot master via environment variable.
For slave:
	1. When compile the slave image for boot from SRIO, no longer
	   need to specify which SRIO port it will boot from.
	2. All slave's cores should be in hold off.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/corenet_ds: Get rid of the SRIOBOOT_MASTER build target

Get rid of the SRIOBOOT_MASTER build target, and to support for serving as
a SRIO boot master via environment variable. Set the environment variable
"bootmaster" to "SRIO1" or "SRIO2" using the following command:

		setenv bootmaster SRIO1
		saveenv

The "bootmaster" will enable the function of the SRIO boot master, and
this has the following advantages compared with SRIOBOOT_MASTER build
configuration:
	1. Reduce a build configuration item in boards.cfg file.
	   No longer need to build a special image for master, just use a
	   normal target image and set the "bootmaster" variable.
	2. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just set the corresponding value to "bootmaster"
	   based on the using SRIO port.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/corenet_ds: Get rid of the CONFIG_SRIOBOOT_SLAVE_PORTx macro

When compile the slave image for boot from SRIO, no longer need to
specify which SRIO port it will boot from. The code will get this
information from RCW and then finishes corresponding configurations.

This has the following advantages:
	1. No longer need to rebuild an image when change the SRIO port for
	   boot from SRIO, just rewrite the new RCW with selected port,
	   then the code will get the port information by reading new RCW.
	2. It will be easier to support other boot location options, for
	   example, boot from PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/corenet_ds: Update README and README.srio-pcie-boot-corenet

Added descriptions about boot from PCIE in the files README and
doc/README.srio-pcie-boot-corenet, and changed the name of the
doc/README.srio-boot-corenet to doc/README.srio-pcie-boot-corenet.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/corenet_ds: Master module for boot from PCIE

For the powerpc processors with PCIE interface, boot location can be
configured from one PCIE interface by RCW. The processor booting from PCIE
can do without flash for u-boot image. The image can be fetched from another
processor's memory space by PCIE link connected between them.

The processor booting from PCIE is slave, the processor booting from normal
flash memory space is master, and it can help slave to boot from master's
memory space.

When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Environment and requirement:

master:
    1. NOR flash for its own u-boot image, ucode and ENV space.
    2. Slave's u-boot image is in master NOR flash.
    3. Normally boot from local NOR flash.
    4. Configure PCIE system if needed.
slave:
    1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
    2. Boot location should be set to one PCIE interface by RCW.
    3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the master module, need to finish these processes:
    1. Initialize the PCIE port and address space.
    2. Set inbound PCIE windows covered slave's u-boot image stored in
       master's NOR flash.
	3. Set outbound windows in order to configure slave's registers
	   for the core's releasing.
    4. Should set the environment variable "bootmaster" to "PCIE1", "PCIE2"
	   or "PCIE3" using the following command:

			setenv bootmaster PCIE1
			saveenv

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/corenet_ds: Slave module for boot from PCIE

When boot from PCIE, slave's core should be in holdoff after powered on for
some specific requirements. Master will release the slave's core at the
right time by PCIE interface.

Slave's ucode and ENV can be stored in master's memory space, then slave
can fetch them through PCIE interface. For the corenet platform, ucode is
for Fman.

NOTE: Because the slave can not erase, write master's NOR flash by
	  PCIE interface, so it can not modify the ENV parameters stored
	  in master's NOR flash using "saveenv" or other commands.

environment and requirement:

master:
	1. NOR flash for its own u-boot image, ucode and ENV space.
	2. Slave's u-boot image is in master NOR flash.
	3. Put the slave's ucode and ENV into it's own memory space.
	4. Normally boot from local NOR flash.
	5. Configure PCIE system if needed.
slave:
	1. Just has EEPROM for RCW. No flash for u-boot image, ucode and ENV.
	2. Boot location should be set to one PCIE interface by RCW.
	3. RCW should configure the SerDes, PCIE interfaces correctly.
	4. Must set all the cores in holdoff by RCW.
	5. Must be powered on before master's boot.

For the slave module, need to finish these processes:
	1. Set the boot location to one PCIE interface by RCW.
    2. Set a specific TLB entry for the boot process.
	3. Set a LAW entry with the TargetID of one PCIE for the boot.
	4. Set a specific TLB entry in order to fetch ucode and ENV from
	   master.
	5. Set a LAW entry with the TargetID one of the PCIE ports for
	   ucode and ENV.
	6. Slave's u-boot image should be generated specifically by
	   make xxxx_SRIO_PCIE_BOOT_config.
	   This will set SYS_TEXT_BASE=0xFFF80000 and other configurations.

In addition, the processes are very similar between boot from SRIO and
boot from PCIE. Some configurations like the address spaces can be set to
the same. So the module of boot from PCIE was added based on the existing
module of boot from SRIO, and the following changes were needed:
	1. Updated the README.srio-boot-corenet to add descriptions about
	   boot from PCIE, and change the name to
	   README.srio-pcie-boot-corenet.
	2. Changed the compile config "xxxx_SRIOBOOT_SLAVE" to
	   "xxxx_SRIO_PCIE_BOOT", and the image builded with
	   "xxxx_SRIO_PCIE_BOOT" can support both the boot from SRIO and
	   from PCIE.
	3. Updated other macros and documents if needed to add information
	   about boot from PCIE.

Signed-off-by: Liu Gang <Gang.Liu@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/CoreNet: add tool to support pbl image build.

Provides a tool to build boot Image for PBL(Pre boot loader) which is
used on Freescale CoreNet SoCs, PBL can be used to load some instructions
and/or data for pre-initialization. The default output image is u-boot.pbl,
for more details please refer to doc/README.pblimage.

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/mpc8xxx: Remove P1015 and P1016 from CPU list

P1015 is the same as P1011 and P1016 is the same as P1012 from software
point of view. They have different packages but share SVRs.

Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
p1014rdb: set ddr bus width properly depending on SVR

Currently, for NAND boot for the P1010/4RDB we hard code the DDR
configuration. We can still dynamically set the DDR bus width in
the nand spl so the P1010/4RDB boards can boot from the same
u-boot image

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
p1010rdb: fix ddr values for p1014rdb (setting bus width to 16bit)

There was an extra 0 in front of the value we were using to mask,
remove it to improve the code.

Also fix the value written to ddr_sdram_cfg to set the bus width
properly to 16 bits

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/p1010rdb: nandboot: compare SVR properly

We were not comparing the SVRs properly previously. This comparison
will properly shift the SVR and mask off the E bit

This fixes the boot output to show the correct DDR bus width:

512 MiB (DDR3, 16-bit, CL=5, ECC off)

instead of

512 MiB (DDR3, 32-bit, CL=5, ECC off)

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
nand_spl: update udelay for Freescale boards

Let's use the more appropriate udelay for the nand_spl. While we
can't make use of u-boot's full udelay we can atl east use a for
loop that won't get optimized away .Since we have the bus clock
we can use the timebase to calculate wall time.

Looked at reusing the u-boot udelay functions but it pulls in a lot
of code and would require quite a bit of work to keep us within the
very small space constrains we currently have

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
nand_spl: p1023rds: wait before enabling DDR controller

We have a requirement to wait a period of time before enabling the
DDR controller

Signed-off-by: Matthew McClintock <msm@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
nand_spl: change out_be32 to raw_writel and depend on subsequent sync

This change reduces the SPL size by removing the redundant syncs produced
by out_be32 and just replies on one final sync

Done with:

sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/`

Signed-off-by: Matthew McClintock <msm@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
mpc85xx: use LCRR_DBYP define instead of raw constant

Using the raw value of 0x80000000 directly in the code can
lead to "count the zeros" bugs like that fixed in commit
718e9d13b98 ("MPC85xxCDS: Fix missing LCRR_DBYP bits for
66-133MHz LBC")

Change all existing raw values to use the symbolic value of
LCRR_DBYP instead.

Cc: Kumar Gala <galak@kernel.crashing.org>
Cc: Scott Wood <scottwood@freescale.com>
Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/85xx: add support for FM2 DTSEC5

Unlike previous SOCs, the Freescale P5040 has a fifth DTSEC on the second
Fman, so add the Fman and SerDes macros for that DTSEC.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>