crypto: tcrypt - randomize speed test memory

Running tests on uniform memory might result better performance results than on random data.

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: blowfish - add AVX2/x86_64 implementation of blowfish cipher

TODO: test performance on real hardware. Estimated performance: 4 to 12 cpb

Performance tests using Intel Architecture Code Analyzer Version - 2.0.1:

Estimates assume that latencies and throughput of 256-bit AVX2 instructions
are same as of 128-bit AVX instructions, except vpgatherdd that is estimated as
following:
 *1: Dispatches 8 load uops, that can be dispatched to two load ports, and 2
     helper uops for merging loads. This also is nearly same as estimating
     case where there is only one load port with gather hardware with 4 cycles
     latency.
 *2: Dedicated gather hardware on two load ports, 1 uop with latency of 8
     cycles (can fetch parallel on two ports) + 2 helper uops.
 *3: Dedicated gather hardware on two load port, 1 uop with latency of 4
     cycles (can fetch parallel on two ports) + 2 helper uops.

blowfish-16way, cycles/byte:
 *1:	4.76
 *2:	5.95
 *3:	4.24

(blowfish-32way, cycles/byte, not yet included in this patch:
 *1:	4.22
 *2:	3.76
 *3:	2.62)

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: twofish - add AVX2/x86_64 assembler implementation of twofish cipher

TODO: benchmarks on real hardware. Est. 5~12 cpb

Performance tests using Intel Architecture Code Analyzer Version - 2.0.1:

Estimates assume that latencies and throughput of 256-bit AVX2 instructions
are same as of 128-bit AVX instructions, except vpgatherdd that is estimated as
following:
 *1: Dispatches 8 load uops, that can be dispatched to two load ports, and 2
     helper uops for merging loads. This also is nearly same as estimating
     case where there is only one load port with gather hardware with 4 cycles
     latency.
 *2: Dedicated gather hardware on two load ports, 1 uop with latency of 8
     cycles (can fetch parallel on two ports) + 2 helper uops.
 *3: Dedicated gather hardware on two load port, 1 uop with latency of 4
     cycles (can fetch parallel on two ports) + 2 helper uops.

twofish-16way, cycles/byte:
 *1:    5.40
 *2:    5.80
 *3:    3.87

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: camellia - add AVX2/x86_64 assembler implementation of camellia cipher

TODO: benchmarks on real hardware. Est. 6~13 cpb

Performance tests using Intel Architecture Code Analyzer Version - 2.0.1:

Estimates assume that latencies and throughput of 256-bit AVX2 instructions
are same as of 128-bit AVX instructions, except vpgatherdd that is estimated as
following:
 *1: Dispatches 8 load uops, that can be dispatched to two load ports, and 2
     helper uops for merging loads. This also is nearly same as estimating
     case where there is only one load port with gather hardware with 4 cycles
     latency.
 *2: Dedicated gather hardware on two load ports, 1 uop with latency of 8
     cycles (can fetch parallel on two ports) + 2 helper uops.
 *3: Dedicated gather hardware on two load port, 1 uop with latency of 4
     cycles (can fetch parallel on two ports) + 2 helper uops.

camellia-16way, cycles/byte:
 *1:    5.63
 *2:    6.19
 *3:    4.14

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>
crypto: serpent - add AVX2/x86_64 assembler implementation of serpent cipher

TODO: benchmarks on real hardware. Est. 4.5~7 cpb

Performance tests using Intel Architecture Code Analyzer Version - 2.0.1:

Estimate assume that latencies and throughput of 256-bit AVX2 instructions
are same as of 128-bit AVX instructions on Ivy Bridge.

serpent-16way, cycles/byte: 4.84

Signed-off-by: Jussi Kivilinna <jussi.kivilinna@mbnet.fi>