Try a completely different approach to this type trait to appease older
compilers. It seems that GCC 4.3 (and likely older) simply aren't going
to do SFINAE on non-type template parameters the way Clang and modern
GCCs do...

Now we detect the implicit conversion to an integer type, and then
blacklist classes, pointers, and floating point types. This seems to
work well enough, and I'm hopeful will return the bots to life.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152227 91177308-0d34-0410-b5e6-96231b3b80d8
Fix infinite loop in nested multiclasses.

Patch by Michael Liao!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152232 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r152202 as it's causing internal buildbot failures.

Original commit message:
Use uint16_t to store InstrNameIndices in MCInstrInfo. Add asserts to protect 
all 16-bit string table offsets. Also make sure the string to offset table 
string is not larger than 65536 characters since larger string literals aren't 
portable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152233 91177308-0d34-0410-b5e6-96231b3b80d8
configure: Don't require a perl interpreter to be present, LLVM's buildsystem doesn't depend on perl anymore.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152234 91177308-0d34-0410-b5e6-96231b3b80d8
Use llvm-mc instead of llc. Patch by Jack Carter.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152242 91177308-0d34-0410-b5e6-96231b3b80d8
[fast-isel] ARMEmitCmp generates FMSTAT, which transfers the floating-point 
condition flags to CPSR.  This allows us to simplify SelectCmp.
Patch by Zonr Chang <zonr.xchg@gmail.com>.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152243 91177308-0d34-0410-b5e6-96231b3b80d8
SmallPtrSet: Copy all the elements when swapping, not just numelements.

This fixes a build failure in webkit. Copying all elements shouldn't be
necessary, I'll look out for a better fix soon.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152252 91177308-0d34-0410-b5e6-96231b3b80d8
Copy the right amount of elements.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152254 91177308-0d34-0410-b5e6-96231b3b80d8
misched preparation: rename core scheduler methods for consistency.

We had half the API with one convention, half with another. Now was a
good time to clean it up.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152255 91177308-0d34-0410-b5e6-96231b3b80d8
misched prep: rename InsertPos to End.

ScheduleDAGInstrs knows nothing about how instructions will be moved or inserted.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152256 91177308-0d34-0410-b5e6-96231b3b80d8
misched prep: remove extra "protected"

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152257 91177308-0d34-0410-b5e6-96231b3b80d8
misched prep: Cleanup ScheduleDAGInstrs interface.

ScheduleDAGInstrs will be the main interface for MI-level
schedulers. Make sure it's readable: one page of protected fields, one
page of public methids.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152258 91177308-0d34-0410-b5e6-96231b3b80d8
misched prep: Comment the ScheduleDAGInstrs interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152259 91177308-0d34-0410-b5e6-96231b3b80d8
misched prep: Remove LLVM_LIBRARY_VISIBILITY from ScheduleDAGInstrs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152260 91177308-0d34-0410-b5e6-96231b3b80d8
misched prep: Expose the ScheduleDAGInstrs interface so targets may
implement their own MachineScheduler.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152261 91177308-0d34-0410-b5e6-96231b3b80d8
Cleanup VLIWPacketizer to use the updated ScheduleDAGInstrs interface.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152262 91177308-0d34-0410-b5e6-96231b3b80d8
Improved support in RuntimeDyldMachO for generating
code that will be relocated into another memory space.
Now when relocations are resolved, the address of
the relocation in the host memory (where the JIT is)
is passed separately from the address that the
relocation will be at in the target memory (where
the code will run).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152264 91177308-0d34-0410-b5e6-96231b3b80d8
ARM don't use MCRelaxAll, as it's not safe on ARM.

The ARM code generator makes aggressive assumptions about the encodings
being selected for branches which MCRelaxAll invalidates.

rdar://11006355


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152268 91177308-0d34-0410-b5e6-96231b3b80d8
misched interface: Expose the MachineScheduler pass.

Allow targets to provide their own schedulers (subclass of
ScheduleDAGInstrs) to the misched pass. Select schedulers using
-misched=...

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152278 91177308-0d34-0410-b5e6-96231b3b80d8
This patch eliminates redundant instructions that produce 0.

For example, the first instruction in the code below can be eliminated if the
use of $vr0 is replaced with $zero: 

addiu $vr0, $zero, 0
add $vr2, $vr1, $vr0

add $vr2, $vr1, $zero



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@152280 91177308-0d34-0410-b5e6-96231b3b80d8