X86 Peephole: fold loads to the source register operand if possible.

Machine CSE and other optimizations can remove instructions so folding
is possible at peephole while not possible at ISel.

rdar://10554090 and rdar://11873276


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160919 91177308-0d34-0410-b5e6-96231b3b80d8
X86 Peephole: fold loads to the source register operand if possible.

Trying to fix the bot by specifying a triple in the failing testing cases.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160920 91177308-0d34-0410-b5e6-96231b3b80d8
Mark some of the SSE/AVX convert instructions as mayLoad/neverHasSideEffects.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160921 91177308-0d34-0410-b5e6-96231b3b80d8
Fold patterns for some of the SSE/AVX convert instructions into their instruction definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160922 91177308-0d34-0410-b5e6-96231b3b80d8
Add testcases for GlobalOpt changes in r160693 and r160757.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160925 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r160920 and r160919 due to dragonegg and clang selfhost failure



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160927 91177308-0d34-0410-b5e6-96231b3b80d8
APInt: Simplify code.

No functionality change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160929 91177308-0d34-0410-b5e6-96231b3b80d8
Move more SSE/AVX convert instruction patterns into their definitions.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160937 91177308-0d34-0410-b5e6-96231b3b80d8
Fix load types on intrinsic forms of SS2SD and SD2SS AVX/SSE convert instruction patterns.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160938 91177308-0d34-0410-b5e6-96231b3b80d8
Fix up patterns for VCVTSS2SD. Specifically give it priority over SSE form. Add an OptForSpeed to explicitly pair up with an OptForSize that was already on another pattern.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160939 91177308-0d34-0410-b5e6-96231b3b80d8
Fix patterns for CVTTPS2DQ to specify SSE2 instead of SSE1.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160941 91177308-0d34-0410-b5e6-96231b3b80d8
Give VCVTTPD2DQ priority over CVTTPD2DQ.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160942 91177308-0d34-0410-b5e6-96231b3b80d8
Remove trailing whitespace.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160945 91177308-0d34-0410-b5e6-96231b3b80d8
Remove check for f256mem from has256BitOperands as nothing depended on it and it isn't the only 256-bit memory type anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160946 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify code that filtered certain instructions in two different ways. No functional change.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160948 91177308-0d34-0410-b5e6-96231b3b80d8
Remove check for sub class of X86Inst from filter function since caller guaranteed it. Replace another sub class check with ShouldBeEmitted flag since it was factored in there already.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160949 91177308-0d34-0410-b5e6-96231b3b80d8
Remove some unnecessary filter checks. They were already covered by IsCodeGenOnly

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160950 91177308-0d34-0410-b5e6-96231b3b80d8
Mark MOVZX32_NOREX as isCodeGenOnly and neverHasSideEffects. The isCodeGenOnly change allows special detection of _NOREX instructions to be removed from tablegen disassembler code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160951 91177308-0d34-0410-b5e6-96231b3b80d8
Mark MOVZX16/MOVSX16 as neverHasSideEffects/mayLoad

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160953 91177308-0d34-0410-b5e6-96231b3b80d8
When constant folding GEP expressions, keep the address space information of pointers.

Together with Ran Chachick <ran.chachick@intel.com>



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160954 91177308-0d34-0410-b5e6-96231b3b80d8