Remove MMX shift intrinsic handling code that also exists in SelectionDAGBuilder.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162661 91177308-0d34-0410-b5e6-96231b3b80d8
llvm/test/CodeGen/X86/fma_patterns.ll: Add -mtriple=x86_64. It was incompatible on i686 and Windows x64.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162664 91177308-0d34-0410-b5e6-96231b3b80d8
DWARFDebugRangeList.cpp: Use PRIx64 for uint64_t as format string.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162665 91177308-0d34-0410-b5e6-96231b3b80d8
llvm/test/CodeGen/X86/fma.ll: Add -march=x86, or two tests would fail on non-x86 hosts.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162667 91177308-0d34-0410-b5e6-96231b3b80d8
Support MIPS DSP Rev2 intrinsics.
The patch reviewed by Akira Hatanaka.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162668 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the the block_node_iterator of Region, replace it by the block_iterator.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162672 91177308-0d34-0410-b5e6-96231b3b80d8
Fix comment for function RuntimeDyldImpl.resolveRelocation()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162677 91177308-0d34-0410-b5e6-96231b3b80d8
Fix comment.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162678 91177308-0d34-0410-b5e6-96231b3b80d8
Don't use for loops for code that is only intended to execute once. No
intended functionality change. Thanks to Ahmed Charles for spotting it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162686 91177308-0d34-0410-b5e6-96231b3b80d8
Make sure we add the predicate after all of the registers are added.
<rdar://problem/12183003>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162703 91177308-0d34-0410-b5e6-96231b3b80d8
Fix compile error when building with C++11 - clang thinks that PRIx64 is a user-defined suffix or something

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162704 91177308-0d34-0410-b5e6-96231b3b80d8
Add --program-prefix support to build.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162707 91177308-0d34-0410-b5e6-96231b3b80d8
Add ATOMIC_LDR* pseudo-instructions to model atomic_load on ARM.

It is not safe to use normal LDR instructions because they may be
reordered by the scheduler. The ATOMIC_LDR pseudos have a mayStore flag
that prevents reordering.

Atomic loads are also prevented from participating in rematerialization
and load folding.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162713 91177308-0d34-0410-b5e6-96231b3b80d8
More missing mayLoad flags on AVX multiclasses.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162714 91177308-0d34-0410-b5e6-96231b3b80d8
Temporarily revert this to bring back the bots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162722 91177308-0d34-0410-b5e6-96231b3b80d8
Optimize zext on PPC64.

The zeroextend IR instruction is lowered to an 'and' node with an immediate
mask operand, which in turn gets legalised to a sequence of ori's & ands.
This can be done more efficiently using the rldicl instruction.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162724 91177308-0d34-0410-b5e6-96231b3b80d8
Eliminate redundant CR moves on PPC32.

The 32-bit ABI requires CR bit 6 to be set if the call has fp arguments and
unset if it doesn't. The solution up to now was to insert a MachineNode to
set/unset the CR bit, which produces a CR vreg. This vreg was then copied
into CR bit 6. When the register allocator saw a bunch of these in the same
function, it allocated the set/unset CR bit in some random CR register (1
extra instruction) and then emitted CR moves before every vararg function
call, rather than just setting and unsetting CR bit 6 directly before every
vararg function call. This patch instead inserts a PPCcrset/PPCcrunset
instruction which are then matched by a dedicated instruction pattern.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162725 91177308-0d34-0410-b5e6-96231b3b80d8
Add the Freescale vendor to Triple.

Adds the vendor 'fsl' (used by Freescale SDK) to Triple. This will allow
clang support for Freescale cross-compile configurations.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162726 91177308-0d34-0410-b5e6-96231b3b80d8
Allow remat of LI on PPC.

Allow load-immediates to be rematerialised in the register coalescer for
PPC. This makes test/CodeGen/PowerPC/big-endian-formal-args.ll fail,
because it relies on a register move getting emitted. The immediate load is
equivalent, so change this test case.

Patch by Tobias von Koch.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162727 91177308-0d34-0410-b5e6-96231b3b80d8
Fix bug 13532.

In SelectionDAGLegalize::ExpandLegalINT_TO_FP, expand INT_TO_FP nodes without
using any f64 operations if f64 is not a legal type.

Patch by Stefan Kristiansson. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@162728 91177308-0d34-0410-b5e6-96231b3b80d8