i965/blorp: Use 16 pixel dispatch on Gen7.

Gen7 hardware requires us to enable at least one WM dispatch mode,
even if there is no program being dispatched to.  When this code was
only used for HiZ operations (which don't use a WM program), we used
32-pixel dispatch, because it didn't matter.  But blit programs are
compiled for 16-pixel dispatch.  So just enable 16-wide dispatch
unconditionally.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

v2: Enable 16-wide dispatch unconditionally rather than add the
unnecessary complication of using 32-wide dispatch when there is no WM
program.
i965/blorp: Implement proper texel fetch messages for Gen7.

On Gen6, texel fetch is always accomplished using the SAMPLE_LD
message, which accepts arguments (u, v, r, lod, si).  On Gen7, there
are two* texel fetch messages: SAMPLE_LD for non-MSAA surfaces, taking
arguments (u, lod, v), and SAMPLE_LD2DSS for MSAA surfaces, taking
arguments (si, u, v).

*Technically, there are other texel fetch messages, but they are used
for "compressed" MSAA surfaces, which we don't yet support.

This patch adds the proper message types and argument orderings for
Gen7.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/blorp: Enable blorp blits on Gen7.

Gen7 support for blorp (blits using the render bath) now works for
non-MSAA purposes.  This patch enables it.

Since blorp operations re-use the logic for HiZ ops, this required
adding a case to the switch statement in gen7_blorp_emit_wm_config(),
to allow for the case where no HiZ op is being performed.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/msaa: Add defines for Gen7.

Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/msaa: Properly handle sliced layout for Gen7.

Starting in Gen7, there are two possible layouts for MSAA surfaces:

- Interleaved, in which additional samples are accommodated by scaling
  up the width and height of the surface.  This is the only layout
  available in Gen6.  On Gen7 it is used for depth and stencil
  surfaces only.

- Sliced, in which the surface is stored as a 2D array, with array
  slice n containing all pixel data for sample n.  On Gen7 this layout
  is used for color surfaces.

The "Sliced" layout has an additional requirement: it must be used in
ARYSPC_LOD0 mode, which means that the surface doesn't leave any extra
room between array slices for miplevels other than 0.

This patch modifies the surface allocation functions to use the
correct layout when allocating MSAA surfaces in Gen7, and to set the
array offsets properly when using ARYSPC_LOD0 mode.  It also modifies
the code that populates SURFACE_STATE structures to ensure that
ARYSPC_LOD0 mode is selected in the appropriate circumstances.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/msaa: Validate Gen7 surface state constraints.

When a Gen7 SURFACE_STATE is configured for MSAA, a number of
additional constaints come in to play.  This patch adds a function
gen7_check_surface_setup() which verifies that all of those
constraints are met.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/msaa: Modify blorp code to account for Gen7 MSAA layouts.

Since blorp uses color textures and render targets to do all its work
(even when blitting stencil and depth data), it always has to
configure the Gen7 GPU to use the new "sliced" MSAA layout.  However,
when blitting stencil or depth data, the actual MSAA layout is
interleaved (as in Gen6).  Therefore, blorp has to do extra coordinate
transformation work to account for the interleaving manually.

This patch causes blorp to perform the necessary extra coordinate
transformations.

It also modifies the blorp SURFACE_STATE setup code for Gen7, so that
it does not try to correct the surface width and height to account for
MSAA, since "sliced" MSAA layout doesn't affect the surface width or
height.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
i965/msaa: Implement manual blending operation for Gen7.

On Gen6, the blending necessary to blit an MSAA surface to a non-MSAA
surface could be accomplished with a single texturing operation.  On
Gen7, the WM program must fetch each sample and blend them together
manually.  From the Bspec (Shared Functions/Messages/Initiating
Message/Message Types/sample):

    [DevIVB+]:Number of Multisamples on the associated surface must be
    MULTISAMPLECOUNT_1.

This patch implements the manual blend operation.

Acked-by: Kenneth Graunke <kenneth@whitecape.org>
i965/msaa: Enable 4x MSAA on Gen7.

Basic 4x MSAA support now works on Gen7.  This patch enables it.

As with Gen6, MSAA support is still fairly preliminary.  In
particular, the following are not yet supported:
- 8x oversampling (Gen7 has hardware support for this, but we do not
  yet expose it).
- Fully general blits between MSAA and non-MSAA buffers.
- Formats other than RGBA8, DEPTH24, and STENCIL8.
- Centrold interpolation.
- Coverage parameters (glSampleCoverage, GL_SAMPLE_ALPHA_TO_COVERAGE,
  GL_SAMPLE_ALPHA_TO_ONE, GL_SAMPLE_COVERAGE, GL_SAMPLE_COVERAGE_VALUE,
  GL_SAMPLE_COVERAGE_INVERT).

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
i965/blorp: Implement destination clipping and scissoring

This patch implements clipping and scissoring of the destination rect
for blits that use the blorp engine (e.g. MSAA blits).
glsl/constant propagation: kill whole var if LHS involves array indexing.

When considering which components of a variable were killed by an
assignment, constant propagation would previously just use the write
mask of the assignment.  This worked if the LHS of the assignment was
simple, e.g.:

v.xy = ...; // (assign (xy) (var_ref v) ...)

But it did the wrong thing if the LHS of the assignment involved an
array indexing operator, since in this case the write mask is always
(x):

v[i] = ...; // (assign (x) (deref_array (var_ref v) (var_ref i)) ...)

In general, we can't predict which vector component will be selected
by array indexing, so the only safe thing to do in this case is to
kill the entire variable.

Fixes piglit tests {fs,vs}-vector-indexing-kills-all-channels.shader_test.
WIP: get RGB MSAA to work
MESA_FORMAT_A8 works now
MESA_FORMAT_RGB565 works now
MESA_FORMAT_RGBA_16 works now
MESA_FORMAT_ARGB4444 works now.
MESA_FORMAT_ARGB1555 works now
MESA_FORMAT_ARGB2101010 works now.
Hack: get something to show up for sRGB.  Not correct yet I suspect.
MESA_FORMAT_SARGB8 now partially works