ARC: [3.5] Upstream LTP run - cacheflush syscall formalized

-cachectl.h header expected by userland with @flags expected by
 userland defined {ICACHE,DCACHE,BCACHE}

-Cacheflush syscall beefed up (@flags used) - from Android kernel

-sys_cacheflush() takes @start and @len (vs. start/end)

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: build: .debug_frame not discarded for !CONFIG_ARC_DW2_UNWIND

This adds ~300k of bloat when stack unwinder is not needed

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-arcfpga] PGU driver build broken in 3.2

After these fixes I was able to run QT GUI tests on a 4.10 based XBF

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: unaligned: Fix build breakage with no KGDB || KPROBES

Due to renaming of configuration options, the generic disassembler
was not built when CONFIG_ARC_MISALIGN_ACCESS was enabled and at the
same time CONFIG_KGDB and CONFIG_KPROBES were disabled.

Signed-off-by: Mischa Jonker <mischa.jonker@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] HAPS51 platform introduced

[vgupta: Platform Kconfig reworked: PLAT_HAPS51 => ARC_PLAT_HAPS51]

Signed-off-by: Frank Dols <frank.dols@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] Integrating into arch/arc/ build system

[vgupta: CONFIG_PLAT_HAPS51 => CONFIG_ARC_PLAT_HAPS51]

Signed-off-by: Frank Dols <frank.dols@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] haps51_defconfig

Signed-off-by: Frank Dols <frank.dols@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] add ST mmac support to the platform

Signed-off-by: Frank Dols <frank.dols@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] defconfig update fot ST mmac

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] cosmetics in stmac platform resource array index

Nothing semantical

Signed-off-by: Frank Dols <frank.dols@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] DW interrupt controller device driver

Signed-off-by: Frank Dols <frank.dols@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] DW interrupt controller device driver #2

[vgupta] This is leftover bits of interrupt controller,
piece-meal reconstructed from Frank's orig patches #4 and #5

Signed-off-by: Frank Dols <frank.dols@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: cleanup: TIMER[01]_INT => TIMER[01]_IRQ

Also since TIMER IRQs are always owned by in-core interrupt controller,
move the defines outside platform code.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] DW interrupt controller rework #1

Slap on Update for prev 2 patches:

(1) Rewriting in general
-with request_irq(), struct irqaction usage was completely bogus
-missing __init tag for dw_intc_init()

(2) providing APIs to reduce #ifdef mess
-Alternate defs for IS_EXTERNAL_IRQ(), dw_intc_init()

(3) Generic IRQ Framework Abuse

-dw_intc_do_handle_irq() needs to have specific signature
-Can't define platform specific IRQ_FLG_* for request_irq() as they
 map to completely unrealted options in generic code.

 #define IRQ_FLG_LOCK    (0x0001)  => #define IRQF_TRIGGER_RISING
 #define IRQ_FLG_REPLACE (0x0002)  => #define IRQF_TRIGGER_FALLING
 #define IRQ_FLG_STD     (0x8000)  => #define IRQF_FORCE_RESUME

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] DW interrupt controller rework #2

The ISR loop is fixed:

-generic_handle_irq() now called multiple times, in case multiple
 downstream devices had asserted on intc (i.e. multiple bits set in
 int_status_final reg)

-The loop is now O(N) vs. O(32) before, where N is number of devices
 asserted (which typically would be 1 or 2 at a time).

-loop was starting from 95..32 - now it's 32..95 (more natural)

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] DW interrupt controller rework #3

using I/O accessors to enforce volatile semantics for mem-mapped I/O
Normal memory LD/ST is subject to gcc optimizations.

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] Regression in DW interrupt controller

The commit "DW interrupt controller rework #2" for optimizing the ISR
loop introduced a bug in bit parsing

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] DW interrupt controller rework #4

-CONFIG_DW_INTC_IRQ removed, it can be hardcoded
-DW_INTC_IRQS_NUM => DW_INTC_NBR_OF_IRQS

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] defconfig update including dw_intc

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
ARC: [plat-haps51] UART registration only if CONFIG_SERIAL_8250

Signed-off-by: Vineet Gupta <vgupta@synopsys.com>