quick fix for PR13006, will check in testcase later.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157813 91177308-0d34-0410-b5e6-96231b3b80d8
Remove noisy semicolons.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157814 91177308-0d34-0410-b5e6-96231b3b80d8
PR1255: case ranges.
IntegersSubset devided into IntegersSubsetGeneric and into IntegersSubset itself. The first has no references to ConstantInt and works with IntItem only.
IntegersSubsetMapping also made generic. Here added second template parameter "IntegersSubsetTy" that allows to use on of two IntegersSubset types described below.



git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157815 91177308-0d34-0410-b5e6-96231b3b80d8
Implement the local-dynamic TLS model for x86 (PR3985)

This implements codegen support for accesses to thread-local variables
using the local-dynamic model, and adds a clean-up pass so that the base
address for the TLS block can be re-used between local-dynamic access on
an execution path.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157818 91177308-0d34-0410-b5e6-96231b3b80d8
BoundsChecking: fix a bug when the handling of recursive PHIs failed and could leave dangling references in the cache
add regression tests for this problem.

Can already compile & run: PHP, PCRE, and ICU  (i.e., all the software I tried)

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157822 91177308-0d34-0410-b5e6-96231b3b80d8
testcase for PR13006, thanks to Duncan for filing it.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157824 91177308-0d34-0410-b5e6-96231b3b80d8
Provide move semantics for (Small)BitVector.

CodeGen makes a lot of BitVector copies.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157826 91177308-0d34-0410-b5e6-96231b3b80d8
Add some tests checking that the verifier rejects cases where a definition
doesn't dominate a use.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157829 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: properly handle alignment for struct byval.

Factor out the expansion code into a function.
This change is to be enabled in clang.

rdar://9877866


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157830 91177308-0d34-0410-b5e6-96231b3b80d8
X86: peephole optimization to remove cmp instruction

This patch will optimize the following:
  sub r1, r3
  cmp r3, r1 or cmp r1, r3
  bge L1
TO
  sub r1, r3
  bge L1 or ble L1

If the branch instruction can use flag from "sub", then we can eliminate
the "cmp" instruction.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157831 91177308-0d34-0410-b5e6-96231b3b80d8
Switch some getAliasSet clients to MCRegAliasIterator.

MCRegAliasIterator can optionally visit the register itself, allowing
for simpler code.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157837 91177308-0d34-0410-b5e6-96231b3b80d8
[arm-fast-isel] Fix handling of the frameaddress intrinsic.  If depth is 0
then DestReg is undefined.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157840 91177308-0d34-0410-b5e6-96231b3b80d8
Use dominates(Instruction, Use) in the verifier.
This removes a bit of context from the verifier erros, but reduces code
duplication in a fairly critical part of LLVM and makes dominates easier to test.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157845 91177308-0d34-0410-b5e6-96231b3b80d8
Simplify some more getAliasSet callers.

MCRegAliasIterator can include Reg itself in the list.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157848 91177308-0d34-0410-b5e6-96231b3b80d8
Remove physreg support from adjustCopiesBackFrom and removeCopyByCommutingDef.

After physreg coalescing was disabled, these functions can't do anything
useful with physregs anyway.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157849 91177308-0d34-0410-b5e6-96231b3b80d8
Register the gcov "writeout" at init time. Don't list this as a d'tor. Instead,
inject some code in that will run via the "__mod_init_func" method that
registers the gcov "writeout" function to execute at exit time.

The problem is that the "__mod_term_func" method of specifying d'tors is
deprecated on Darwin. And it can lead to some ambiguities when dealing with
multiple libraries.
<rdar://problem/11110106>


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157852 91177308-0d34-0410-b5e6-96231b3b80d8
Switch all register list clients to the new MC*Iterator interface.

No functional change intended.

Sorry for the churn. The iterator classes are supposed to help avoid
giant commits like this one in the future. The TableGen-produced
register lists are getting quite large, and it may be necessary to
change the table representation.

This makes it possible to do so without changing all clients (again).

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157854 91177308-0d34-0410-b5e6-96231b3b80d8
Remove the old register list functions from MCRegisterInfo.

These functions exposed the layout of the underlying data tables as
null-terminated uint16_t arrays.

Use the new MCSubRegIterator, MCSuperRegIterator, and MCRegAliasIterator
classes instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157855 91177308-0d34-0410-b5e6-96231b3b80d8
In MipsMCInstLower::LowerSymbolOperand, get offset from symbol if
the MachineOperand type has a valid offset. 


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157861 91177308-0d34-0410-b5e6-96231b3b80d8
Expand unaligned i16 loads/stores for the Mips backend.

This is the first of a series of patches which make changes to the backend to
emit unaligned load/store instructions (lwl,lwr,swl,swr) during instruction
selection.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@157862 91177308-0d34-0410-b5e6-96231b3b80d8