powerpc/mpc83xx: fix copyright string in serdes.c

The misspelling of "semiconductor" causes some internal copyright analysis
tools to complain.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
powerpc/mpc83xx: increment malloc heap size

extention of commit 3b6b256 "powerpc/mpc83xx: increment
malloc heap size for the MPC832x MDS boards" to all other
mpc83xx based boards.  It fixes "Unable to save the rest
of sector" messages when trying to save the environment
to flash.

Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
powerpc/85xx: Add USB device-tree fixup for various platforms

Add USB device-tree fixup for following platforms:
MPC8536DS, P1022DS, P1023RDS, P2020COME, P2020DS, P2041RDB, P3060QDS

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
powerpc/mpc85xx:Add BSC9131/BSC9130/BSC9231 Processor Support

- BSC9131 is integrated device that targets Femto base station market.
   It combines Power Architecture e500v2 and DSP StarCore SC3850 core
   technologies with MAPLE-B2F baseband acceleration processing elements.
 - BSC9130 is exactly same as BSC9131 except that the max e500v2
   core and DSP core frequencies are 800M(these are 1G in case of 9131).
 - BSC9231 is similar to BSC9131 except no MAPLE

The BSC9131 SoC includes the following function and features:
    . Power Architecture subsystem including a e500 processor with 256-Kbyte shared
      L2 cache
    . StarCore SC3850 DSP subsystem with a 512-Kbyte private L2 cache
    . The Multi Accelerator Platform Engine for Femto BaseStation Baseband
      Processing (MAPLE-B2F)
    . A multi-standard baseband algorithm accelerator for Channel Decoding/Encoding,
     Fourier Transforms, UMTS chip rate processing, LTE UP/DL Channel processing,
     and CRC algorithms
    . Consists of accelerators for Convolution, Filtering, Turbo Encoding,
     Turbo Decoding, Viterbi decoding, Chiprate processing, and Matrix Inversion
     operations
    . DDR3/3L memory interface with 32-bit data width without ECC and 16-bit with
     ECC, up to 400-MHz clock/800 MHz data rate
    . Dedicated security engine featuring trusted boot
    . DMA controller
    . OCNDMA with four bidirectional channels
    . Interfaces
    . Two triple-speed Gigabit Ethernet controllers featuring network acceleration
      including IEEE 1588. v2 hardware support and virtualization (eTSEC)
    . eTSEC 1 supports RGMII/RMII
    . eTSEC 2 supports RGMII
    . High-speed USB 2.0 host and device controller with ULPI interface
    . Enhanced secure digital (SD/MMC) host controller (eSDHC)
    . Antenna interface controller (AIC), supporting three industry standard
      JESD207/three custom ADI RF interfaces (two dual port and one single port)
      and three MAXIM's MaxPHY serial interfaces
    . ADI lanes support both full duplex FDD support and half duplex TDD support
    . Universal Subscriber Identity Module (USIM) interface that facilitates
      communication to SIM cards or Eurochip pre-paid phone cards
    . TDM with one TDM port
    . Two DUART, four eSPI, and two I2C controllers
    . Integrated Flash memory controller (IFC)
    . TDM with 256 channels
    . GPIO
    . Sixteen 32-bit timers

The DSP portion of the SoC consists of DSP core (SC3850) and various
accelerators pertaining to DSP operations.

This patch takes care of code pertaining to power side functionality only.

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
powerpc/mpc85xx:Add BSC9131 RDB Support

BSC9131RDB is a Freescale reference design board for BSC9131 SoC. BSC9131 SOC
 is an integrated device that targets Femto base station market. It combines
 Power Architecture e500v2 and DSP StarCore SC3850 core technologies with
 MAPLE-B2F baseband acceleration processing elements

  BSC9131RDB Overview
   -----------------
     -1Gbyte DDR3 (on board DDR)
     -128Mbyte 2K page size NAND Flash
     -256 Kbit M24256 I2C EEPROM
     -128 Mbit SPI Flash memory
     -USB-ULPI
     -eTSEC1: Connected to RGMII PHY
     -eTSEC2: Connected to RGMII PHY
     -DUART interface: supports one UARTs up to 115200 bps for console display
Apart from the above it also consists various peripherals to support DSP
functionalities.

This patch adds support for mainly Power side functionalities and peripherals

Signed-off-by: Ramneek Mehresh <ramneek.mehresh@freescale.com>
Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com>
Signed-off-by: Akhil Goyal <Akhil.Goyal@freescale.com>
Signed-off-by: Rajan Srivastava <rajan.srivastava@freescale.com>
Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
powerpc/p1010rdb: update mux config of p1010rdb board

On p1010rdb some signals are muxed for tdm/can/uart/flash.
If we don't set fsl_p1010mux:tdm_can to "can" or "tdm" explicitly,
defaultly we keep spi chip selection to spi-flash instead of to
tdm/slic and disable uart1 when not using flexcan, as well disable sdhc.

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
PATCH 1/4][v4] doc:Add documentation for e500 external debugger support

This describes requirement of e500 and e500v2 processor to support external
debugger.

It also provide an insight of the configuration switch required and their
description.

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
powerpc/85xx:Fix MSR[DE] bit in MSR to support debugger

Debugging of e500 and e500v1 processer requires MSR[DE] bit to be set always.
Where MSR = Machine State register

Make sure of MSR[DE] bit is set uniformaly across the different execution
address space i.e. AS0 and AS1.

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Catalin Udma <catalin.udma@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
powerpc/85xx:Make debug exception vector accessible

Debugging of e500 and e500v1 processer requires debug exception vecter (IVPR +
IVOR15) to have valid and fetchable OP code.

1) While executing in translated space (AS=1), whenever a debug exception is
generated, the MSR[DS/IS] gets cleared i.e. AS=0 and the processor tries to
fetch an instruction from the debug exception vector (IVPR + IVOR15); since now
we are in AS=0, the application needs to ensure the proper TLB configuration to
have (IVOR + IVOR15) accessible from AS=0 also.
Create a temporary TLB in AS0 to make sure debug exception verctor is
accessible on debug exception.

2) Just after relocation in DDR, Make sure IVPR + IVOR15 points to valid opcode

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
powerpc/85xx:Fix NAND code base to support debugger

Update NAND code base to ovecome e500 and e500v2's second limitation i.e. IVPR
+ IVOR15 should be valid fetchable OP code address.

As NAND SPL does not compile vector table so making sure IVOR + IVOR15 points to
any fetchable valid data

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Marius Grigoras <marius.grigoras@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
powerpc/mpc85xx:Add debugger support for e500v2 SoC

Freescale's e500v1 and e500v2 cores (used in mpc85xx chips) have some
restrictions on external debugging (JTAG).

So define CONFIG_SYS_PPC_E500_DEBUG_TLB to enable a temporary TLB entry to be
used during boot to work around the limitations.

Please refer doc/README.mpc85xx for more information

Signed-off-by: Radu Lazarescu <radu.lazarescu@freescale.com>
Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
powerpc/mpc85xx:NAND_SPL:Avoid IFC/eLBC Base address setting

During NAND_SPL boot, base address and different register are programmed
default by corresponding NAND controllers(eLBC/IFC). These settings are
sufficient enough for NAND SPL.

Avoid updating these register.They will be programmed during NAND RAMBOOT.

Signed-off-by: Prabhakar Kushwaha <prabhakar@freescale.com>
powerpc/p1010rdb: add readme document for p1010rdb

Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
powerpc/85xx: minor clean-ups to the P2020DS board header file

Remove some unused macros and remove all #undef macros.

The RTL8139 network adapter is not shipped with the board nor commonly
used, so don't define it by default.  The E1000 is still defined.

Add 57,600 baud as an option.  For some reason, this baud rate is missing
from many boards.

Signed-off-by: Timur Tabi <timur@freescale.com>
powerpc/85xx: fdt_set_phy_handle() should return an error code

fdt_set_phy_handle() makes several FDT calls that could fail, so it should
not be hiding these errors.

Signed-off-by: Timur Tabi <timur@freescale.com>
powerpc/85xx: clean up P1022DS board configuration header file

Remove some unused default environment variables (memctl_intlv_ctl,
perf_mode, diuregs, dium, and diuerr), update 'tftpflash' variable,
and add videobootargs as a Linux command line variable (so that we can
easily pass video= to the kernel).

Signed-off-by: Timur Tabi <timur@freescale.com>
lib/powerpc: addrmap_phys_to_virt() should return a pointer

addrmap_phys_to_virt() converts a physical address (phys_addr_t) to a
virtual address, so it should return a pointer instead of an unsigned long.
Its counterpart, addrmap_virt_to_phys(), takes a pointer, so now they're
orthogonal.

The only caller of addrmap_phys_to_virt() converts the return value to
a pointer anyway.

Signed-off-by: Timur Tabi <timur@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
powerpc/P4080: Check SVR for CPU22 workaround

Workaround for erratum CPU22 applies to P4080 rev 1 and rev 2 only.

Signed-off-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: Ignore E bit for SVR_SOC_VER()

We don't care E bit of SVR in most cases. Clear E bit for SVR_SOC_VER().
This will simplify the coding. Use IS_E_PROCESSOR() to identify SoC with
encryption. Remove all _E entries from SVR list and CPU list.

Signed-off-by: York Sun <yorksun@freescale.com>
powerpc/mpc85xx: Workaround for erratum CPU_A011

Erratum NMG_CPU_A011 applies to P4080 rev 1.0, 2.0, fixed in rev 3.0.
It also applies to P3041 rev 1.0, 1.1, P2041 rev 1.0, 1.1. It shares the
same workaround as erratum CPU22. Rearrange registers usage in assembly
code to avoid accidental overwriting.

Signed-off-by: York Sun <yorksun@freescale.com>