ARM: tegra: power: Report LP3 state if LP2 is not allowed

Properly report LP3 state to idle governor when LP2 entry is not
allowed and LP2 request is redirected to LP3.

Reviewed-on: http://git-master/r/77956

Change-Id: If4bdf6b635d7b40a8958dc5357903c4ea563d112
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78697
Reviewed-by: Automatic_Commit_Validation_User
ARM:tegra:power Set awake system CPU floor
mmc: Set suspend/resume bus operations if CONFIG_PM_RUNTIME is used

Signed-off-by: Dmitry Shmidt <dimitrysh@google.com>
sched: disable GENTLTE_FAIR_SLEEPERS for better performance on Android
ARM: vfp: only clear vfp state for current cpu in vfp_pm_suspend

vfp_pm_suspend runs on each cpu, only clear the hardware state
pointer for the current cpu.  Prevents a possible crash if one
cpu clears the hw state pointer when another cpu has already
checked if it is valid.

Change-Id: I997ab1554944eba86730818ff242d7ebe1b32736
Signed-off-by: Colin Cross <ccross@android.com>
process.c cleanups
sched/nohz: Fix rq->cpu_load[] calculations

While investigating why the load-balancer did funny I found that the
rq->cpu_load[] tables were completely screwy.. a bit more digging
revealed that the updates that got through were missing ticks followed
by a catchup of 2 ticks.

The catchup assumes the cpu was idle during that time (since only nohz
can cause missed ticks and the machine is idle etc..) this means that
esp. the higher indices were significantly lower than they ought to
be.

The reason for this is that its not correct to compare against jiffies
on every jiffy on any other cpu than the cpu that updates jiffies.

This patch cludges around it by only doing the catch-up stuff from
nohz_idle_balance() and doing the regular stuff unconditionally from
the tick.

Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Cc: pjt@google.com
Cc: Venkatesh Pallipadi <venki@google.com>
Link: http://lkml.kernel.org/n/tip-tp4kj18xdd5aj4vvj0qg55s2@git.kernel.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
modified for Linux 3.0 from Linux 3.4+ by faux123
ARM: tegra: power: Re-factor Tegra3 secondary CPU LP2 entry

When Tegra3 secondary CPU is entering LP2, read TWD timer state
into context structure, rather than separate local variables.

Reviewed-on: http://git-master/r/77957

Change-Id: I237eafc50a11d535b94f334631d039ba9c4bf44b
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78899
Reviewed-by: Automatic_Commit_Validation_User
modified for HTC One X kernel from nv reference by faux123
ARM: tegra: power: Separate lp2 latency for G/LP CPU modes

Do not use common lp2 exit latency for Tegra3 CPU G and CPU LP modes.
Separately measure and adjust latency in each mode; restart calculation
after mode switch from the last measured latency in the target mode.

Reviewed-on: http://git-master/r/78344

Change-Id: I54803c6abf4107a578aa1fed8feaa4a419a9c07f
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78902
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
ARM: tegra: power: Separate lp2 latency for secondary CPUs

Do not use common lp2 exit latency for Tegra3 secondary CPUs in
G mode. Separately measure and adjust latency on each slave CPU;
use per-cpu latency to determine target residency threshold for
entering lp2 on each CPU.

Reviewed-on: http://git-master/r/78375

Change-Id: I4470d1b4814d8f12129e21105dd952a903084f1e
Signed-off-by: Alex Frid <afrid@nvidia.com>
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
Reviewed-on: http://git-master/r/78903
Reviewed-by: Automatic_Commit_Validation_User
modified for HTC One X kernel from nv reference by faux123
ARM: tegra: power: Don't over-sleep LP2 on secondary CPUs

Adjust Tegra3 secondary CPU LP2 time for exit latency to avoid
scheduler event over-sleep.

Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/78635
(cherry picked from commit 433a3e356a0281efb1caf9b78bb1576008a58ed2)

Change-Id: Ifd298f0a4364fe4775ae209d76b2eda24b1bfefc
Signed-off-by: Pritesh Raithatha <praithatha@nvidia.com>
Reviewed-on: http://git-master/r/82709
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
Tested-by: Bharat Nihalani <bnihalani@nvidia.com>
Reviewed-by: Aleksandr Frid <afrid@nvidia.com>
Tested-by: Aleksandr Frid <afrid@nvidia.com>
modified for HTC One X kernel from nv reference by faux123
ARM: tegra: power: Add external LP2 wake timers on secondary CPUs

Add an option to use external timer as Tegra3 secondary CPU wake
source from lp2 (power gated) state. This is a follow up to commit
51e6be9ce103fbeb2b73fa2a9d2b6528a6941e81 that disabled wake from
external timer, since its interrupt is registered too late - after
secondary CPU is brought on-line, and already had a chance to enter
lp2. With this commit, secondary CPU is not allowed to enter lp2 in
idle until wake timer is registered (clock-gated lp3 state is entered
instead).

External timer wake up mechanism is enabled on Tegra3 only if option
HAVE_ARM_TWD is not selected. Otherwise, continue to use local CPU
timers as lp2 wake sources.

Change-Id: Ic8c33f55e77174717bfa6525041e1263d3232dd5
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/83546
Reviewed-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
Tested-by: Rohan Somvanshi <rsomvanshi@nvidia.com>
modified for HTC One X kernel from nv reference by faux123
ARM: tegra: power: Power off multiple CPUs on-line

Currently on Tegra3 cpu complex is powered off in idle (enters CPU0
LP2 state) only if all secondary CPUs are off-line. This commit adds
an option for CPU0 to enter LP2 while secondary CPUs are still on-line
but have been power gated and entered LP2 state by themselves.

The critical race: secondary CPU is waking up from LP2, while CPU0 is
turning common CPU rail off, is addressed as follows.

1. When entering LP2 state on CPU0:
a) disable GIC distributor
b) check that CPU1-3 are all power-gated (i.e., either off-lined or
have entered LP2)
c) if (b) passes - set all interrupts affinity to CPU0, then
re-enable distributor and continue with CPU complex powering off
d) if (b) fails - re-enable distributor and enter clock-gated (LP3)
state on CPU0
This procedure prevents waking secondary CPUs by GIC SPIs.

2. We still need to make sure that no CPU1-3 PPIs from legacy IRQ/FIQ
or private timers would happen. This is achieved by disabling timers
and legacy interrupts if CPU1-3 enters LP2 state with external timers
selected as wake sources. Respectively, establish dependency between
turning rail off and LP2 wake timers configuration options.

3. Finally, no IPIs is sent by CPU0 entering LP2.

There are no special changes in wake up procedures - whenever CPU0
is awaken by external interrupt or wake timer, cpu complex is powered
on by h/w, and secondary CPUs that were in LP2 state are ungated by
the same interrupt (off-line CPUs are kept power gated). Hence, there
is no need for CPU1-3 external wake timers to run while the rail is
off, and these timers are stopped. To make sure that none of secondary
CPUs over-sleeps its LP2 time, CPU0 wake timer is set to minimum sleep
interval of all CPUs.

By default configuration option for powering off multiple on-line CPUs
is disabled on Tegra3.

Change-Id: I4920d0df375536b2b8ebd9e6738c5fe4f92b92a0
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/83547
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
modified for HTC One X kernel from nv reference by faux123
ARM: tegra: power: Fix LP2 timers suspend/resume

On entry/exit to suspend state remove/restore Tegra3 LP2 wake timers
interrupts affinity to the respective secondary CPUs.

Change-Id: I9b46c5fa446a8c6e813343f4564abda5313853da
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/87541
Reviewed-by: Scott Williams <scwilliams@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Reviewed-by: Krishna Reddy <vdumpa@nvidia.com>
ARM: tegra: clock: Update secondary pll dividers resume

During resume from LP0 on Tegra3 always enable pll secondary dividers
before clocks restoration (to make sure clock sources are enabled).
Restore actual secondary dividers settings after clocks are restored.

Remove pllp secondary dividers restoration from cpu complex restore,
and add them to common clock restoration procedure. These dividers
are not affected by CPU complex suspend, only by LP0 core suspend.

Signed-off-by: Alex Frid <afrid@nvidia.com>
(cherry picked from commit 1f631436717c0602ef30770f7976615150114afe)

Change-Id: I45777ca0535f51a39c35e9d360ac6e97a13ea92c
Reviewed-on: http://git-master/r/84712
Reviewed-by: Lokesh Pathak <lpathak@nvidia.com>
Tested-by: Lokesh Pathak <lpathak@nvidia.com>
arm: tegra: xmm power state handling

Avoid unwanted xmm power state changes.
Added missing spin_unlock_irqrestore.

Bug 935834
Bug 938553

Signed-off-by: Seshendra Gadagottu<sgadagottu@nvidia.com>
Reviewed-on: http://git-master/r/82796
(cherry picked from commit 8af674aadfc1196851d5a2ecd1ecdd2cfe2d4148)

Change-Id: Ic5b354376c0239773762d1b0f6e8848491e74e08
Reviewed-on: http://git-master/r/87503
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
modified for HTC One X from NV 3.1 reference by faux123
arm: tegra: xmm: add enable_irq_wake in probe

Add enable_irq_wake in probe to enable gpio irq wake.

Bug 928950

Signed-off-by: Seongho Joo <sjoo@nvidia.com>
Reviewed-on: http://git-master/r/85972
(cherry picked from commit e81069047c14a0ab9a3e1eb5588060959d550c49)

Change-Id: Ic513179670661ddc8a75d73a0afaa6264847cb1a
Reviewed-on: http://git-master/r/87644
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
use cpu friendly wait_for_completions

Be nice to CPU and don't hog the resources, use a nice wait_for_interruptible
timeout for completions instead of wait_for_timeout which is
non-interruptible.

Change-Id: I87542c2980978543bc3832f45592b719a61ba5b8
Signed-off-by: Pavan Savoy <pavan_savoy@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
modified for HTC One X kernel from Omapzoom by faux123
ti-st: use msleep_interruptible instead of mdelay

Be nice to CPU and use msleep_interruptible instead of msleep which chops the
CPU up into a spin loop.
Used for all delays > 20ms.

Change-Id: I8f84ff34d9191e8fde9af28f81681470571c0b51
Signed-off-by: Pavan Savoy <pavan_savoy@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
modified for HTC One X kernel from omapzoom by faux123
usb: rndis: Avoid unwanted usb config access

Request complete may be called when there is no valid usb config
Avoid access to config when not required.

Bug 949543

Signed-off-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-on: http://git-master/r/91151
(cherry picked from commit 08bc68164d0bd90c84a8ea82f87f9f44e4341df2)

Change-Id: I5969144aaa9bcffddefa7933d43bfd3690814fba
Reviewed-on: http://git-master/r/93816
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Tested-by: Krishna Yarlagadda <kyarlagadda@nvidia.com>
Reviewed-by: Venkat Moganty <vmoganty@nvidia.com>
modified for HTC One X from nv reference by faux123