Fix inconsistent surface dimension during allocating surface buffer object

When one surface is created, the height/width is aligned to 16 pixels.
But when trying to allocate the buffer object for it, the width is aligned
to 128 and height is aligned to 32. If the surface is mapped and accessed
before allocating the buffer object, the APP will get the incorrect dimension.

From: Zhao Yakui <yakui.zhao@intel.com>
Add haswell PCI IDs

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
haswell: use at least 64 URB entries for GT2+.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
intel: fix max number of threads used on Ivy Bridge.

Fix the max number of threads to be used on Ivy Bridge. In particular,
the GEN7_PS_MAX_THREADS_SHIFT offset was wrong, thus causing the GPU
to use half of what was specified.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
haswell: fix max PS threads shift value.

The maximum number of threads is now a 9-bit value. Thus, one more bit
towards LSB was re-used. i.e. bit position is now 23 instead of 24 on
Ivy Bridge.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
haswell: fix 3DSTATE_PS to fill in number of samples.

The sample mask value must match what is set for 3DSTATE_SAMPLE_MASK,
through gen7_emit_invarient_states().

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
haswell: set "Shader Channel Select" fields in surface state.

For normal behaviour, each Shader Channel Select should be set to the
value indicating that same channel. i.e. Shader Channel Select Red is
set to SCS_RED, Shader Channel Select Green is set to SCS_GREEN, etc.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
haswell: fix render kernels.

Regenerate render kernels for Haswell because JMPI instruction semantics
changed there. In particular, the offset is now expressed in bytes instead
of 64-bit units.

Signed-off-by: Gwenole Beauchesne <gwenole.beauchesne@intel.com>
Add the separated file for media encoding on haswell

There exist a lot of changes about the media encoder between Haswell
and IvyBridge. For example: the VME programming and the corresponding
general media command. To be simple, the separated files are added for Haswell.
Otherwise it has to consider the complex backward compatibility.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Add the seperated file for media decoding on Haswell

As the MFX involves quite a lot of changes between Ivy and Haswell,
the seperated file is added for the media decoding on haswell. This
can avoid the complex backward logic for Ivy.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Add the Intra VME for I-frame on Haswell

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Add the support of encoding P frame on haswell

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Handle the MFX change between A stepping and B-stepping for haswell

The A0-stepping is still covered.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Haswell: Disable Picture ID Remapping for AVC decoding

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Unify the code for xxx_free_avc_surface

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Fix thread issue with AVC private surafce

https://bugs.freedesktop.org/show_bug.cgi?id=55282

Signed-off-by: Gautam <manamgautam@gmail.com>
Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
VPP: enabling scaling function for post processing

Signed-off-by: Li,Xiaowei A <xiaowei.a.li@intel.com>
VEBox: add special batch command and macro for VEBox command streamer

VEBox is a new feature introducted in haswell, which aims
to do video process through fixed functions, it also owns
one seperated command streamer.

Signed-off-by: Li,Xiaowei A  <xiaowei.a.li@intel.com>
VEBox: setup haswell vebox pipeline for video post process

Currently, deinterlacing, denoise, color balance, color space conversion
are supported by vebox pipeline, and only deinterlace is exposed to video
post process on haswell.

Signed-off-by: Li,Xiaowei A  <xiaowei.a.li@intel.com>
Make it built against the current upstream libdrm

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>