input: misc: fix light level issue at resume

The light level is very low at the beginning of resume if auto
backlight level is enabled.
Remove the trigger event code with zero value code and directly
report the actual adc level to fix the issue.

Bug 1005271

Change-Id: I225f2b2b07e676d736ea5cd116cdc769d57ce2f2
Signed-off-by: Chandler Zhang <chazhang@nvidia.com>
Reviewed-on: http://git-master/r/112892
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
arm: tegra: pcie: Resolve L4T ethernet failure

1. Removed the stop/add pci devices after rescan to
   avoid panic in 2nd time suspend for L4T.
2. Moved the setting irq code before adding devices
   to avoid probe failure for usb3.

Bug 959642
Bug 946385
Bug 1009086

Change-Id: Ia425a4e11667f6f2f110eb68d63c8fb229486c21
Signed-off-by: Jay Agarwal <jagarwal@nvidia.com>
Reviewed-on: http://git-master/r/112959
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
ARM: tegra: fuse: Fix sysfs output

Adding extra byte for null character. Without this
string concatenation of fuse read will be erratic.

Bug 1007619

Change-Id: Idbb5f997840f5ed27418d5b0b8dfbc9516354f4c
Signed-off-by: Animesh Kishore <ankishore@nvidia.com>
Reviewed-on: http://git-master/r/112974
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
ARM: cpuquiet: Go to and stay on G-CPU if min_cpus 1 is requested

Only return to LP-CPU if minimum number of cpus requested by the PM QoS
interface is at the default 0 level.

Change-Id: I1384c7fc62b86e385e10b4baaf81eb600f31da6e
Signed-off-by: Sai Charan Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/109831
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: add sysfs support for tegra cpuquiet driver

Change-Id: I215c5de8e98d139a93113978e1e27adb5a6b252c
Signed-off-by: Sai Charan Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/111283
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
cpuquiet: Properly return the first registered governor

Change-Id: I8a21a15d5cf8e4c91a166810387b5d8f1dd7cdb6
Signed-off-by: Sai Charan Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/111284
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
cpuquiet: Update stats only on successful operations

Change-Id: I0584fba7458b3a860f9ab3751a8eb5f0345864ad
Signed-off-by: Sai Charan Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/111285
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
cpuquiet: Fix compiler warning

Change-Id: I03c11c295b40ebd500a715974f7fdca560d9a43a
Signed-off-by: Sai Charan Gurrappadi <sgurrappadi@nvidia.com>
Reviewed-on: http://git-master/r/111286
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
ARM: tegra: kai: Add platform data to spi_device1

Adding platform data to spi_device1 and limiting
buffer to 128

Bug 1007899

Change-Id: I9c421cb18215f7db94bbaeae00bc46235edece05
Signed-off-by: aghuge <aghuge@nvidia.com>
Reviewed-on: http://git-master/r/112143
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
ARM: tegra: cardhu: enable clock gating features for E1506 panel

Enable clock gating features for 720p DSI panel on the E1506.

Change-Id: I554c31a6697d5a9e37cab21418fb08477503d82d
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/113030
Reviewed-by: Kevin Huang (Eng-SW) <kevinh@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
misc: tegra-baseband: treat compilation warning as error

- Handling warning of wrong return type from function.

bug 949219

Change-Id: I49e74de9314ee4934a5a58a8e406f9bade278aaf
Signed-off-by: Sanjay Singh Rawat <srawat@nvidia.com>
Reviewed-on: http://git-master/r/112906
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Sachin Nikam <snikam@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
ARM: tegra: p1852: defconfig: disable erratum 727915.

PL310_ERRATA_727915 holds for PL310 revision r2p0 which
is there in T20. T30 has PL310 r3p1.

bug 820324

Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/111169
(cherry picked from commit 1e29090d6d700f6afb39828e93605d5742847271)

Change-Id: I01516eedbb6bfaec3e3b619d47e30ff54dfb2824
Reviewed-on: http://git-master/r/113267
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Manoj Chourasia <mchourasia@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Sandeep Trasi <strasi@nvidia.com>
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
ARM: tegra: p1852_defconfig: enable NON_ALIASED_COHERENT_MEM

Enabling CONFIG_NON_ALIASED_COHERENT_MEM in p1852 defconfig
to avoid coherent memmory aliasing.

also enabling ARM_ERRATA_742230

bug 965047

Signed-off-by: Manoj Chourasia <mchourasia@nvidia.com>
Reviewed-on: http://git-master/r/111174
(cherry picked from commit 086cfc1330df0a158e865d39af48d71d15fd5730)

Change-Id: I410bc14e0c062d14bbfc4b7cfa722a20465010de
Reviewed-on: http://git-master/r/113268
Reviewed-by: Automatic_Commit_Validation_User
Tested-by: Manoj Chourasia <mchourasia@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Varun Wadekar <vwadekar@nvidia.com>
arm: config: tegra2: Enable CONFIG_THERMAL

Enable CONFIG_THERMAL option so that Linux Thermal Sysfs
framework and Tegra Thermal Throttling are enabled.

Bug 1002374
Signed-off-by: Preetham Chandru R <pchandru@nvidia.com>

Change-Id: Ied33df234c9484abbb232036e6fca44fc6d308a1
Reviewed-on: http://git-master/r/111516
Tested-by: Preetham Chandru <pchandru@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Wei Ni <wni@nvidia.com>
Reviewed-by: Kiran Adduri <kadduri@nvidia.com>
Reviewed-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
ARM: Tegra: p1852: changed pinmux settings

Pinmux updated as per the latest pinmux sheet.

Bug 978870

Change-Id: I122439df3d043216f1c8c2c1a0a3c88e74d760ee
Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/111573
(cherry picked from commit 4e65d7d21b5ac5b25e3563ce6a7eb50cf1d8128d)
Reviewed-on: http://git-master/r/103340
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
video: tegra: nvmap: Use trace points in NvMap.

Change-Id: I2a5f0c9305bd53c42df181556d97efa5d6792ad7
Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
Reviewed-on: http://git-master/r/106500
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Bo Yan <byan@nvidia.com>
video: tegra: host: Exclude suspend/resume if disabled

Compile power management suspend and resume functions only when
CONFIG_PM is enabled.

Change-Id: If349984d62ed002594ba60ac25cd4dddd956aa6c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/109425
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Mayuresh Kulkarni <mkulkarni@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
video: tegra: host: Register devices in SoC files

Move the device structures to the driver source code files. Register
all nvhost_device's in one loop which is called from board file.

host1x driver code is moved to live under host1x, too. This causes
a need to add host to include path of tegradc and nvavp.

Bug 982965

Change-Id: If99cf9d1ef6bc24663ee8294c19370429ed04ca7
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/104076
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
video: tegra: host: Parametrize host1x

Add parameters in host1x nvhost_device on
* number of sync points
* number of wait bases
* number of channels
* number of mlocks
* client managed bitmask
* naming of sync points

Add automatically generated headers and use symbols from them to
access hardware.

Move host1x device definition from generic host1x to SoC specific
source files t20.c and t30.c.

Bug 982965

Change-Id: Ibec84be22d75b363900d10bcbd59d4d8321d54a1
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/104974
Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com>
video: tegra: dc: Move #includes from dc_priv.h

Move #include directives for nvhost headers from dc_priv.h to the
source files that need the #includes. This allows #including
dc_priv.h without access to all nvhost headers.

Also adds nvhost to the #include path of dc to allow making dev.h a
stub in a later commit.

Bug 982965

Change-Id: Icfe7084d295f57926195b178174f81047eb01187
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/108225
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>