SmallVector: Make use of move semantics to speed up moving objects in erase() and insert()

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159914 91177308-0d34-0410-b5e6-96231b3b80d8
Remove some trivial copy ctors so the classes become trivially copyable and get the optimized SmallVector implementation.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159916 91177308-0d34-0410-b5e6-96231b3b80d8
Teach the assembler to use the narrow thumb encodings of various three-register dp instructions where permissable.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159935 91177308-0d34-0410-b5e6-96231b3b80d8
Spelling!


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159936 91177308-0d34-0410-b5e6-96231b3b80d8
Prevent ARM assembler from losing a right shift by #32 applied to a register


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159937 91177308-0d34-0410-b5e6-96231b3b80d8
Fix instruction description of VMOV (between two ARM core registers and two single-precision resiters)


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159938 91177308-0d34-0410-b5e6-96231b3b80d8
Oops - correct broken disassembly for VMOV


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159945 91177308-0d34-0410-b5e6-96231b3b80d8
Some formatting to keep Clang happy


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159948 91177308-0d34-0410-b5e6-96231b3b80d8
instcombine: merge the functions that remove dead allocas and dead mallocs/callocs/...
This patch removes ~70 lines in InstCombineLoadStoreAlloca.cpp and makes both functions a bit more aggressive than before :)
In theory, we can be more aggressive when removing an alloca than a malloc, because an alloca pointer should never escape, but we are not taking advantage of this anyway

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159952 91177308-0d34-0410-b5e6-96231b3b80d8
Reapply r158846.

Access mips register classes via MCRegisterInfo's functions instead of via the
TargetRegisterClasses defined in MipsGenRegisterInfo.inc.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159953 91177308-0d34-0410-b5e6-96231b3b80d8
X86: implement functions to analyze & synthesize CMOV|SET|Jcc
getCondFromSETOpc, getCondFromCMovOpc, getSETFromCond, getCMovFromCond

No functional change intended.
If we want to update the condition code of CMOV|SET|Jcc, we first analyze the
opcode to get the condition code, then update the condition code, finally
synthesize the new opcode form the new condition code.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159955 91177308-0d34-0410-b5e6-96231b3b80d8
Teach the DAG combiner to turn sitofp/uitofp from i1 into a conditional move, since there are only two possible values.
Previously, this would become an integer extension operation, followed by a real integer->float conversion.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159957 91177308-0d34-0410-b5e6-96231b3b80d8
indentation

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159958 91177308-0d34-0410-b5e6-96231b3b80d8
Machine model: allow itineraries to be shared by different processor models.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159959 91177308-0d34-0410-b5e6-96231b3b80d8
Revert r159938 (and r159945) to appease the buildbots.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159960 91177308-0d34-0410-b5e6-96231b3b80d8
Delete code for folding undefs in ScalarEvolution. It's invalid in
obscure ways, and it isn't actually important in the real world.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159969 91177308-0d34-0410-b5e6-96231b3b80d8
Make register Mips::RA allocatable if not in mips16 mode.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159971 91177308-0d34-0410-b5e6-96231b3b80d8
Allow intrinsics to be used in place of node matchables.

TableGen has support for using an intrinics name directly in a DAG,
but this breaks down when referring to just a node, as that's
handled initializer list stuff entirely via subclassing in the
parser. That is, using an instrinsic like "(int_my_intrinsic ...)"
works fine. Using it standalone for parameterizing the operator
in such a DAG does not.

Fixing this is simple enough, as we simply declare Intrinsic
as deriving from SDPatternOperator, which is the class name
intended for exactly this purpose in TargetSelectionDAG.td.

When the intrinsic is actually used in the DAG pattern, it will
be recognized and expanded to an intrinsic_wo_chain (et. al.)
just like when it's used directly.

Incoming ARM NEON cleanup based on this and a bit of functionality
improvement after that.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159973 91177308-0d34-0410-b5e6-96231b3b80d8
ARM: Allow more flexible patterns in NEON formats.

Some NEON instructions want to match against normal SDNodes for some
operand types and Intrinsics for others. For example, CTLZ. To enable this,
switch from explicitly requiring Intrinsic on the class templates to using
SDPatternOperator instead.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@159974 91177308-0d34-0410-b5e6-96231b3b80d8