ARM: Use TTBR1 instead of reserved context ID

On ARMv7 CPUs that cache first level page table entries (like the
Cortex-A15), using a reserved ASID while changing the TTBR or flushing
the TLB is unsafe.

This is because the CPU may cache the first level entry as the result of
a speculative memory access while the reserved ASID is assigned. After
the process owning the page tables dies, the memory will be reallocated
and may be written with junk values which can be interpreted as global,
valid PTEs by the processor. This will result in the TLB being populated
with bogus global entries.

This patch avoids the use of a reserved context ID in the v7 switch_mm
and ASID rollover code by temporarily using the swapper_pg_dir pointed
at by TTBR1, which contains only global entries that are not tagged
with ASIDs.

Reviewed-by: Frank Rowand <frank.rowand@am.sony.com>
Tested-by: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
[catalin.marinas@arm.com: add LPAE support]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on ASID-capable CPUs

Since the ASIDs must be unique to an mm across all the CPUs in a system,
the __new_context() function needs to broadcast a context reset event to
all the CPUs during ASID allocation if a roll-over occurred. Such IPIs
cannot be issued with interrupts disabled and ARM had to define
__ARCH_WANT_INTERRUPTS_ON_CTXSW.

This patch changes the check_context() function to
check_and_switch_context() called from switch_mm(). In case of
ASID-capable CPUs (ARMv6 onwards), if a new ASID is needed and the
interrupts are disabled, it defers the __new_context() and
cpu_switch_mm() calls to the post-lock switch hook where the interrupts
are enabled. Setting the reserved TTBR0 was also moved to
check_and_switch_context() from cpu_v7_switch_mm().

Reviewed-by: Will Deacon <will.deacon@arm.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Frank Rowand <frank.rowand@am.sony.com>
Tested-by: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on pre-ARMv6 CPUs

This patch removes the __ARCH_WANT_INTERRUPTS_ON_CTXSW definition for
ARMv5 and earlier processors. On such processors, the context switch
requires a full cache flush. To avoid high interrupt latencies, this
patch defers the mm switching to the post-lock switch hook if the
interrupts are disabled.

Reviewed-by: Will Deacon <will.deacon@arm.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Frank Rowand <frank.rowand@am.sony.com>
Tested-by: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
ARM: Remove current_mm per-cpu variable

The current_mm variable was used to store the new mm between the
switch_mm() and switch_to() calls where an IPI to reset the context
could have set the wrong mm. Since the interrupts are disabled during
context switch, there is no need for this variable, current->active_mm
already points to the current mm when interrupts are re-enabled.

Reviewed-by: Will Deacon <will.deacon@arm.com>
Tested-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Frank Rowand <frank.rowand@am.sony.com>
Tested-by: Marc Zyngier <Marc.Zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
mm: Limit pgd range freeing to mm->task_size

ARM processors with LPAE enabled use 3 levels of page tables, with an
entry in the top level (pgd) covering 1GB of virtual space. Because of
the branch relocation limitations on ARM, the loadable modules are
mapped 16MB below PAGE_OFFSET, making the corresponding 1GB pgd shared
between kernel modules and user space.

Since free_pgtables() is called with ceiling == 0, free_pgd_range() (and
subsequently called functions) also frees the page table
shared between user space and kernel modules (which is normally handled
by the ARM-specific pgd_free() function).

This patch changes the ceiling argument to mm->task_size for the
free_pgtables() and free_pgd_range() function calls. We cannot use
TASK_SIZE since this macro may not be a run-time constant on 64-bit
systems supporting compat applications.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Andrea Arcangeli <aarcange@redhat.com>
Cc: Russell King <linux@arm.linux.org.uk>
ARM: mm: Avoid the use of r8 register in cache flush all/level apis.

Currently cache_flush_by_level API is called from __v7_setup.
At this point, r8 contains the initial TTBR1 base address.
But r8 is not saved/restored in the API, resulting in corrupting
it. So when the corrupted r8 is used further during the
boot sequence, causes weird issues.

The issue becomes evident when the ARM workaround to use
"TTBR1 instead of reserved ASID during the context switch"
is applied.

Fixing this by optimising the code to avoid using r8.

Also there was a issue with optimise patch corrupting r3.
This has no functional impact, but resulted in unnessecary
cmp instructions.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
ARM: CORTEX-A15: Implement WA for erratum 763722.

  Conditions:
   1. Store streaming in progress with at least two fill buffers
      pending with full cache lines
   2. 5 non-cacheable/SO/Dev store requests in quick succession
   3. Eviction pending in the L1 waiting to go out
   4. Snoop request is waiting for the L1 to issue that eviction
   5. Snoop request is preventing forward progress on the L2 write-buffer

Implications:
   If all of the conditions are met, the part could deadlock, with
   the snoop holding up the write buffer, the write buffer being too
   full to accept the evict, and the lack of the evict holding up
   the snoop.

Workaround:
   In a single core system with no snoop traffic, this erratum
   cannot occur.  The full workaround for this is to disable
   store streaming. This can be done by setting ACTLR[28:27]
   (Write streaming no-allocate threshold) to b11 (disabled) and
   ACTLR[26:25] (Write streaming "no-L1-allocate" threshold) to
   b11 (disabled).

Signed-off-by: R Sricharan <r.sricharan@ti.com>
[Resolve Merge-conflicts]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

Change-Id: Ie26abcf4f5953bfd9287c587e560ad4667dc59cd
ARM: CORTEX-A15: Implement WA for erratum 762974.

  Conditions:
   1. Cache line request from an L1 Data Cache hits the L2 and
      needs to set the inclusion bit

   2. Instruction fetch request to the L2 hits prefetched data and
      needs to clear the prefetch bit

   3. Both requests are to the same tag bank and overlapping in time

  Implications:
      If the above conditions happen enough times (minimum >8 times
      for a given cache set) without any of the afected lines being
      loaded into the data cache or clean/invalidated through software
      maintenance, the part could deadlock. In our hundreds of billions
      of simulation cycles the event occurring even a single time is
      very rare, but in silicon running over a long period of time without
      any L2 cache clean/invalidation it would be possible to generate a
      deadlock case.

Workaround
      The full workaround for this is to disable hardware prefetch in the L2.
      Write 0x0000_0400 to the L2 Prefetch Control Register to accomplish this.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
[Resolve Merge-conflicts and rebase for p-linux-omap-3.4]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

Change-Id: I4a450412fcc80d195b2cd84be3886f19aca0e1e9
ARM: CORTEX-A15: Implement WA for errata 775619

    Conditions:
      1) All ways in a given L2 set have their lock or inclusion bit set
      2) An ACP write allocate request is made to that set OR another
         cache line fill needs to replace a way in that set

    Implications:
        In an A15 with one or two CPUs, there is an easy zero impact workaround
        that will prevent all the lock/inclusion bits in a set from ever being set
        at the same time (see workaround below), completely avoiding the data
        corruption or deadlock. In an A15 with three or four CPUs, there is no
        workaround. A system with no ACP write allocate traffic will avoid the data
        corruption scenario, but could see a deadlock.

    Workaround:
         This erratum can be completely avoided for an A15 containing only one or two
         CPUs. The Force in-order requests to same set/way
	 Register should be set (ACTLR[23] set to 1) in each CPU. This bit will prevent
         that CPU from having more than two cache line fills outstanding at a given time to the
         same set. This will completely prevent the L2 from ever seeing all 16 ways in a
         set with their inclusion or lock.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
[Resolve merge-conflict and rebase to p-linux-omap-3.4]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

Change-Id: Iba725f7d06b31c7313cfb899103675dcc9b33362
ARM: CORTEX-A15: Implement WA for errata 773022.

This patch adds the workaround to disable Loop Buffer.
The WA is to set ACTLR[1] bit to 0x1.

Signed-off-by: R Sricharan <r.sricharan@ti.com>
[Resolve merge conflicts and rebase to p-linux-omap-3.4]
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>

Change-Id: If448484290d2e21613dd3573a3a5054f690bff9c
ARM: CORTEX-A15: Sync omap2plus_defconfig with omap2plus_temp_defconfig

Enable patches in omap2plus_temp_defconfig
71ffdbc ARM: CORTEX-A15: Implement WA for errata 773022.
bcd1013 ARM: CORTEX-A15: Implement WA for errata 775619
3af8a1b ARM: CORTEX-A15: Implement WA for erratum 762974.
4002337 ARM: CORTEX-A15: Implement WA for erratum 763722

Change-Id: Id680cd1c95f57efa8e19ff820525bd7752c5ba5c
Signed-off-by: Praneeth Bajjuri <praneeth@ti.com>
misc: emif: use default custom config parameter.

In-case of low power mode selected and custom parameters
are not configured, then use default configuration.

Change-Id: I414229c692d30c2dae8bfca1fb3ef5fbfeef80e9
Signed-off-by: Ambresh K <ambresh@ti.com>
misc: emif: setup LP settings on freq update

Program the power management shadow register on freq update
Else the concept of threshold frequencies dont really matter
as the system always uses the performance mode timing for LP
which is programmed in at init time.

Change-Id: I22aa79e9c784712ecaacb7d28668b03ffd286626
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Ambresh K <ambresh@ti.com>
misc: emif: use shadow register for LP mode timing update

power management shadow register should be used to update
LP mode timing.

Change-Id: Ia4325cf551913928e23c36d9f478d2d6e6d3a737
Signed-off-by: Nishanth Menon <nm@ti.com>
misc: emif: correct the lpmode timeout calculation

The driver tries to round up the specified timeout cycles to
the next power of 2 value. But this is done wrongly.
Correcting this here.

Change-Id: I3d39fd6729561395e5be027efaf190eb2578ca23
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
misc: emif: handle overflow for timing for LP mode

In case the custom timings provide values which overflow
the maximum possible field value, warn and use maximum
permissible value.

Change-Id: I3390bc3f9c587d67e539c02781615a844a6747ce
Signed-off-by: Nishanth Menon <nm@ti.com>
ARM: OMAP5: sevm: enable EMIF selfrefresh

Change-Id: Ic962fffe10b597ee38e7093c8c54ba620c8c956b
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Ambresh K <ambresh@ti.com>
ARM: OMAP54XX: CM2 module adapatations for ES2.0 data

Patch implements the following data changes between ES1 and ES2:
- CM_CORE.L4PER_CM_CORE registers are merged with CM_CORE.CORE_CM_CORE
registers in ES2.0
- CM_COREAON_BANDGAP_CLKCTRL register is removed from ES2.0
- CM_MIPIEXT_UNIPRO1_CLKCTRL register is removed from ES2.0

Change-Id: I4df9d475b7e0d57a63d7a61f5ad68b47323fea19
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
ARM: OMAP54XX: update prcm-54xx-debug.c to handle ES2.0 properly

Patch implements the following data changes between ES1 and ES2:
- Bandgap module is not present in ES2.0
- Unipro1 module is not present in ES2.0
- CD_L4_PER clockdomain belongs to PD_CORE in ES2.0
- CD_L4_SEC clockdomain belongs to PD_CORE in ES2.0

Change-Id: If5d15e324ba2f82173df50c205e1785f95f57b5f
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>
ARM: OMAP54XX: add needed include to powerdomains54xx_data.c file

Specified header file contains PWRDM_POWER_RET macros,
which is needed for powerdomains54xx_data.c

Change-Id: I705ba7a68cf324e13b28ab725f846f58776a8ad4
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>