OMAP3+: DVFS: ensure proper volt config if curr_volt==new_volt

At times when current_volt is same as new voltage, voltdm_scale is not
invoked. Since, vp_err_gain update and voltdm->curr_volt update is done
as part of vc_prescale and post_scale invoked as part of scale call,
these are left configured to old OPP values even if we are moving
to a new OPP.

Update these when we detect voltdm_scale is not being invoked, but
new OPP Vnom is detected.

Change-Id: Ic45d5a51edb4e5fe526529c6040cd014907b560e
Reported-by: Honda Kenji <x0092217@ti.com>
Reported-by: Maki Tanaka <m-tanaka1@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Merge branch 'android-omap-tuna' of github.com:drod2169/KernelSanders-OMAP into android-omap-tuna
Merge branch 'android-omap-tuna' of github.com:drod2169/KernelSanders-OMAP into android-omap-tuna
Merge branch 'android-omap-tuna' of github.com:drod2169/KernelSanders-OMAP into android-omap-tuna
Linux 3.0.29 update

Conflicts:

	arch/arm/configs/tuna_defconfig
misc: modem_if: modemcontrol: add cp_dump pin level when cp crash

1. Add cp_dump_pin input gpio level when phone_active_pin goes low
	- if cp_dump_pin is high, it means cp sw crash
	- if cp_dump_pin is low, it's wrong detecting for phone_active_pin
	- requested by CP

Bug: 6281406
Change-Id: Ib8d586f711a1a338086aca715f56f932d992fbf2
Signed-off-by: wonhee <wonhee48.seo@samsung.com>
OMAP4: SGX: Set DPLL PER m7x2 as source for SGX FCLK

SGX functional clock can be sourced from either CORE or PER
DPLLs and usually set to PER in the boot-loader for OMAP4.
If not set to PER, then by default gets sourced from CORE M7x2.

On OMAP4, OPP100/OPP50 freqs for SGX are 307.2/153.6 Mhz, which
can be directly derived from PER m7x2 without changing the
divider. Otherwise will be sourced from CORE m7x2 and when dvfs
layer request for 307.2/153.6Mhz will be getting  320/160Mhz.

Change-Id: Ifd3b9374f029adcdcf1bf04e570d188fea3737f3
Signed-off-by: Ambresh K <ambresh@ti.com>
Signed-off-by: Vinay Chaurasia <vinaych@ti.com>

Patch Set 1
OMAP4: DSS: Implement workaround for Errata ID:i733.

Description of Errata i733:
Due to wrong timings, all register accesses transitioning through the L4
interconnect toward DSS are not reliable.

Workaround:
DSS register access should be addressed through the L3 interconnect.

This change fixes errata by using L3 for access to DSS in dss_hwmod
instead of L4.

Silicon Versions Impacted:
OMAP4430 ES1.0, ES2.0, ES2.1, ES2.2, ES2.3
OMAP4460 ES1.0, ES1.1
OMAP4470 ES1.0

Change-Id: Ie087b861ee653a3beeacba74c3afe7b1a0490ed4
Co-author: Raghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: Mykhailo Denysiuk <x0172934@ti.com>

Patch Set 5
OMAP4: correct CPU Idle settings for exit latency and thresholds

------------------------------------------------------------------------------------
Cstates					exit_latency	thresholds
OMAP4430	CPUs	MPU	Core		us		us	SystemClock
------------------------------------------------------------------------------------
C1		WFI	ON	ON		4		4		ON
------------------------------------------------------------------------------------
C2		OFF	INA	INA		300		300		ON
------------------------------------------------------------------------------------
C3		OFF	CSWR	OSWR		5000		10000		OFF
------------------------------------------------------------------------------------
C4		OFF	OSWR	OSWR		5200		35000		OFF
------------------------------------------------------------------------------------

------------------------------------------------------------------------------------
Cstates					exit_latency	thresholds
OMAP4460	CPUs	MPU	Core		us		us	SystemClock
------------------------------------------------------------------------------------
C1		WFI	ON	ON		4		4		ON
------------------------------------------------------------------------------------
C2		OFF	INA	INA		300		1800		ON
------------------------------------------------------------------------------------
C3		OFF	CSWR	OSWR		4000		4000		OFF
------------------------------------------------------------------------------------
C4		OFF	OSWR	OSWR		4200		4200		OFF
------------------------------------------------------------------------------------

------------------------------------------------------------------------------------
Cstates					exit_latency	thresholds
OMAP4470	CPUs	MPU	Core		us		us	SystemClock
------------------------------------------------------------------------------------
C1		WFI	ON	ON		4		4		ON
------------------------------------------------------------------------------------
C2		OFF	INA	INA		500		1200		ON
------------------------------------------------------------------------------------
C3		OFF	CSWR	OSWR		5300		5300		OFF
------------------------------------------------------------------------------------
C4		OFF	OSWR	OSWR		5500		15000		OFF
------------------------------------------------------------------------------------

Change-Id: I6f9046db4273b10cecd7bf896c1a8488774e0d5b
Signed-off-by: Andrii Tseglytskyi <andrii.tseglytskyi@ti.com>

Patch Set 3