Add IC_MSG_LINE_INVALIDATE_* message types for I_LINE_INV
Preliminary target RWX permissions checking on loads and stores, quick and dirty RIGEL_CFG_NUM=2 Heartbeat.

The backing store now holds lists of target address intervals that
are readable, writable, and executable.  It checks all target read
and write accesses against these lists and throws an exception if
the access is disallowed.
FIXME should this checking be moved to a separate class?

These lists of intervals are populated by the ELF loader.  Executable
ELF sections are marked as executable, static data sections are marked
as read-only or read-write according to the ELF section header flags,
and the heap and stack areas are marked read-write.  We mark
3*ISSUE_WIDTH words past the end of each executable ELF section as
executable, to prevent spurious exceptions when we speculatively
fetch past the end of the program before we resolve the branch.

We detect the end of the static data sections and the beginning of
the heap the same way target code does; we have a special symbol
_end that the linker script places there for us, and we find its
address by iterating over the ELF symbol table.

NOTE: Instead of read_word() and write_word(), backing_store now
exposes read_instr_word(), read_data_word(), read_host_word(),
and write_word().  read_host_word() is used for reads that may be
unsafe for the target to do, but we want to do for simulator-specific
purposes (like dumping memory, or printing an address for the user
in interactive mode).  The other three are all checked against the
valid intervals.  If any of the 3 sets of intervals are empty,
any access of that type will succeed.

FIXME Split write_word() into write_data_word() and write_host_word()
so that we can do cheating writes for e.g. putting syscall results
back in memory once we have more restrictive permissions on stack
and heap.
header reorg for caches, relocate caches to caches_legacy
Merge branch 'dev' of /afs/crhc.illinois.edu/project/rigel/common/github/rigelproject-release/rigel-sim into dev
relocate older mshr code
relocate core instruction execution functionality to RigelISA static members for easier reuse
associated updateds to CF and CCF
rtm cg-coherence1 test pipe diff mismatch to file
regfile: remove unused float flags, fix naming with _s
added missing header
checkpoint commit: compiles, but bugs in synchronization codes
trivial passes
bugfix for CF: NOPed memory requests (prefetches, cache control) were not marked as completed
nor were they sent for service. Currently, mark NOPed memory requests as completed immediately
rigel-sim/test: patch a few test scripts to pipe diff output to files, not screen
pretty colorize test folder pass/fail messages
test: remove unused threads tests, patch up common.sh,Makefiles
test folder script update: trivial/mt_prog pipe diff output to file
stallable memory requests via ports for CF
multithreaded mode in CoreFunctional stalls and serializes threads on multicycle memory requests
(who cares about perf, this mode is not for accurate perf modelling)
commit missing rigel_isa file (functional instruction execution)
cluster_cache_functional allows zero, fixed latencies
cache code readability cleanup
checkpoint commit
rename ClusterSimple ClusterFunctional
port name changes
initial portmanager header (incomplete)
checkpoint commit: ports named, registered at construction