board-endeavoru-sdhci: disable .ocr_mask
Asynchronous I/O latency to a solid-state disk greatly increased

between the 2.6.32 and 3.0 kernels. By removing the plug from
do_io_submit(), we observed a 34% improvement in the I/O latency.

Unfortunately, at this level, we don't know if the request is to
a rotating disk or not.

Signed-off-by: Dave Kleikamp <dave.kleikamp@oracle.com>
Cc: linux-aio@kvack.org
Cc: Chris Mason <chris.mason@oracle.com>
Cc: Jens Axboe <axboe@kernel.dk>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Jeff Moyer <jmoyer@redhat.com>
usb: core: hub.c: implement fixes for endeavoru, fix warnings
wakeups-t3: prevent useless baseband wakeups
ARM: tegra: clocks: Frequency stats for SCLK/CBUS

This adds a frequency histogram of the frequencies that SCLK
and CBUS clocks go to over time. Stats are presented in the
debugfs at /d/clock_stats/cbus and /d/clock_stats/sclk only if
debugfs is enabled in config

Change-Id: Icae83329612958d8ed4318b2e10c487683d9d734
Signed-off-by: Dan Willemsen <dwillemsen@nvidia.com>
Reviewed-on: http://git-master/r/118380
Reviewed-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Cherry <tcherry@nvidia.com>
video: tegra: nvmap: fix input check in mmap ioctl

nvmap_map_into_caller_ptr takes a memory handle from usermode
and adds a memory mapping for the handle. However, the handle
is not checked for being allocated. An unallocated handle
would cause a kernel panic later on from a NULL dereference.

Change-Id: I73987b097a0c843b913660445e8bd1b4755dac61
Signed-off-by: Tuomas Tynkkynen <ttynkkynen@nvidia.com>
Reviewed-on: http://git-master/r/119689
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
PM: Need to wake_up_all when suspend fail

In rpm_suspend, when suspend fail,
before going to reschedule another autosuspend,
wake_up_all is required to avoid remote wakeup
issues.

Bug 1026169
Bug 1027598
Bug 1032565

Change-Id: Ieaf9282dae59b2cb343bf01aa2ba837a8cdc39c7
Signed-off-by: BH Hsieh <bhsieh@nvidia.com>
Reviewed-on: http://git-master/r/122978
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Neil Patel <neilp@nvidia.com>
Tested-by: Neil Patel <neilp@nvidia.com>
Tested-by: Steve Lin <stlin@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Steve Lin <stlin@nvidia.com>
arm: tegra: Set Core to 0.95V in LP1

When the device prepares for LP1, the Core voltage is set to the
highest value(1.2V for Enterprise and Kai, and 1.3V for AP37 and
Cardhu). This is to set for some of the driver suspend along the
sequence need a higher emc frequency and thus a higher Core voltage.

Since the sequence of drivers suspend depends on the sequence of
their registration in the table, which in turn is platform-dependent,
there is no right place in the LP1 entry path where the Core voltage
can be set to a lower voltage. Hence, the Core voltage remains high
in LP1 resulting in higher power.

Thus, the only safe location where the Core voltage can be lowered is
once all the drivers are suspended and the DRAM is set in self-refresh,
at the final point just before the system is suspended in the IRAM code.
This location at the assembly code ensures that no other module will be
running and thus that nothing will require a higher core voltage. The Core
is set to the lowest possible value since nothing requires it. It is then
restored to the highest voltage as soon as the LP1 resume code is started
so that all drivers are resumed safely.

At the execution point in IRAM during LP1 suspend path, even the I2C clocks
are gated. They must be reset first and then the I2C transaction is performed.
An I2C transaction involves 4 bytes of data, to send the slave address,
the Core voltage register address and 2 bytes of data which has the value
to set the voltage(the second byte is not required for this transaction).
Once these registers are set, the I2C transaction is performed by setting
the I2C transaction register to 0xA02. After sending the I2C transaction,
we wait for about 250us to check the status of the transaction and if not
updated, wait for more time to check again. If after 2ms and the transaction
fails to register, the transaction is aborted and the device is allowed
to enter at high voltage. Since the failure rate of I2C transaction is very
low at this point in execution where there will be no conflicts in the bus,
it is okay to have Core high for some of the LP1 cycles.

However, it is unacceptable for the I2C transaction to fail on the way
from LP1 resume since the device cannot come up with a lower Core
voltage. In this case, the transaction is retried again and again till
it is successful. There is no way but to keep trying as the device
would fail to resume with Core at 0.95V.

Each platform(or each PMU) has different values for the I2C transaction
ie. slave address, Core voltage register and the value to set the
voltage. For the device in IRAM, it cannot access anything in SDRAM
memory, these values needs to be pushed to IRAM memory before the device
starts execution in IRAM. This is done during initialization of suspend
code when it picks values from the board files and copies it to IRAM
part of code, before the whole memory is copied to IRAM.

This new feature is controlled by a KConfig variable TEGRA_LP1_950 which
should be enabled once the board file of the device is updated with the
right values. The device hangs when it does not have the right values for
the I2C transaction.

With this change in Core, LP1 power is reduced by 12mW in Enterprise,
20mW in AP37 and about 24mW in Kai.

Bug 1035684

Change-Id: I4318c66fd70ab227ef0786d6a13286e020e4541d
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
Reviewed-on: http://git-master/r/124135
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
arm: tegra: Board files settings for LP1 0.95V CoreV

Set the register values for each of the board files to
keep the Core voltage to 0.95V in LP1.

This change is only for those platforms where LP1 is supported.
Enterprise and Kai are the main platforms for this change. There
is no support for Cardhu for LP1 and so is left blank and the
feature will be skipped for Cardhu platforms, except for AP37.
AP37 with a PM269 board needs this change and so Cardhu board
file is updated with the values specific to AP37.

This change is part of the feature to set VCore to 0.95V
Refer to http://git-master/r/124135 for more details
Bug 1035684

Change-Id: I6d1d984b0e7968b441cebbc37705c25647a4a85a
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
Reviewed-on: http://git-master/r/124136
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
arm: tegra: Enable LP1_950 config

Enable LP1 Core voltage settings to 950mV

The feature is added in the below change.
Refer to http://git-master/r/#change,124135 for more details.
Bug 1035684

Change-Id: I922efff17797f4666fd6ed069a8523c164445842
Signed-off-by: Karthik Ramakrishnan <karthikr@nvidia.com>
Reviewed-on: http://git-master/r/124137
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Dan Willemsen <dwillemsen@nvidia.com>
board-endeavoru-power: settings for LP1 0.95V CoreV
ARM: tegra: cardhu: report height/width for cardhu

For accurate Dots-per-inch computation we need to report height/width for
the cardhu panel.

Bug 1003707.

Change-Id: I9a3413d06d97bed532ffc501000ca9bc2360e842
Signed-off-by: Rakesh Iyer <riyer@nvidia.com>
Reviewed-on: http://git-master/r/118777
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Jon Mayo <jmayo@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
cpufreq: protect cpufreq_stats_free_table with spinlock

Prevents crash on cpufreq_stat_notifier_trans when cpufreq_stats_table
has been freed due to a core being hotplugged out.

Bug 948348

Change-Id: I2640a9a23c9a79cad8c76bfefd243a07162d2004
Signed-off-by: Peter Boonstoppel <pboonstoppel@nvidia.com>
(cherry picked from commit 03070a4b0b8eb74825c99c6bbfb108ddb36a041c)
Reviewed-on: http://git-master/r/114248
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
arm: tegra: cpu: changing cpu min. freq to 51MHz

Changing the CPU min. frequency to 51MHz. This helps
in bringing down the core power to 46mW.

Bug 1005275

Change-Id: I61daa59866be7baf8ebb741000904422cb095e85
Signed-off-by: Prem Sasidharan <psasidharan@nvidia.com>
(cherry picked from commit afbb34d5871b69df328d5aae37f69f25a8946514)
Reviewed-on: http://git-master/r/115452
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Wen Yi <wyi@nvidia.com>
Tested-by: Wen Yi <wyi@nvidia.com>
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
power: max17048: fix power polling at resume

The state of charing is not correct because of the 1 sec delay.
Remove the delay to fix the issue.

Bug 1016683

Change-Id: I389970e32d34578bb1ec1f2019d78145f250a673
Signed-off-by: Chandler Zhang <chazhang@nvidia.com>
Reviewed-on: http://git-master/r/115632
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bharat Nihalani <bnihalani@nvidia.com>
ARM: tegra: clock: Add missed Tegra3 PERIPH_ON_APB attributes

Change-Id: I12be16dbc2614224ba852216a645d0f84c795334
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/115929
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Scott Peterson <speterson@nvidia.com>
ARM: tegra: thermal: Call pm register only once

Fixed bug where pm register was being called multiple times.

Change-Id: I32f7b10547275e0a9bdad1073f9842589180c0f8
Signed-off-by: Joshua Primero <jprimero@nvidia.com>
Reviewed-on: http://git-master/r/116203
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Bitan Biswas <bbiswas@nvidia.com>
ARM: Tegra3: clocks: optional se.cbus

Made se.cbus optional so that se clock can be derived
from other clocks and not just from the clocks which drive cbus.

Added config option for the same.

Bug 978870

Change-Id: I7b5bf405efb58bbb53143f52d2bfe0ebcf6b8322
Signed-off-by: Mohit Kataria <mkataria@nvidia.com>
Reviewed-on: http://git-master/r/110827
(cherry picked from commit 35e9017b79a3a4b4e0b4098cd2e63ad24018d3de)
Reviewed-on: http://git-master/r/106397
Reviewed-by: Simone Willett <swillett@nvidia.com>
Tested-by: Simone Willett <swillett@nvidia.com>
gpio: tegra: disable non-wake source interrupts

Gpio interrupts for non-wake sources are disabled before suspend

bug 904746

Change-Id: I21f3e5798055cbae7324b1571291eab4538e256f
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/115654
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
ARM: tegra: wake source interrupts enabled

Tegra wake source interrupts are only enabled before suspend

bug 904746

Change-Id: Ie9722199b4541f2bac77e47d0c8c7e65d5d8b54d
Signed-off-by: Bitan Biswas <bbiswas@nvidia.com>
Reviewed-on: http://git-master/r/115655
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Laxman Dewangan <ldewangan@nvidia.com>