ARM: OMAP2+: INTC: fix suspend abort, set IRQCHIP_SKIP_SET_WAKE

Without an ->irq_set_wake() method in an irq_chip, calls to
enable_irq_wake() will fail.  This also causes these interrupts to not
be able to abort suspend (via check_wakeup_irqs() in late suspend.)

Currently, we don't implement ->irq_set_wake() for INTC interrupts
because they default to be wakeup enabled by setting the GRPSEL bits
in PM init.  Even though there is no ->irq_set_wake(), we want
enable_irq_wake() to succeed so these interrupts can abort suspend
when necessary.

To fix, set IRQCHIP_SKIP_SET_WAKE flag for all the INTC
interrupts which avoids trying to check irq_chip->irq_set_wake()
and failing when it doesn't exist.

Longer term, we need to implement ->irq_set_wake() for the INTC
which can manage the appropriate GRPSEL bits.

Signed-off-by: NeilBrown <neilb@suse.de>
[khilman@ti.com: rework changelog]
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
ARM: OMAP3: PM: fix shared PRCM interrupts: leave disabled at boot

By default, request_irq() will auto-enable the requested IRQ.

For PRCM interrupts, we may want to avoid that until the PM core code
is fully ready to handle the interrupts.  This is particularily true
for IO pad interrupts on OMAP3, which are shared between the hwmod
core and the PRM core.

In order to avoid PRCM IO-chain interrupts until the PM core is ready
to handle them, ready, set the IRQ_NOAUTOEN flag for the PRCM IO-chain
interrupt,  which means it will remain disabled after request_irq().

Then, explicitly enable the PRCM interrupts after the request_irq() in
the PM core (but not in the hwmod core.)

Special thanks to Tero Kristo for suggesting to isolate the fix to
only the IO-chain interrupt on OMAP3 instead of all PRCM interrupts.

Cc: Tero Kristo <t-kristo@ti.com>
Acked-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
arm: omap3: am35x: Don't mark missing features as present

The Chip Identification register on the am35x family of SoCs
has bits 12, 7:5, and 3:2 marked as reserved and are read as
zeroes.  Unfortunately, on other omap SoCs, a 0 bit means a
feature is "Full Use" so the OMAP3_CHECK_FEATURE() macro
called by omap3_check_features() will incorrectly interpret
those zeroes to mean that a feature is present even though it
isn't.  To fix that, the feature bits that are incorrectly
set (namely, OMAP3_HAS_IVA and OMAP3_HAS_ISP) need to be
cleared after all of the calls to OMAP3_CHECK_FEATURE() in
omap3_check_features() are made.

Signed-off-by: Mark A. Greer <mgreer@animalcreek.com>
[khilman@ti.com: use soc_is_am35xx() instead of cpu_is_am35xx()]
Signed-off-by: Kevin Hilman <khilman@ti.com>
ARM i.MX5: fix gpt peripheral clock path

- The gpt peripheral clk parent is per_root, not ipg
- The register for selectin per_lp_apm and per_root is
  MXC_CCM_CBCMR, not MXC_CCM_CBCDR

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM: i.MX: change timer clock from ipg to perclk

Contrary to the ipg clock the perclk rate is not changed or
gated in low power mode, so we choose perclk for gpt.

With the port to the common clock framework as a side effect
the timer used the rate returned from the peripheral clock
but the hardware was still programmed to use the ipg clock,
so this patch only changes the hardware to really use the
clock it already assumed.

Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX: remove now unnecessary argument from mxc_timer_init

As the timer code now does a clk_get to get its clock we don't
need the struct clk argument anymore.
This also changes the alternative EPIT timer to do a clk_get.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM: imx6q: prepare and enable init on clks directly instead of clk_get first

This also removes the usboh3 clk from the initially turned on
clocks which leaked in from an internal development tree.

Signed-off-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM: OMAP3: clock data: cleanup AM3[35]x SoC detection

Use the more generic SoC family soc_is_am35xx() instead of the specific
cpu_is_omap3517() (which is being removed.)

Acked-by: Vaibhav Hiremath <hvaibhav@ti.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
Tested-by: Mark A. Greer <mgreer@animalcreek.com>
Cc: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
ARM: OMAP: SoC detection: remove unused cpu_is macros

Remove multiple unused cpu_is_omap35xx macros.

In particular, the cpu_is_omap35* macros for 3503, 3515, 3525 are removed
because they are using omap_has_* feature checks and we want to
remove specific feature detection from SoC family detection.

There are no longer any cpu_is_* checks that depend on specific IP
detection.

Acked-by: Vaibhav Hiremath <hvaibhav@ti.com>
Tested-by: Vaibhav Hiremath <hvaibhav@ti.com>
Tested-by: Mark A. Greer <mgreer@animalcreek.com>
Signed-off-by: Kevin Hilman <khilman@ti.com>
ARM: mx31_3ds: Fix build due to missing IMX_HAVE_PLATFORM_IMX_SSI

commit 5fb86e5 (ARM: mx31_3ds: Add sound support) missed to select IMX_HAVE_PLATFORM_IMX_SSI,
which causes the following build error when only mx31_3ds is selected:

arch/arm/mach-imx/built-in.o: In function `mx31_3ds_init':
mach-mx31_3ds.c:(.init.text+0x15dc): undefined reference to `imx_add_imx_ssi'
mach-mx31_3ds.c:(.init.text+0x16b8): undefined reference to `imx31_imx_ssi_data'

Select IMX_HAVE_PLATFORM_IMX_SSI to fix it.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM: imx: only specify i2c device type once

The first argument of I2C_BOARD_INFO is used to assign .type, so drop
second assignment.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM: imx: only call l2x0_init if it's available

This fixes a build failure with CONFIG_CACHE_L2X0=n:

	arch/arm/mach-imx/built-in.o: In function `imx3_init_l2x0':
	imx53-dt.c:(.init.text+0x190): undefined reference to `l2x0_init'
	make[2]: *** [.tmp_vmlinux1] Error 1
	make[1]: *** [sub-make] Error 2
	make: *** [all] Error 2

When the l2 cache isn't enabled the quirk introduced in
9524705 (MX35: Fix bogus L2 cache settings) doesn't need to be done
either.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Merge branch 'for_3.5/fixes/pm' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into fixes
Merge branch 'for_3.5/cleanup/am3xxx-cpu-is-leftovers' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-omap-pm into fixes
ARM: OMAP: Fix lis3lv02d accelerometer to use gpio_to_irq

Commit 3b511201 (ARM: OMAP: rx51: Platform support for lis3lv02d accelerometer)
added support for lis3lv02d accelerometer.

The patch was still using OMAP_GPIO_IRQ which no longer exists.

Fix it by using gpio_to_irq().

Signed-off-by: Tony Lindgren <tony@atomide.com>
ARM i.MX pllv2: use standard register set unconditionally

The i.MX5 PLL has two different register sets for setting the
rate. One is used for the standard case and and is used for
DVFS. Which one of them is used depends on a hardware input
of the PLL. Current implementation reads back from the hardware
which setting is used. This is bogus: If we ever want to implement
DVFS we have to program both register sets and not only the one
which happens to be used at the moment. For now, just use the
standard register set uncondionally.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX pllv2: make round_rate accurate

in round_rate we made the assumption that we can set arbitrary
frequencies and thus returned the input rate. This is not correct,
for certain frequencies after setting a frequency with set_rate,
recalc_rate will return different values. To fix this, introduce
set_rate/recalc_rate functions which work on variables instead
of registers directly. This way we can call these in round_rate
to get the exact rate which we would get if we call set_rate
with this value.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
ARM i.MX53: Fix PLL4 base address

MX53_DPLL4_BASE accidently returned the base address of PLL3.
Fix this.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Cc: stable@vger.kernel.org
iio: documentation: Add out_altvoltage and friends

Continuous frequency/clock generating devices, such as DDSs or PLLs
should use out_altvoltage.

Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
staging:iio: remove num_interrupt_lines from documentation

Commit 5aa9618896e0ba49 ("staging:iio: remove broken support for
multiple event interfaces.") removed the num_interrupt_lines field from
struct iio_info but the documentation was never updated.

Signed-off-by: Johan Hovold <jhovold@gmail.com>
Acked-by: Jonathan Cameron <jic23@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>