theory Interrupt_R

lemma performIRQControl_corres:
  "irq_control_inv_relation i i' \<Longrightarrow>
   corres (dc \<oplus> dc) (einvs and irq_control_inv_valid i)
             (invs' and irq_control_inv_valid' i')
     (invoke_irq_control i)
     (performIRQControl i')" apply (cases i, simp_all add: performIRQControl_def) apply (rule corres_guard_imp) apply (rule corres_split_nor[OF setIRQState_corres]) apply (simp add: irq_state_relation_def) apply (rule cteInsert_simple_corres) apply (wp | simp add: IRQHandler_valid IRQHandler_valid')+ apply (clarsimp simp: invs_def valid_state_def valid_pspace_def
                          cte_wp_at_caps_of_state is_simple_cap_def
                          is_cap_simps safe_parent_for_def) apply (clarsimp simp: invs'_def valid_state'_def valid_pspace'_def
                         IRQHandler_valid  IRQHandler_valid' is_simple_cap'_def
                         isCap_simps) apply (clarsimp simp: safe_parent_for'_def cte_wp_at_ctes_of) apply (case_tac ctea) apply (clarsimp simp: isCap_simps sameRegionAs_def3) apply (auto dest: valid_irq_handlers_ctes_ofD)[1] by (clarsimp simp: arch_performIRQControl_corres)

(* Proof state trace *)
proof (prove)
goal (1 subgoal):
 1. irq_control_inv_relation i i' \<Longrightarrow> corres (dc \<oplus> dc) (einvs and irq_control_inv_valid i) (invs' and irq_control_inv_valid' i') (invoke_irq_control i) (global.performIRQControl i') proof (prove)
goal (2 subgoals):
 1. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> corres dc (einvs and (cte_wp_at ((=) cap.NullCap) x12 and cte_wp_at ((=) cap.IRQControlCap) x13 and ex_cte_cap_wp_to is_cnode_cap x12 and real_cte_at x12 and (\<lambda>y. x11 \<le> maxIRQ))) (invs' and (cte_wp_at' (\<lambda>cte. cteCap cte = capability.NullCap) (cte_map x12) and cte_wp_at' (\<lambda>cte. cteCap cte = capability.IRQControlCap) (cte_map x13) and ex_cte_cap_wp_to' (\<lambda>_. True) (cte_map x12) and real_cte_at' (cte_map x12) and Not \<circ> irq_issued' x11 and (\<lambda>y. x11 \<le> maxIRQ))) (do y <- set_irq_state irq_state.IRQSignal x11;
cap_insert (cap.IRQHandlerCap x11) x13 x12
od) (do y <- setIRQState irqstate.IRQSignal x11;
cteInsert (capability.IRQHandlerCap x11) (cte_map x13) (cte_map x12)
od)
 2. \<And>x2. \<lbrakk>\<exists>ivk'. i' = irqcontrol_invocation.ArchIRQControl ivk' \<and> arch_irq_control_inv_relation x2 ivk'; i = irq_control_invocation.ArchIRQControl x2\<rbrakk> \<Longrightarrow> corres (dc \<oplus> dc) (einvs and arch_irq_control_inv_valid x2) (invs' and irq_control_inv_valid' i') (arch_invoke_irq_control x2) (case i' of irqcontrol_invocation.ArchIRQControl invok \<Rightarrow> Arch.performIRQControl invok | Invocations_H.irqcontrol_invocation.IssueIRQHandler irq handlerSlot controlSlot \<Rightarrow> withoutPreemption $ do setIRQState irqstate.IRQSignal irq;
cteInsert (capability.IRQHandlerCap irq) controlSlot handlerSlot
od) proof (prove)
goal (4 subgoals):
 1. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> corres dc (?Q2 x11 x12 x13) (?Q'2 x11 x12 x13) (do y <- set_irq_state irq_state.IRQSignal x11;
cap_insert (cap.IRQHandlerCap x11) x13 x12
od) (do y <- setIRQState irqstate.IRQSignal x11;
cteInsert (capability.IRQHandlerCap x11) (cte_map x13) (cte_map x12)
od)
 2. \<And>x11 x12 x13 s. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13; (einvs and (cte_wp_at ((=) cap.NullCap) x12 and cte_wp_at ((=) cap.IRQControlCap) x13 and ex_cte_cap_wp_to is_cnode_cap x12 and real_cte_at x12 and (\<lambda>y. x11 \<le> maxIRQ))) s\<rbrakk> \<Longrightarrow> ?Q2 x11 x12 x13 s
 3. \<And>x11 x12 x13 s. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13; (invs' and (cte_wp_at' (\<lambda>cte. cteCap cte = capability.NullCap) (cte_map x12) and cte_wp_at' (\<lambda>cte. cteCap cte = capability.IRQControlCap) (cte_map x13) and ex_cte_cap_wp_to' (\<lambda>_. True) (cte_map x12) and real_cte_at' (cte_map x12) and Not \<circ> irq_issued' x11 and (\<lambda>y. x11 \<le> maxIRQ))) s\<rbrakk> \<Longrightarrow> ?Q'2 x11 x12 x13 s
 4. \<And>x2. \<lbrakk>\<exists>ivk'. i' = irqcontrol_invocation.ArchIRQControl ivk' \<and> arch_irq_control_inv_relation x2 ivk'; i = irq_control_invocation.ArchIRQControl x2\<rbrakk> \<Longrightarrow> corres (dc \<oplus> dc) (einvs and arch_irq_control_inv_valid x2) (invs' and irq_control_inv_valid' i') (arch_invoke_irq_control x2) (case i' of irqcontrol_invocation.ArchIRQControl invok \<Rightarrow> Arch.performIRQControl invok | Invocations_H.irqcontrol_invocation.IssueIRQHandler irq handlerSlot controlSlot \<Rightarrow> withoutPreemption $ do setIRQState irqstate.IRQSignal irq;
cteInsert (capability.IRQHandlerCap irq) controlSlot handlerSlot
od) proof (prove)
goal (7 subgoals):
 1. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> irq_state_relation irq_state.IRQSignal irqstate.IRQSignal
 2. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> corres dc (?R6 x11 x12 x13) (?R'6 x11 x12 x13) (cap_insert (cap.IRQHandlerCap x11) x13 x12) (cteInsert (capability.IRQHandlerCap x11) (cte_map x13) (cte_map x12))
 3. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> \<lbrace>?Q6 x11 x12 x13\<rbrace> set_irq_state irq_state.IRQSignal x11 \<lbrace>\<lambda>x. ?R6 x11 x12 x13\<rbrace>
 4. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> \<lbrace>?Q'6 x11 x12 x13\<rbrace> setIRQState irqstate.IRQSignal x11 \<lbrace>\<lambda>x. ?R'6 x11 x12 x13\<rbrace>
 5. \<And>x11 x12 x13 s. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13; (einvs and (cte_wp_at ((=) cap.NullCap) x12 and cte_wp_at ((=) cap.IRQControlCap) x13 and ex_cte_cap_wp_to is_cnode_cap x12 and real_cte_at x12 and (\<lambda>y. x11 \<le> maxIRQ))) s\<rbrakk> \<Longrightarrow> ((\<lambda>_. True) and ?Q6 x11 x12 x13) s
 6. \<And>x11 x12 x13 s. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13; (invs' and (cte_wp_at' (\<lambda>cte. cteCap cte = capability.NullCap) (cte_map x12) and cte_wp_at' (\<lambda>cte. cteCap cte = capability.IRQControlCap) (cte_map x13) and ex_cte_cap_wp_to' (\<lambda>_. True) (cte_map x12) and real_cte_at' (cte_map x12) and Not \<circ> irq_issued' x11 and (\<lambda>y. x11 \<le> maxIRQ))) s\<rbrakk> \<Longrightarrow> ((\<lambda>_. True) and ?Q'6 x11 x12 x13) s
 7. \<And>x2. \<lbrakk>\<exists>ivk'. i' = irqcontrol_invocation.ArchIRQControl ivk' \<and> arch_irq_control_inv_relation x2 ivk'; i = irq_control_invocation.ArchIRQControl x2\<rbrakk> \<Longrightarrow> corres (dc \<oplus> dc) (einvs and arch_irq_control_inv_valid x2) (invs' and irq_control_inv_valid' i') (arch_invoke_irq_control x2) (case i' of irqcontrol_invocation.ArchIRQControl invok \<Rightarrow> Arch.performIRQControl invok | Invocations_H.irqcontrol_invocation.IssueIRQHandler irq handlerSlot controlSlot \<Rightarrow> withoutPreemption $ do setIRQState irqstate.IRQSignal irq;
cteInsert (capability.IRQHandlerCap irq) controlSlot handlerSlot
od) proof (prove)
goal (6 subgoals):
 1. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> corres dc (?R6 x11 x12 x13) (?R'6 x11 x12 x13) (cap_insert (cap.IRQHandlerCap x11) x13 x12) (cteInsert (capability.IRQHandlerCap x11) (cte_map x13) (cte_map x12))
 2. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> \<lbrace>?Q6 x11 x12 x13\<rbrace> set_irq_state irq_state.IRQSignal x11 \<lbrace>\<lambda>x. ?R6 x11 x12 x13\<rbrace>
 3. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> \<lbrace>?Q'6 x11 x12 x13\<rbrace> setIRQState irqstate.IRQSignal x11 \<lbrace>\<lambda>x. ?R'6 x11 x12 x13\<rbrace>
 4. \<And>x11 x12 x13 s. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13; (einvs and (cte_wp_at ((=) cap.NullCap) x12 and cte_wp_at ((=) cap.IRQControlCap) x13 and ex_cte_cap_wp_to is_cnode_cap x12 and real_cte_at x12 and (\<lambda>y. x11 \<le> maxIRQ))) s\<rbrakk> \<Longrightarrow> ((\<lambda>_. True) and ?Q6 x11 x12 x13) s
 5. \<And>x11 x12 x13 s. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13; (invs' and (cte_wp_at' (\<lambda>cte. cteCap cte = capability.NullCap) (cte_map x12) and cte_wp_at' (\<lambda>cte. cteCap cte = capability.IRQControlCap) (cte_map x13) and ex_cte_cap_wp_to' (\<lambda>_. True) (cte_map x12) and real_cte_at' (cte_map x12) and Not \<circ> irq_issued' x11 and (\<lambda>y. x11 \<le> maxIRQ))) s\<rbrakk> \<Longrightarrow> ((\<lambda>_. True) and ?Q'6 x11 x12 x13) s
 6. \<And>x2. \<lbrakk>\<exists>ivk'. i' = irqcontrol_invocation.ArchIRQControl ivk' \<and> arch_irq_control_inv_relation x2 ivk'; i = irq_control_invocation.ArchIRQControl x2\<rbrakk> \<Longrightarrow> corres (dc \<oplus> dc) (einvs and arch_irq_control_inv_valid x2) (invs' and irq_control_inv_valid' i') (arch_invoke_irq_control x2) (case i' of irqcontrol_invocation.ArchIRQControl invok \<Rightarrow> Arch.performIRQControl invok | Invocations_H.irqcontrol_invocation.IssueIRQHandler irq handlerSlot controlSlot \<Rightarrow> withoutPreemption $ do setIRQState irqstate.IRQSignal irq;
cteInsert (capability.IRQHandlerCap irq) controlSlot handlerSlot
od) proof (prove)
goal (8 subgoals):
 1. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> cap_relation (cap.IRQHandlerCap x11) (capability.IRQHandlerCap x11)
 2. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> cte_map x13 = cte_map x13
 3. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> cte_map x12 = cte_map x12
 4. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> \<lbrace>?Q6 x11 x12 x13\<rbrace> set_irq_state irq_state.IRQSignal x11 \<lbrace>\<lambda>x. valid_objs and pspace_distinct and pspace_aligned and valid_mdb and valid_list and K (x13 \<noteq> x12) and cte_wp_at (\<lambda>c. c = cap.NullCap) x12 and K (is_simple_cap (cap.IRQHandlerCap x11)) and (\<lambda>s. cte_wp_at (safe_parent_for (cdt s) x13 (cap.IRQHandlerCap x11)) x13 s)\<rbrace>
 5. \<And>x11 x12 x13. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13\<rbrakk> \<Longrightarrow> \<lbrace>?Q'6 x11 x12 x13\<rbrace> setIRQState irqstate.IRQSignal x11 \<lbrace>\<lambda>x. pspace_distinct' and pspace_aligned' and valid_mdb' and valid_cap' (capability.IRQHandlerCap x11) and K (is_simple_cap' (capability.IRQHandlerCap x11)) and cte_wp_at' (\<lambda>c. cteCap c = capability.NullCap) (cte_map x12) and (\<lambda>s. safe_parent_for' (ctes_of s) (cte_map x13) (capability.IRQHandlerCap x11))\<rbrace>
 6. \<And>x11 x12 x13 s. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13; (einvs and (cte_wp_at ((=) cap.NullCap) x12 and cte_wp_at ((=) cap.IRQControlCap) x13 and ex_cte_cap_wp_to is_cnode_cap x12 and real_cte_at x12 and (\<lambda>y. x11 \<le> maxIRQ))) s\<rbrakk> \<Longrightarrow> ((\<lambda>_. True) and ?Q6 x11 x12 x13) s
 7. \<And>x11 x12 x13 s. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13; (invs' and (cte_wp_at' (\<lambda>cte. cteCap cte = capability.NullCap) (cte_map x12) and cte_wp_at' (\<lambda>cte. cteCap cte = capability.IRQControlCap) (cte_map x13) and ex_cte_cap_wp_to' (\<lambda>_. True) (cte_map x12) and real_cte_at' (cte_map x12) and Not \<circ> irq_issued' x11 and (\<lambda>y. x11 \<le> maxIRQ))) s\<rbrakk> \<Longrightarrow> ((\<lambda>_. True) and ?Q'6 x11 x12 x13) s
 8. \<And>x2. \<lbrakk>\<exists>ivk'. i' = irqcontrol_invocation.ArchIRQControl ivk' \<and> arch_irq_control_inv_relation x2 ivk'; i = irq_control_invocation.ArchIRQControl x2\<rbrakk> \<Longrightarrow> corres (dc \<oplus> dc) (einvs and arch_irq_control_inv_valid x2) (invs' and irq_control_inv_valid' i') (arch_invoke_irq_control x2) (case i' of irqcontrol_invocation.ArchIRQControl invok \<Rightarrow> Arch.performIRQControl invok | Invocations_H.irqcontrol_invocation.IssueIRQHandler irq handlerSlot controlSlot \<Rightarrow> withoutPreemption $ do setIRQState irqstate.IRQSignal irq;
cteInsert (capability.IRQHandlerCap irq) controlSlot handlerSlot
od) proof (prove)
goal (3 subgoals):
 1. \<And>x11 x12 x13 s. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13; invs s \<and> valid_list s \<and> valid_sched s \<and> cte_wp_at ((=) cap.NullCap) x12 s \<and> cte_wp_at ((=) cap.IRQControlCap) x13 s \<and> ex_cte_cap_wp_to is_cnode_cap x12 s \<and> real_cte_at x12 s \<and> x11 \<le> maxIRQ\<rbrakk> \<Longrightarrow> valid_objs s \<and> pspace_distinct s \<and> pspace_aligned s \<and> valid_mdb s \<and> x13 \<noteq> x12 \<and> cte_wp_at (\<lambda>a. a = cap.NullCap) x12 s \<and> is_simple_cap (cap.IRQHandlerCap x11) \<and> cte_wp_at (safe_parent_for (cdt s) x13 (cap.IRQHandlerCap x11)) x13 s
 2. \<And>x11 x12 x13 s. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13; (invs' and (cte_wp_at' (\<lambda>cte. cteCap cte = capability.NullCap) (cte_map x12) and cte_wp_at' (\<lambda>cte. cteCap cte = capability.IRQControlCap) (cte_map x13) and ex_cte_cap_wp_to' (\<lambda>_. True) (cte_map x12) and real_cte_at' (cte_map x12) and Not \<circ> irq_issued' x11 and (\<lambda>y. x11 \<le> maxIRQ))) s\<rbrakk> \<Longrightarrow> ((\<lambda>_. True) and (\<lambda>s. pspace_distinct' s \<and> pspace_aligned' s \<and> valid_mdb' s \<and> x11 \<le> maxIRQ \<and> is_simple_cap' (capability.IRQHandlerCap x11) \<and> cte_wp_at' (\<lambda>a. cteCap a = capability.NullCap) (cte_map x12) s \<and> safe_parent_for' (ctes_of s) (cte_map x13) (capability.IRQHandlerCap x11))) s
 3. \<And>x2. \<lbrakk>\<exists>ivk'. i' = irqcontrol_invocation.ArchIRQControl ivk' \<and> arch_irq_control_inv_relation x2 ivk'; i = irq_control_invocation.ArchIRQControl x2\<rbrakk> \<Longrightarrow> corres (dc \<oplus> dc) (einvs and arch_irq_control_inv_valid x2) (invs' and irq_control_inv_valid' i') (arch_invoke_irq_control x2) (case i' of irqcontrol_invocation.ArchIRQControl invok \<Rightarrow> Arch.performIRQControl invok | Invocations_H.irqcontrol_invocation.IssueIRQHandler irq handlerSlot controlSlot \<Rightarrow> withoutPreemption $ do setIRQState irqstate.IRQSignal irq;
cteInsert (capability.IRQHandlerCap irq) controlSlot handlerSlot
od) proof (prove)
goal (2 subgoals):
 1. \<And>x11 x12 x13 s. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map x12) (cte_map x13); i = IRQControl x11 x12 x13; (invs' and (cte_wp_at' (\<lambda>cte. cteCap cte = capability.NullCap) (cte_map x12) and cte_wp_at' (\<lambda>cte. cteCap cte = capability.IRQControlCap) (cte_map x13) and ex_cte_cap_wp_to' (\<lambda>_. True) (cte_map x12) and real_cte_at' (cte_map x12) and Not \<circ> irq_issued' x11 and (\<lambda>y. x11 \<le> maxIRQ))) s\<rbrakk> \<Longrightarrow> ((\<lambda>_. True) and (\<lambda>s. pspace_distinct' s \<and> pspace_aligned' s \<and> valid_mdb' s \<and> x11 \<le> maxIRQ \<and> is_simple_cap' (capability.IRQHandlerCap x11) \<and> cte_wp_at' (\<lambda>a. cteCap a = capability.NullCap) (cte_map x12) s \<and> safe_parent_for' (ctes_of s) (cte_map x13) (capability.IRQHandlerCap x11))) s
 2. \<And>x2. \<lbrakk>\<exists>ivk'. i' = irqcontrol_invocation.ArchIRQControl ivk' \<and> arch_irq_control_inv_relation x2 ivk'; i = irq_control_invocation.ArchIRQControl x2\<rbrakk> \<Longrightarrow> corres (dc \<oplus> dc) (einvs and arch_irq_control_inv_valid x2) (invs' and irq_control_inv_valid' i') (arch_invoke_irq_control x2) (case i' of irqcontrol_invocation.ArchIRQControl invok \<Rightarrow> Arch.performIRQControl invok | Invocations_H.irqcontrol_invocation.IssueIRQHandler irq handlerSlot controlSlot \<Rightarrow> withoutPreemption $ do setIRQState irqstate.IRQSignal irq;
cteInsert (capability.IRQHandlerCap irq) controlSlot handlerSlot
od) proof (prove)
goal (2 subgoals):
 1. \<And>x11 a b aa ba s. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map (a, b)) (cte_map (aa, ba)); i = IRQControl x11 (a, b) (aa, ba); valid_objs' s; pspace_aligned' s; pspace_distinct' s; no_0_obj' s; valid_mdb' s; sch_act_wf (ksSchedulerAction s) s; Invariants_H.valid_queues s; sym_refs (state_refs_of' s); if_live_then_nonz_cap' s; if_unsafe_then_cap' s; valid_idle' s; valid_global_refs' s; valid_arch_state' s; valid_irq_node' (irq_node' s) s; valid_irq_handlers' s; valid_irq_states' s; valid_machine_state' s; irqs_masked' s; valid_queues' s; ct_not_inQ s; ct_idle_or_in_cur_domain' s; valid_pde_mappings' s; pspace_domain_valid s; ksCurDomain s \<le> maxDomain; ksDomSchedule (KernelInit_H.newKernelState undefined) \<noteq> []; \<forall>x\<in>set (ksDomSchedule (KernelInit_H.newKernelState undefined)). dschDomain x \<le> maxDomain \<and> 0 < dschLength x; ksDomSchedule s = ksDomSchedule (KernelInit_H.newKernelState undefined); ksDomScheduleIdx s < length (ksDomSchedule (KernelInit_H.newKernelState undefined)); untyped_ranges_zero' s; cur_tcb' s; cte_wp_at' (\<lambda>cte. cteCap cte = capability.NullCap) (cte_map (a, b)) s; cte_wp_at' (\<lambda>cte. cteCap cte = capability.IRQControlCap) (cte_map (aa, ba)) s; ex_cte_cap_wp_to' (\<lambda>_. True) (cte_map (a, b)) s; real_cte_at' (cte_map (a, b)) s; \<not> irq_issued' x11 s; x11 \<le> maxIRQ\<rbrakk> \<Longrightarrow> safe_parent_for' (ctes_of s) (cte_map (aa, ba)) (capability.IRQHandlerCap x11)
 2. \<And>x2. \<lbrakk>\<exists>ivk'. i' = irqcontrol_invocation.ArchIRQControl ivk' \<and> arch_irq_control_inv_relation x2 ivk'; i = irq_control_invocation.ArchIRQControl x2\<rbrakk> \<Longrightarrow> corres (dc \<oplus> dc) (einvs and arch_irq_control_inv_valid x2) (invs' and irq_control_inv_valid' i') (arch_invoke_irq_control x2) (case i' of irqcontrol_invocation.ArchIRQControl invok \<Rightarrow> Arch.performIRQControl invok | Invocations_H.irqcontrol_invocation.IssueIRQHandler irq handlerSlot controlSlot \<Rightarrow> withoutPreemption $ do setIRQState irqstate.IRQSignal irq;
cteInsert (capability.IRQHandlerCap irq) controlSlot handlerSlot
od) proof (prove)
goal (2 subgoals):
 1. \<And>x11 a b aa ba s cte ctea. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map (a, b)) (cte_map (aa, ba)); i = IRQControl x11 (a, b) (aa, ba); valid_objs' s; pspace_aligned' s; pspace_distinct' s; no_0_obj' s; valid_mdb' s; sch_act_wf (ksSchedulerAction s) s; Invariants_H.valid_queues s; sym_refs (state_refs_of' s); if_live_then_nonz_cap' s; if_unsafe_then_cap' s; valid_idle' s; valid_global_refs' s; valid_arch_state' s; valid_irq_node' (irq_node' s) s; valid_irq_handlers' s; valid_irq_states' s; valid_machine_state' s; irqs_masked' s; valid_queues' s; ct_not_inQ s; ct_idle_or_in_cur_domain' s; valid_pde_mappings' s; pspace_domain_valid s; ksCurDomain s \<le> maxDomain; ksDomSchedule (KernelInit_H.newKernelState undefined) \<noteq> []; \<forall>x\<in>set (ksDomSchedule (KernelInit_H.newKernelState undefined)). dschDomain x \<le> maxDomain \<and> 0 < dschLength x; ksDomSchedule s = ksDomSchedule (KernelInit_H.newKernelState undefined); ksDomScheduleIdx s < length (ksDomSchedule (KernelInit_H.newKernelState undefined)); untyped_ranges_zero' s; cur_tcb' s; ex_cte_cap_wp_to' (\<lambda>_. True) (cte_map (a, b)) s; real_cte_at' (cte_map (a, b)) s; \<not> irq_issued' x11 s; x11 \<le> maxIRQ; ctes_of s (cte_map (a, b)) = Some cte; cteCap cte = capability.NullCap; ctes_of s (cte_map (aa, ba)) = Some ctea; cteCap ctea = capability.IRQControlCap\<rbrakk> \<Longrightarrow> \<exists>parent. (\<exists>node. ctea = CTE parent node) \<and> global.sameRegionAs parent (capability.IRQHandlerCap x11) \<and> (parent = capability.IRQControlCap \<and> (\<forall>p n'. ctes_of s p \<noteq> Some (CTE (capability.IRQHandlerCap x11) n')) \<or> isUntypedCap parent \<and> descendants_of' (cte_map (aa, ba)) (ctes_of s) = {} \<and> capRange (capability.IRQHandlerCap x11) \<noteq> {})
 2. \<And>x2. \<lbrakk>\<exists>ivk'. i' = irqcontrol_invocation.ArchIRQControl ivk' \<and> arch_irq_control_inv_relation x2 ivk'; i = irq_control_invocation.ArchIRQControl x2\<rbrakk> \<Longrightarrow> corres (dc \<oplus> dc) (einvs and arch_irq_control_inv_valid x2) (invs' and irq_control_inv_valid' i') (arch_invoke_irq_control x2) (case i' of irqcontrol_invocation.ArchIRQControl invok \<Rightarrow> Arch.performIRQControl invok | Invocations_H.irqcontrol_invocation.IssueIRQHandler irq handlerSlot controlSlot \<Rightarrow> withoutPreemption $ do setIRQState irqstate.IRQSignal irq;
cteInsert (capability.IRQHandlerCap irq) controlSlot handlerSlot
od) proof (prove)
goal (2 subgoals):
 1. \<And>x11 a b aa ba s cte ctea x1 x2. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map (a, b)) (cte_map (aa, ba)); i = IRQControl x11 (a, b) (aa, ba); valid_objs' s; pspace_aligned' s; pspace_distinct' s; no_0_obj' s; valid_mdb' s; sch_act_wf (ksSchedulerAction s) s; Invariants_H.valid_queues s; sym_refs (state_refs_of' s); if_live_then_nonz_cap' s; if_unsafe_then_cap' s; valid_idle' s; valid_global_refs' s; valid_arch_state' s; valid_irq_node' (irq_node' s) s; valid_irq_handlers' s; valid_irq_states' s; valid_machine_state' s; irqs_masked' s; valid_queues' s; ct_not_inQ s; ct_idle_or_in_cur_domain' s; valid_pde_mappings' s; pspace_domain_valid s; ksCurDomain s \<le> maxDomain; ksDomSchedule (KernelInit_H.newKernelState undefined) \<noteq> []; \<forall>x\<in>set (ksDomSchedule (KernelInit_H.newKernelState undefined)). dschDomain x \<le> maxDomain \<and> 0 < dschLength x; ksDomSchedule s = ksDomSchedule (KernelInit_H.newKernelState undefined); ksDomScheduleIdx s < length (ksDomSchedule (KernelInit_H.newKernelState undefined)); untyped_ranges_zero' s; cur_tcb' s; ex_cte_cap_wp_to' (\<lambda>_. True) (cte_map (a, b)) s; real_cte_at' (cte_map (a, b)) s; \<not> irq_issued' x11 s; x11 \<le> maxIRQ; ctes_of s (cte_map (a, b)) = Some cte; cteCap cte = capability.NullCap; ctes_of s (cte_map (aa, ba)) = Some ctea; cteCap ctea = capability.IRQControlCap; ctea = CTE x1 x2\<rbrakk> \<Longrightarrow> \<exists>parent. (\<exists>node. ctea = CTE parent node) \<and> global.sameRegionAs parent (capability.IRQHandlerCap x11) \<and> (parent = capability.IRQControlCap \<and> (\<forall>p n'. ctes_of s p \<noteq> Some (CTE (capability.IRQHandlerCap x11) n')) \<or> isUntypedCap parent \<and> descendants_of' (cte_map (aa, ba)) (ctes_of s) = {} \<and> capRange (capability.IRQHandlerCap x11) \<noteq> {})
 2. \<And>x2. \<lbrakk>\<exists>ivk'. i' = irqcontrol_invocation.ArchIRQControl ivk' \<and> arch_irq_control_inv_relation x2 ivk'; i = irq_control_invocation.ArchIRQControl x2\<rbrakk> \<Longrightarrow> corres (dc \<oplus> dc) (einvs and arch_irq_control_inv_valid x2) (invs' and irq_control_inv_valid' i') (arch_invoke_irq_control x2) (case i' of irqcontrol_invocation.ArchIRQControl invok \<Rightarrow> Arch.performIRQControl invok | Invocations_H.irqcontrol_invocation.IssueIRQHandler irq handlerSlot controlSlot \<Rightarrow> withoutPreemption $ do setIRQState irqstate.IRQSignal irq;
cteInsert (capability.IRQHandlerCap irq) controlSlot handlerSlot
od) proof (prove)
goal (2 subgoals):
 1. \<And>x11 a b aa ba s cte x2 p n'. \<lbrakk>i' = Invocations_H.irqcontrol_invocation.IssueIRQHandler x11 (cte_map (a, b)) (cte_map (aa, ba)); i = IRQControl x11 (a, b) (aa, ba); valid_objs' s; pspace_aligned' s; pspace_distinct' s; no_0_obj' s; valid_mdb' s; sch_act_wf (ksSchedulerAction s) s; Invariants_H.valid_queues s; sym_refs (state_refs_of' s); if_live_then_nonz_cap' s; if_unsafe_then_cap' s; valid_idle' s; valid_global_refs' s; valid_arch_state' s; valid_irq_node' (irq_node' s) s; valid_irq_handlers' s; valid_irq_states' s; valid_machine_state' s; irqs_masked' s; valid_queues' s; ct_not_inQ s; ct_idle_or_in_cur_domain' s; valid_pde_mappings' s; pspace_domain_valid s; ksCurDomain s \<le> maxDomain; ksDomSchedule (KernelInit_H.newKernelState undefined) \<noteq> []; \<forall>x\<in>set (ksDomSchedule (KernelInit_H.newKernelState undefined)). dschDomain x \<le> maxDomain \<and> 0 < dschLength x; ksDomSchedule s = ksDomSchedule (KernelInit_H.newKernelState undefined); ksDomScheduleIdx s < length (ksDomSchedule (KernelInit_H.newKernelState undefined)); untyped_ranges_zero' s; cur_tcb' s; ex_cte_cap_wp_to' (\<lambda>_. True) (cte_map (a, b)) s; real_cte_at' (cte_map (a, b)) s; \<not> irq_issued' x11 s; x11 \<le> maxIRQ; ctes_of s (cte_map (a, b)) = Some cte; cteCap cte = capability.NullCap; ctes_of s (cte_map (aa, ba)) = Some (CTE capability.IRQControlCap x2); ctes_of s p = Some (CTE (capability.IRQHandlerCap x11) n')\<rbrakk> \<Longrightarrow> False
 2. \<And>x2. \<lbrakk>\<exists>ivk'. i' = irqcontrol_invocation.ArchIRQControl ivk' \<and> arch_irq_control_inv_relation x2 ivk'; i = irq_control_invocation.ArchIRQControl x2\<rbrakk> \<Longrightarrow> corres (dc \<oplus> dc) (einvs and arch_irq_control_inv_valid x2) (invs' and irq_control_inv_valid' i') (arch_invoke_irq_control x2) (case i' of irqcontrol_invocation.ArchIRQControl invok \<Rightarrow> Arch.performIRQControl invok | Invocations_H.irqcontrol_invocation.IssueIRQHandler irq handlerSlot controlSlot \<Rightarrow> withoutPreemption $ do setIRQState irqstate.IRQSignal irq;
cteInsert (capability.IRQHandlerCap irq) controlSlot handlerSlot
od) proof (prove)
goal (1 subgoal):
 1. \<And>x2. \<lbrakk>\<exists>ivk'. i' = irqcontrol_invocation.ArchIRQControl ivk' \<and> arch_irq_control_inv_relation x2 ivk'; i = irq_control_invocation.ArchIRQControl x2\<rbrakk> \<Longrightarrow> corres (dc \<oplus> dc) (einvs and arch_irq_control_inv_valid x2) (invs' and irq_control_inv_valid' i') (arch_invoke_irq_control x2) (case i' of irqcontrol_invocation.ArchIRQControl invok \<Rightarrow> Arch.performIRQControl invok | Invocations_H.irqcontrol_invocation.IssueIRQHandler irq handlerSlot controlSlot \<Rightarrow> withoutPreemption $ do setIRQState irqstate.IRQSignal irq;
cteInsert (capability.IRQHandlerCap irq) controlSlot handlerSlot
od)