Patent ID: 10832961

Abstract:
Embodiments of the invention are directed to a method of forming an integrated circuit (IC). The method includes forming a first transistor and a second transistor over a substrate. The first transistor includes a first gate structure having a first gate spacer, and the second transistor includes a second gate structure having a second gate spacer. A top portion of the first gate spacer is replaced with a first sacrificial gate spacer region, and a top portion of the second gate spacer is replaced with a second sacrificial gate spacer region. A source or drain (S/D) conductive plug trench and a S/D cap trench are formed in the dielectric region of the IC and positioned over a S/D region of the first transistor. A volume of the S/D cap trench is increased by removing the first sacrificial gate spacer region and/or the second sacrificial gate spacer region.