Patent ID: 10224242

Abstract:
Semiconductor devices with low-resistivity metallic interconnect structures are provided. For example, a sacrificial dielectric layer is formed on a substrate, and patterned to form an opening in the sacrificial dielectric layer. The opening is filled with a metallic material to form a metallic interconnect structure, and the sacrificial dielectric layer is removed to expose the metallic interconnect structure. A heat treatment process is applied to the exposed metallic interconnect structure to modulate a microstructure of the metallic material of the metallic interconnect structure from a first microstructure to a second microstructure. A conformal liner layer is selectively deposited on exposed surfaces of the metallic interconnect structure, subsequent to the heat treatment process. A dielectric layer is formed to encapsulate the metallic interconnect structure in dielectric material, wherein the conformal liner layer serves as a diffusion barrier layer between the metallic interconnect structure and the dielectric layer.