Patent ID: 10192790

Abstract:
A method for fabricating an SRAM device includes providing a base substrate including a pull up transistor (PUT) region and a pull down transistor (PDT) region, forming a gate dielectric layer, forming a first work function (WF) layer using a P-type WF material, removing the first WF layer formed in the PDT region, forming a second WF layer using a P-type WF material on the first WF layer in the PUT region and on the gate dielectric layer in the PDT region, removing the second WF layer formed in the PDT region, forming a third WF layer using an N-type WF material on the top and the sidewall surfaces of the second WF layer in the PUT region, the sidewall surface of the first WF layer in the PUT region, and the gate dielectric layer in the PDT region, and forming a gate electrode layer on the third WF layer.