Patent ID: 11522545

Abstract:
A level shifter circuit for translating input signal to output signal is disclosed. The level shifter includes an input stage and a latch stage. The latch stage comprises at least a transistor characterized in a substantially matched transconductance with the input stage for preventing a discrete realization of a voltage clamp circuit. The transistor is a semiconductor device including a source region having a source doping region and a drain region having a first doping region and a second doping region. The first doping region is doped with a first conductivity impurity. The second doping region is disposed around the first doping region so as to surround the first doping region, and is doped with a second conductivity impurity. The second doping region has a higher on-resistance than the first doping region, thereby a high resistive series path is created by the second doping region to mimic an embedded resistor.