Patent ID: 10168719

Abstract:
The present invention provides a digital low dropout regulator and a control method thereof. The regulator comprises a voltage comparator, a counter, a decoder, a PMOSFET array and a divider. The voltage comparator receives an actual voltage output from the PMOSFET array through the positive input terminal, receives a reference voltage through the negative input terminal, and compares the actual voltage and the reference voltage to obtain a level signal. The divider calculates based on an output voltage pre-configured for a PMOSFET array and an actual voltage output by the PMOSFET array in at least two clock cycles to obtain a first value. The counter generates a control signal based on the level signal and the first value. The decoder receives the control signal transmitted by the counter and controlling the number of switched-on transistors, in the PMOSFET on a basis of the control signal.