Patent ID: 10120813

Abstract:
Address translation apparatus comprises translation circuitry to access an ordered set of two or more address translation tables stored at respective storage locations to generate an address translation between an input virtual memory address in a virtual memory address space and a respective translated memory address in a translated memory address space. Each address translation table in the ordered set of two or more address translation tables is configured to provide translation data indicating mappings between virtual memory addresses and translated memory addresses for a contiguous range of virtual memory addresses applicable to that address translation table. The ordered set of address translation tables are ordered with respect to one another according to an order of their respective ranges of virtual memory addresses for which they provide translation data. Each address translation table in the ordered set of two or more address translation tables comprises location information defining the storage location of at least those of the other address translation tables in the ordered set of two or more address translation tables which are adjacent to that address translation table in the ordered set of two or more address translation tables.