Patent ID: 10381376

Abstract:
A three-dimensional memory device includes alternating stacks of insulating strips and electrically conductive strips located over a substrate and laterally spaced apart among one another by vertically undulating trenches. The vertically undulating trenches have a greater lateral extent at levels of the electrically conductive strips than at levels of the insulating strips. An interlaced two-dimensional array of memory stack assemblies and dielectric pillar structures are located in the vertically undulating trenches. Each memory stack assembly includes a vertical semiconductor channel and a pair of memory films including a respective pair of convex outer sidewalls that contact, or are spaced by a uniform distance from, concave sidewalls of the electrically conductive strips. Local electrical field at laterally protruding tips of the vertical semiconductor channels are enhanced due to the geometric effect provided by the concave sidewalls of the electrically conductive strips to facilitate faster program and erase operations.