Patent ID: 10871900

Abstract:
According to one embodiment, a memory system comprises a non-volatile semiconductor memory having a plurality of first storage areas, the first storage areas being capable of including one or more second storage areas, a plurality of third storage areas in which data is written in a first mode, and a plurality of fourth storage areas in which data is written in a second mode, the first mode being different from the second mode, and processing circuitry. The processing circuitry performs acquiring the one or more second storage areas from the plurality of first storage areas, selecting a plurality of storage areas from the plurality of third storage areas or from the plurality of fourth storage areas based on a rate of valid date in fifth storage area, the fifth storage area being the plurality of fourth storage areas, the rate of valid data in the fifth storage area being a rate of the total amount of valid data stored in the fifth storage area with respect to the total capacity of the fifth storage area, and writing the valid data stored in the selected plurality of storage areas in the acquired one or more second storage areas using the second mode.