Patent ID: 11335428

Abstract:
The disclosed embodiments relate to method, apparatus and system for testing memory circuitry and diagnostic components designed to test the memory circuitry. The memory may be tested regularly using Memory Built-In Self-Test (MBIST) to detect memory failure. Error Correction Code (ECC)/Parity is implemented for SRAM/Register Files/ROM memory structures to protect against transient and permanent faults during runtime. ECC/Parity encoder and decoder logic detect failure on both data and address buses and are intended to catch soft error or structural fault in address decoding logic in SRAM Controller, where data may be read/written from/to different locations due to faults. ECC/parity logic on the memory structures are subject to failures. In certain exemplary embodiments, an array test controller is used to generate and transmit error vectors to thereby determine faulty diagnostic components. The test vectors may be generated randomly to test the diagnostic components during run-time for in-field testing.