Patent ID: 11803685

Abstract:
The disclosure discloses a layout design method, chip and terminal of power device, wherein the non-top metal layout design: the metal is routed along the first direction and several metal wires that fully occupy the available area of the die unit are thereby obtained, and the wiring properties of the metal wires are sequentially changed at intervals, making the source ends and the drain ends of the device are alternately distributed at intervals, and the metal routing in two or more layers of non-top metal are arranged vertically; the top metal layout design: the source end region and drain end region in the top metal are formed into sheets independently and the pad is arranged in the top metal region; eventually realize the interconnection of metal layers and complete the layout design. The disclosure adopts a criss-cross design between non-top metals, thereby the device has a smaller parasitic resistance value; the removal of the stack-up design can reduce the metal layer design and save the cost; the source end and drain end regions in the top metal are designed into sheets to ensure the adequacy of the interconnection between the metal layers and further improve the reliability of the device.