Patent ID: 10423482

Abstract:
The disclosed embodiments provide a memory system that provides error detection and correction. Each block of data in the memory system includes an array of bits logically organized into R rows and C columns, including C−M−1 data-bit columns containing data bits, a row check bit column including row-parity bits for each of the R rows in the block, and M inner check bit columns that collectively include MR inner check bits. These inner check bits are defined to cover bits in the array in accordance with a set of check vectors, wherein each check vector is associated with a different bit in the array and is an element of Res(P), a residue system comprising a set of polynomials with GF(2) coefficients modulo a polynomial P with GF(2) coefficients, wherein each column is associated with a different pin in a memory module interface, and wherein the check bits are generated from the data bits to facilitate block-level detection and correction for errors that arise during the transmission. During operation, the system transmits a block of data from the memory. Next, the system uses an error-detection circuit to examine the block of data, and determine whether an error has occurred during the transmission based on the examination.