Patent ID: 10901020

Abstract:
In one embodiment, a system including a duty-cycle-monitoring circuit is configured to receive a monitored signal having cycles that have a high portion and a low portion. The duty-cycle-monitoring circuit includes: a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal, a plurality of corresponding flip-flops. Each flip-flop is triggered by a second signal based on the monitored signal. The data input of each flip-flop is connected to an output of a corresponding buffer. The duty-cycle-monitoring circuit further includes a control circuit configured to determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal and determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.