Patent ID: 10877827

Abstract:
A method for biasing read voltage for flash memory in a storage system, performed by the storage system, is provided. The method includes determining a first number of bit errors for a first read of data at an address in the flash memory at a previously determined optimum read voltage level. Determining a second number of bit errors for a second read of the data at the address in the flash memory at a further read voltage level. Adjusting the optimum read voltage level up or down based on a comparison of the first number of bit errors and the second number of bit errors. Iterating each method operation, to adjust the optimum read voltage level in a first direction of the further read voltage level when the second number of bit errors is less than the first number of bit errors, and to adjust the optimum read voltage level in a second direction when the second number of bit errors is greater than the first number of bit errors.