Patent ID: 10380302

Abstract:
An integrated circuit includes a plurality of vertically-stacked layers including a front end of line (FEOL) layer and a back end of line (BEOL) layer. The FEOL layer includes individual transistors that are not interconnected. The BEOL layer includes transistor interconnections and no transistors. The transistors are electrically connected to the transistor interconnections by vias within the FEOL ad BEOL layers. The FEOL and BEOL layers each have contact pads on the top and bottom surfaces thereof that are each in alignment with vias, are arranged in a checkerboard pattern, and occupy about fifty percent of the surface area of the FEOL and BEOL layers. The contact pads on a top surface of the FEOL layer are in electrical communication with contact pads on a bottom surface of the BEOL layer to facilitate vertical current flow between the transistors and the transistor interconnections through the vias.