Patent ID: 10691606

Abstract:
An apparatus and method are provided for supporting multiple cache features. The apparatus provides cache storage comprising a plurality of cache ways and organised as a plurality of ways groups, where each way group comprises multiple cache ways from the plurality of cache ways. First cache feature circuitry is provided to implement a first cache feature that is applied to the way groups, and second cache feature circuitry is provided to implement a second cache feature that is applied to the way groups. Way group control circuitry is then arranged to provide a first mapping defining which cache ways belong to each way group when the first cache feature is applied to the way groups, and a second mapping defining which cache ways belong to each way group when the second cache feature is applied to the way groups. The first mapping and the second mapping are selected so as to prevent application of a cache feature to the way groups by one of the cache feature circuits from interfering with the ability of the other cache feature circuit to access at least one cache way in each of the way groups. Such an approach alleviates the risk of actions taken by one of the cache features from interfering with the ability of the other cache feature to operate as intended.