Patent ID: 10713196

Abstract:
The present disclosure is directed to accelerator circuitry useful in a network applications, such as cloud-based radio access networks. The accelerator circuitry includes interface circuitry that couples the accelerator circuitry to each of a plurality of processor circuits and to system memory circuitry. The accelerator circuitry also includes queue management circuitry, local storage circuitry, direct memory access (DMA) circuitry, and a plurality of accelerator circuits. In operation, the processor circuit communicates a message to the queue management circuitry. The message includes pointer data and prioritized data. The queue management circuitry enqueues the message in one of a plurality of queues. The DMA circuitry receives the message and locates a descriptor at the address designed by the pointer. The DMA circuitry retrieves input data, selects an accelerator circuit, and provides the input data to the selected accelerator circuit. The accelerator circuit returns output data to the DMA circuitry, The output data is stored in system memory circuitry.