Patent ID: 10474543

Abstract:
A method for economizing computing resources and verifying an integrity of parameters of a neural network by inserting test pattern into a background area of an input image is provided for fault tolerance, fluctuation robustness in extreme situations, functional safety on the neural network, and an annotation cost reduction. The method includes: a computing device (a) generating t-th background prediction information of a t-th image by referring to information on each of a (t−2)-th image and a (t−1)-th image; (b) inserting the test pattern into the t-th image by referring to the t-th background prediction information, to thereby generate an input for verification; (c) generating an output for verification from the input for verification; and (d) determining the integrity of the neural network by referring to the output for verification and an output for reference. According to the method, a data compression and a computation reduction are achieved.