Patent ID: 11810614

Abstract:
Embodiments provide a data processing circuit and a device. The circuit includes: a first bank group 301 and a second bank group 302, a write circuit 303 including one write input buffer circuit 3031, and a write circuit 304 including one write input buffer circuit 3041. The two write circuits 303 and 304 are configured to: receive stored data from a same write bus 306 by means of the write input buffer circuits 3031 and 3041 respectively, write the stored data into the first bank group 301 by means of a first read-write bus 307, and write the stored data into the second bank group 302 by means of a second read-write bus 308. Frequencies of control signals employed by the two write input buffer circuits 3031 and 3041 both are half of a clock frequency configured for writing the stored data by the write bus 306.