Patent ID: 10522673

Abstract:
Plural trenches are provided in a semiconductor substrate. First p+-type regions underlie bottoms of the trenches. A MOS gate is embedded in first trenches of the trenches and one unit cell of a trench-gate-type MOSFET is configured. One unit cell of a trench-type SBD is constituted by a Schottky junction formed by an n-type current spreading region and a conductive layer embedded in a second trench of the trenches. Between second trenches in which the trench-type SBD is embedded, at least two of the first trenches in which a MOS gate is embedded are disposed. A sum of widths of all first p+-type regions disposed in a MOS cell region C′ that is substantially half of a region between the adjacent second trenches is in a range of about 2 μm to 8 μm.