Patent ID: 10691461

Abstract:
Data processing circuitry comprises fetch circuitry to fetch blocks, containing instructions for execution, defined by a fetch queue; and prediction circuitry to predict one or more next blocks to be fetched and to add the predicted next blocks to the fetch queue; the prediction circuitry comprising: branch prediction circuitry to detect a predicted branch destination for a branch instruction in a current block, the predicted branch destination representing either a branch target for a branch predicted to be taken or a next instruction after the branch instruction, for a branch predicted not to be taken; and sequence prediction circuitry to detect sequence data, associated with the predicted branch destination, identifying a next block following the predicted branch destination in the program flow order having a next instance of a branch instruction, to add to the fetch queue the identified next block and any intervening blocks between the current block and the identified next block, and to initiate branch prediction in respect of the predicted next instance of a branch instruction.