Patent ID: 10211847

Abstract:
A successive approximation register (SAR) analog-digital converter (ADC) and a method for operating the same are provided. The SAR ADC includes a first capacitor DAC (CDAC), a comparator and a controller. The first CDAC receives and samples an analog input signal to generate a first voltage. The comparator compares the first voltage with a comparison reference voltage to generate a first comparison result. In a k-th iteration of at least two iterations, the controller switches a k-th switching capacitor set from a first state to a second state, such that the first CDAC generates a second voltage, and the comparator compares the second voltage with the comparison reference voltage to generate a second comparison result. The controller determines a window region and determines whether the k-th switching capacitor set is switched back to the first state according to the first comparison result and the second comparison result.