Patent ID: 10686070

Abstract:
A trench-gate MOSFET is disclosed. A plurality of trenches penetrating through a well region are formed in a semiconductor substrate, and horizontal widths of the trenches are defined by first openings formed. The trenches are filled with polysilicon gates. The first openings at the tops of the polysilicon gates are filled with a first dielectric layer. Under the self-alignment definition of the first dielectric layer, the portions, between the first openings, of the hard mask layer are removed to form second openings. First inner spacers are formed through self-alignment on inner sides of the second openings, and the second openings are narrowed by the first inner spacers to form third openings. The third openings are filled with a metal layer, so that a source contact hole is formed through self-alignment at the top of the source region. A method for manufacturing a trench-gate MOSFET is further disclosed.