Patent ID: 12016172

Abstract:
An N+ layer connects to the bottom portion of a Si pillar standing on a substrate 1 and an N+ layer connects to the top portion of the Si pillar. Of the N+ layer and the N+ layer, one serves as the source and the other serves as the drain. A region of the Si pillar between the N+ layer and the N+ layer serves as a channel region. A first gate insulating layer surrounds the lower portion of the Si pillar and a second gate insulating layer surrounds the upper portion of the Si pillar. The first gate insulating layer and the second gate insulating layer are respectively disposed in contact with or near the N+ layers serving as the source and the drain. A first gate conductor layer and a second gate conductor layer surround the first gate insulating layer. The first gate conductor layer and the second gate conductor layer are formed so as to surround the first gate insulating layer and to be isolated from each other. A third gate conductor layer surrounds the second gate insulating layer. Thus, a dynamic flash memory cell is formed.