Patent ID: 10056151

Abstract:
A multi-read only memory (ROM) state machine circuit includes first and second ROMs (or other memory types), each ROM addressable as a plurality of rows. Each row of the first ROM includes a pointer. Each row of the second ROM includes a set of input compare bits and a next state identifier. A comparator circuit compares each input bit to the state machine circuit to a corresponding bit of the set of input compare bits from the second ROM. A register stores next state identifiers from the second ROM based on the comparator's outputs. Upon receipt of a clock edge, the stored next state identifier from the register is used an address to read a row from the first ROM. The pointer from the first ROM row is then used as an address to read a row from the second ROM. Responsive to the comparator circuit, the next state identifier corresponding to a set of input compare bits that match the input bits to the finite state machine circuit is stored in the register and used as an address to read another row from the first ROM.