Patent ID: 10504826

Abstract:
An electronics package is disclosed that comprises a multilayer interconnect structure including a plurality of insulating substrate layers each having a plurality of microvias formed therein, a plurality of conductive wiring layers positioned on the plurality of insulating substrate layers, and a plurality of conductive microvias in the plurality of microvias to, wherein a bottom wiring layer includes a plurality of first terminal pads that are positioned on a bottom surface of the multilayer interconnect structure. The electronics package also comprises an electrical component coupled to the bottom surface of the multilayer interconnect structure, the electrical component including first I/O pads aligned with the first terminal pads and second I/O pads aligned to regions of the multilayer interconnect structure without first terminal pads. The electronics package further comprises a plurality of conductive through vias extending through the multilayer interconnect structure and electrically connected to the plurality of second I/O pads.