Patent ID: 10840200

Abstract:
A manufacturing method of a chip package structure includes: dicing a wafer to separate chips formed thereon; mounting the chips on a carrier, wherein an active surface and pads of each chip are buried in an adhesive layer disposed on the carrier, and a top surface of the adhesive layer between the chips is bulged away from the carrier; forming an encapsulant to encapsulate the chips and cover the adhesive layer, wherein the encapsulant has a concave surface covering the top surface of the adhesive layer and a back surface opposite to the concave surface; removing the carrier and the adhesive layer; forming a first dielectric layer to cover the concave surface and the active surface; forming a patterned circuit layer on the first dielectric layer, to electrically connect to the pads through openings in the first dielectric layer; and forming a second dielectric layer on the patterned circuit layer.