Patent ID: 11416400

Abstract:
A cache memory subsystem includes a virtually-indexed virtually-tagged first-level data cache (L1D) and a physically-indexed physically-tagged second-level set-associative cache (L2). Each L2 entry is uniquely identified by a set index and a way number. The cache memory subsystem has an inclusive allocation policy. When a snoop request that specifies a physical memory line address hits in an entry in the L2, the cache memory subsystem forwards the snoop request to the L1D but substitutes a physical address proxy (PAP) for the physical memory line address. The PAP specifies the way number and the set index of the hit entry in the L2. To process the forwarded snoop request, the L1D uses N bits of the PAP to select S sets and uses the remaining PAP bits (diminutive PAP) for comparison with a diminutive PAP stored in each valid entry of the S selected sets.