Patent ID: 11563431

Abstract:
A reverse current suppression circuit for a PMOS transistor, which includes: a gate drive unit, when the source potential of the first PMOS transistor is lower than the drain potential, the gate drive unit making the gate potential of the first PMOS transistor equal to the drain potential, so that the first PMOS transistor comes into a reverse current suppression state; and a substrate switching unit, when the source potential of the first PMOS transistor is lower than the drain potential, the substrate switching unit short-circuiting the substrate of the first PMOS transistor with the drain of the first PMOS transistor. According to the present invention, when the source potential of the PMOS transistor is lower than the drain potential, the PMOS transistor can be controlled to operate in the reverse current suppression state, so that the PMOS transistor can be effectively protected.