Patent ID: 10770407

Abstract:
An integrated circuit (IC) structure includes a back end of line (BEOL) stack on a substrate, the BEOL stack having a plurality of metal layers therein and a plurality of inter-level dielectric (ILD) layers therein. The plurality of metal layers includes a lowermost metal layer and an uppermost metal layer. A pair of metal guard structures proximate a perimeter of the BEOL stack concentrically surrounds the active circuitry. Each metal guard structure includes a continuous metal fill between the lowermost metal layer and the uppermost metal layer of the plurality of metal layers. A set of interdigitating conductive elements within one of the plurality of metal layers includes a first plurality of conductive elements electrically coupled to one of the pair of metal guard structures interdigitating with a second plurality of conductive elements electrically coupled to the other of the pair of metal guard structures.