Patent ID: 11876037

Abstract:
A chip stacking and packaging structure includes a substrate, a first chip stacked on the substrate, a heat dissipation module, and a second chip stacked on the heat dissipation module. First bonding pads and second bonding pads are arranged on the substrate. First welding pins are arranged on the first chip. The first welding pins one-to-one cover and are one-to-one electrically connected to the first bonding pads. The heat dissipation module includes a first groove, a cooling liquid cavity, a liquid inlet, a liquid outlet, and first conductive columns. The first chip is embedded in the first groove. A side wall and a bottom wall of the first groove extend into the cooling liquid cavity. Each of the first conductive columns is electrically connected with a corresponding second bonding pad. Each of second welding pins of the second chip is electrically connected to a corresponding first conductive column.