Patent ID: 10637463

Abstract:
A voltage level shifting circuit includes two PMOS transistors and four NMOS transistors. Sources of the PMOS transistors receive a first supply voltage value, a first PMOS transistor gate coupled with drains of second PMOS and NMOS transistors is a first output, and a second PMOS transistor gate coupled with drains of first PMOS and NMOS transistors is a second output. The first NMOS transistor source is coupled with a third NMOS transistor drain, and the third NMOS transistor gate is a first input. The second NMOS transistor source is coupled with a fourth NMOS transistor drain, and the fourth NMOS transistor gate is a second input. A voltage generating circuit generates a voltage at first and second NMOS transistor gates based on the first supply voltage value and on a signal, the signal behaving based on the first supply voltage value and a different second supply voltage value.