Patent ID: 11756956

Abstract:
Disclosed is a semiconductor device comprising: a substrate; a vertical active region formed on the substrate and comprising a first source/drain region, a channel region, and a second source/drain region sequentially disposed in a vertical direction, the first source/drain region including a laterally extending portion extending beyond a portion of the active region above the laterally extending portion; a gate stack formed around the periphery of the channel region, the gate stack including a laterally extending portion; and a stack contact portion from above the laterally extending portion of the first source/drain region to the laterally extending portion of the first source/drain region. The stack contact portion comprises a three-layer structure sequentially disposed in the vertical direction: a lower layer portion, a middle layer portion, and an upper layer portion. The lower layer portion contains at least the same element as the first source/drain region, the middle layer portion contains at least the same element as the channel region, and the upper layer portion contains at least the same element as the second source/drain region.