Patent ID: 11862595

Abstract:
The present disclosure provides a packaging method for a fan-out wafer-level packaging structure, including: providing two or more semiconductor chips, and bonding the semiconductor chips to a bonding layer; packaging the semiconductor chips by a plastic packaging layer; removing the bonding layer, and forming a redistribution layer on the semiconductor chips, so as to achieve interconnection between the semiconductor chips, where the redistribution layer includes one or more redistribution sublayers stacked in sequence, and a method for forming each redistribution sublayer includes: forming a dielectric layer on the semiconductor chips; forming vias in the dielectric layer by photolithography; baking the dielectric layer having the vias formed therein, wherein the warpage of the dielectric layer around the vias is mitigated; curing the dielectric layer; and forming on the dielectric layer a patterned metal distribution layer corresponding to the vias; and forming metal bumps on the redistribution layer.