Patent ID: 10050612

Abstract:
A delay circuit includes precharge and discharge transistors configured to receive an input signal. The delay circuit also includes a resistor coupled to the precharge transistor having a negative temperature coefficient to thereby form a node. A capacitive device and an inverter are coupled to the node. The inverter produces an output signal. Responsive to the input signal having a first polarity, the precharge transistor is configured to be turned on and the discharge transistor is configured to be turned off to thereby cause current to flow through the precharge transistor to the capacitive device to thereby charge the capacitive device. Responsive to the input signal having a second polarity, the precharge and discharge transistors are configured to change state to thereby cause charge from the capacitive device to discharge through the resistor and through the discharge transistor. The voltage on the node decays to a level which eventually causes the inverter's output to change state.