Patent ID: 10651257

Abstract:
The present disclosure provides a manufacturing method of an array substrate, including: forming a gate layer on a substrate; forming a gate insulating material layer on the gate layer; forming a polysilicon material layer on the gate insulating material layer; depositing an etch stop material layer on the polysilicon material layer; channel doping the polysilicon material layer; etching the polysilicon material layer, the etch stop material layer and the gate insulating material layer to form an active layer, an etch stop layer and a gate insulating layer; forming a source/drain layer on the active layer and the gate insulating layer, the active layer being electrically connected to the source/drain layer, and forming a through hole on the source/drain layer to form a source and a drain, the through hole being corresponding to the active layer, and both of the source and the drain being electrically connected to the active layer.