Patent ID: 10928847

Abstract:
Methods and apparatuses relating to a hashing accelerator having a frequency scaled message scheduler data path circuit are described. In one embodiment, a hardware accelerator includes a message digest data path circuit comprising a first message digest circuit to output a second state vector, at a first clock rate, based on a first state vector and an output from a first switch, and a second message digest circuit to output a third state vector, at the first clock rate, based on the second state vector and an output from a second switch; a message scheduler data path circuit comprising at least one first message scheduler circuit to output an element into a second message vector, at a second clock rate that is slower than the first clock rate, based on a plurality of elements of a first message vector, and at least one second message scheduler circuit to output an element into a fourth message vector, at the second clock rate that is slower than the first clock rate, based on a plurality of elements of a third message vector; and a controller to switch the first switch at the second clock rate between sourcing a first element of the first message vector and a first element of the third message vector as the output from the first switch, and switch the second switch at the second clock rate between sourcing a second element of the first message vector and a second element of the third message vector as the output from the second switch.