Patent ID: 11552162

Abstract:
In a transparent display panel, a layer of each of a VSS voltage connection line and a VDD voltage connection line as a power line in a display region is different from a layer of a data line and a reference voltage connection line, while each of the VSS voltage connection line and the VDD voltage connection line partially overlaps the data line and the reference voltage connection line. Thus, an overall width of a line region may be reduced. Thus, an area of a pixel circuit region is reduced, such that an area of a transmissive region increases, thereby to increase an overall transmittance of the panel. Further, a width of each of the VSS voltage connection line and the VDD voltage connection line is large while reducing or minimizing an area of the line region in the display region. This reduces or minimizes occurrence of VDD drop or VSS rise, thereby to reduce luminance non-uniformity of the panel.