Patent ID: 11742857

Abstract:
A level shifter circuit shifts a digital signal between first and second voltage levels. For a LOW to HIGH transition, an output PMOS transistor is switched on using a first NMOS transistor activated by the digital signal at the first voltage level while a second NMOS transistor is switched off to uncouple the output PMOS transistor from ground, and a third NMOS transistor is switched off to uncouple a current mirror circuit from ground. For a HIGH to LOW transition, the output PMOS transistor is switched off and a fourth NMOS transistor is switched on using an output of the current mirror circuit. The second NMOS transistor is switched on using an inverted version of the digital signal, and the current in the current mirror circuit is turned off with a fifth NMOS transistor when the drain of the output PMOS transistor approaches the voltage level of ground.