Patent ID: 10999214

Abstract:
A method, apparatus and system for a secure memory with restricted access by processors. System has a plurality of processor units (PUs) coupled to a block of memory with at least one section secured (BMSS) against hacking by not allowing all PUs to access BMSS. One or more PUs has access to BMSS and is implemented with a dedicated function(s) that no other PU can perform such as a security function for encryption key checks. A thread running on a given PU that lacks access to a given memory location in BMSS is transferred to another PU with i) access to given memory location in BMSS; ii) implemented dedicated function; and/or iii) locked down instruction memory not free to run other code. Any attempt to breach protocol issues a fault. Existing code is hardened against less secure user code by only permitting authorized routines to transfer to the implemented PU.