Patent ID: 11631743

Abstract:
A semiconductor structure and a forming method of a semiconductor structure are provided. One form of the forming method includes: providing a base, where a discrete gate structure is formed on the base, a spacer is formed on a side wall of the gate structure, and a source/drain doped layer is formed in the base on two sides of the gate structure, and a bottom dielectric layer covering the source/drain doped layer is formed on the two sides of the gate structure; forming a bottom source/drain plug running through the bottom dielectric layer above the source/drain doped layer, a source/drain cap layer located on a top surface of the bottom source/drain plug, a gate cap layer located on a top surface of the gate structure, and an etching barrier layer located between the gate cap layer and the source/drain cap layer and covering a top surface of the spacer; forming a top dielectric layer covering the gate cap layer, the source/drain cap layer, and the etching barrier layer on the bottom dielectric layer; forming a top source/drain plug that runs through the source/drain cap layer and the top dielectric layer and that is in contact with the bottom source/drain plug; and forming a gate plug that runs through the gate cap layer and the top dielectric layer and that is in contact with the gate structure. Embodiments of the present disclosure help improve the performance of the semiconductor structure.