Patent ID: 11138068

Abstract:
Several embodiments of systems incorporating memory devices are disclosed herein. In one embodiment, a memory device can include a controller and a memory component operably coupled to the controller. The controller can include a memory manager, a quality metrics first in first out (FIFO) circuit, and an error correction code (ECC) decoder. In some embodiments, the ECC decoder can generate quality metrics relating to one or more codewords saved in the memory component and read into the controller. In these and other embodiments, the ECC decoder can stream the quality metrics to the quality metrics FIFO circuit, and the quality metrics FIFO circuit can stream the quality metrics to the memory manager. In some embodiments, the memory manager can save all or a subset of the quality metrics in the memory component and/or can use the quality metrics in post-processing, such as in error avoidance operations of the memory device.