Patent ID: 10684975

Abstract:
An integrated circuit comprising a plurality of one-hot-bit multiplexers interconnected to form a switch interconnect network (e.g., hierarchical and/or mesh type networks), wherein each of the plurality of one-hot-bit multiplexers includes an output, inputs, and input selects, wherein each one-hot-bit multiplexer of the plurality of one-hot-bit multiplexers are capable of receiving: (i) an input select signal to select one of the plurality of inputs, (ii) an operational input signal at a selected input during a normal operation of the switch interconnect network, and (iii) an initialization input signal at the selected input during an initialization operation. The integrated circuit further includes initialization circuitry to generate a plurality of initialization input signals in response to an initialization signal, wherein the initialization input signals have (i) an identical data state and (ii) are applied to the selected input of each of the plurality of one-hot-bit multiplexers during the initialization operation.