Patent ID: 11630603

Abstract:
A process includes, responsive to a first epoch of a sequence of epochs, a plurality of processors accessing first entries of a first buffer that is shared among the plurality of processors. The first entries identify a first subset of hardware devices to be polled of a plurality of hardware devices. Responsive to the accessing, the plurality of processors poll the first subset of hardware devices. Responsive to the first epoch, the process includes, responsive to results of the polling, the plurality of processors updating delay orders that are associated with the first subset of hardware devices; and the plurality of processors adding second entries identifying the first subset of hardware devices to a plurality of second buffers based on the delay orders, where each second buffer of the plurality of second buffers corresponds to a different delay order of the delay orders. The process includes, responsive to a condition that represents an end of the first epoch, preparing the first buffer for a second epoch of the sequence of epochs. The preparation includes, responsive to a position of the second epoch in the sequence of epochs, selecting a second subset of hardware devices of the plurality of hardware devices for the second epoch. The selection includes selecting, from the plurality of second buffers, third entries that identify the second subset of hardware devices and adding the third entries to the first buffer.