Patent ID: 10043740

Abstract:
Semiconductor packages with interconnects having passivation thereon is disclosed. The passivation layer may be any suitable dielectric material that may overlie a build-up dielectric layer and metal traces of an interconnect layer in a semiconductor package. Via holes may be formed in the build-up dielectric and the passivation layer may be removed from the bottom of the via hole. By removing the passivation layer at the bottom of the via hole, any residual build-up dielectric may also be removed from the bottom of the via hole. Thus removal of the residual build-up dielectric may not require a desmear process that would otherwise roughen metal and/or dielectric surfaces. The resulting smoother metal and/or dielectric surfaces enabled by the use of the passivation layer may allow greater process latitude and/or flexibility to fabricate relatively smaller dimensional interconnect features and/or relatively improved signaling frequency and integrity.