Patent ID: 10748862

Abstract:
A TFT substrate includes a source-gate connection section in a non-transmission and/or reception region. The source-gate connection section includes a source lower connection wiring line included in a gate metal layer, a first opening formed in a gate insulating layer and at least reaching the source lower connection wiring line, a source bus line connection section included in a source metal layer and connected to a source bus line, a second opening formed in a first insulating layer and overlapping the first opening when viewed from a normal direction of a dielectric substrate, a third opening formed in the first insulating layer and at least reaching the source bus line connection section, a first connection section including at least one conductive layer formed between the first insulating layer and the second insulating layer, connected to the source lower connection wiring line within the first opening, and connected to the source bus line connection section within the third opening, a fourth opening formed in a second insulating layer and at least reaching the first connection section, and a second connection section included in an upper conductive layer and connected to the first connection section within the fourth opening.