Patent ID: 11183835

Abstract:
A gate driver circuit is provided that includes a high-side power transistor; a low-side power transistor coupled to the high-side power transistor, where an output voltage is generated at a load node coupled between the low-side power transistor and the high-side power transistor; a gate driver configured to receive a high-side control signal and a low-side control signal, drive the high-side power transistor based on the high-side control signal, and drive the low-side power transistor based on the low-side control signal; and a short circuit detection circuit configured to monitor for short circuit events at the high-side power transistor and at the low-side power transistor based on the high-side control signal, the low-side control signal, and the output voltage, and, generate a fault signal in response to detecting a short circuit event at either of the high-side power transistor or the low-side power transistor.