Patent ID: 10833262

Abstract:
A memory device is disclosed. The memory device includes a bottom contact and a memory layer connected to the bottom contact. The memory layer has a variable resistance. The memory device also includes a top electrode on the memory layer, where the top electrode and the memory layer cooperatively form a heterojunction memory structure. The memory device also includes a top contact on the top electrode; a first barrier layer, configured to substantially prevent the conduction of ions therethrough, where the first barrier layer is between the top electrode and the top contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m; and a second barrier layer, configured to substantially prevent the conduction of ions or vacancies therethrough, where the second barrier layer is between the memory layer and the bottom contact, and where the first barrier layer has a resistivity less than 1e-4 ohm-m.