Patent ID: 10962875

Abstract:
An integrated circuit (IC) method is provided. The method includes building a mask model to simulate an aerial mask image of a mask, and a compound lithography computational (CLC) model to simulate a wafer pattern; calibrating the mask model using a measured aerial mask image of the mask; calibrating the CLC model using measured wafer data and the calibrated mask model; performing an optical proximity correction (OPC) process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication. Alternatively, the method includes measuring a mask image of a mask optically projected on a wafer with an instrument; calibrating a mask model using the measured mask image; calibrating a CLC model using measured wafer data and the calibrated mask model; and performing an OPC process to a mask pattern using the calibrated CLC model, thereby generating a corrected mask pattern for mask fabrication.