Patent ID: 11144486

Abstract:
An information handling system includes a processor with an Improved Inter-Integrated Circuit (I3C) master interface, a first device with a first I3C slave interface, and a second device with a second I3C slave interface. The first I3C slave interface provides first In-Band Interrupts (IBIs) to the I3C master interface and has a first I3C address. The second I3C interface provides second IBIs to the I3C master interface and has a second I3C address. The second I3C address is higher than the first I3C address. The processor receives the first IBI, determines that the second IBIs are masked by the first Mb due to the second I3C address being higher than the first I3C address, and assigns a third I3C address to one of the first I3C slave interface and the second I3C slave interface in response to determining that the second IBIs are masked by the first IBIs.