Patent ID: 11508754

Abstract:
A semiconductor memory structure includes a substrate, two doped regions in the substrate, a plurality of gate layers, a plurality of insulating layers, a column over the substrate, a charge-trapping layer, and a channel layer. The substrate includes dopants of a first conductivity type, and the two doped regions include dopants of a second conductivity type complementary to the first conductivity type. The gate layers and the insulating layers are alternately stacked over the substrate. The column penetrates the gate layers and the insulating layers, and includes an isolation structure, a source structure and a drain structure. at two sides of the isolation structure. The charge-trapping layer is at two sides of the column, and the channel layer is between the charge-trapping layer and the column. A bottom surface of the charge-trapping layer is in contact with the substrate and separated from the two doped regions.