Patent ID: 10691866

Abstract:
A circuit design verification method suitable for use with a 2.5D transceiver device potentially having hundreds of dice mounted on an interposer. An illustrative method includes: (a) retrieving a design of a circuit that includes multiple integrated circuit dice connected via an interposer, each die having at least one contact for receiving or transmitting a digital signal conveyed by an interchip connection of the interposer, said circuit including an IO cell for each such contact; (b) obtaining a timing model for components of said circuit, the timing model accounting for propagation delays of said IO cells and propagation delays of said interchip connections; (c) performing a static timing analysis of the design using the timing model to determine data required times and data arrival times at each of said components; (d) comparing the data required times with the data arrival times to detect timing violations; and (e) reporting said timing violations.