Patent ID: 10879953

Abstract:
An apparatus is comprised of a processor, first and second first Phase-Locked Loop Waveform Generators (PLLWGs), first and second Voltage Controlled Oscillators (VCOs), and a Radio Frequency (RF) switch. The processor generates first and second data program signals to program the first PLLWG and the second PLLWG, respectively, and generates a first and second trigger command signals instructing the first and second PLLWGs to generate first and second analog tuning signals, respectively. The first PLLWG, coupled to the processor, generates the first analog tuning signal. The second PLLWG, coupled to the processor, generates the second analog tuning signal. The first VCO, coupled to the first PLLWG, generates a first channel frequency signal. The second VCO, coupled to the second PLLWG, generates a second channel frequency signal. The RF switch selectively outputs one of a first pre-switch frequency signal and a second pre-switch frequency signal.