Patent ID: 10127876

Abstract:
A gate driving circuit includes a plurality of stages, a k-th stage (where k is a natural number) of the plurality of stages being configured to receive a clock signal, a (k−1)-th carry signal from a (k−1)-th stage of the plurality of stages, a (k+1)-th carry signal from a (k+1)-th stage of the plurality of stages, a (k+2)-th carry signal from a (k+2)-th stage of the plurality of stages, a first ground voltage, a second ground voltage, and a third ground voltage, and to output a k-th gate signal and a k-th carry signal, the k-th stage including a first pull down circuit configured to discharge the k-th gate signal as the third ground voltage in response to the (k+1)-th carry signal, and the third ground voltage having a lower voltage level than the first ground voltage and having a higher voltage level than the second ground voltage.