Patent ID: 11227933

Abstract:
A ferroelectric field effect transistor includes a semiconductor substrate that contains a semiconductor channel that extends between a source region and a drain region. A ferroelectric gate dielectric layer is disposed over the semiconductor channel, and includes a ferroelectric material having a charge trapping band including electronic states generated by interfacial traps of the ferroelectric material. A gate electrode is located on the ferroelectric gate dielectric layer, and is configured to provide an on-state and an off-state for the ferroelectric field effect transistor through application of an on-voltage and an off-voltage, respectively, from a gate bias circuit. An energy level of the charge trapping band during the on-state is offset from an energy level of minority charge carriers of the semiconductor channel. Charge trapping in the ferroelectric material is avoided during operation of the ferroelectric field effect transistor, thereby increasing the endurance of the ferroelectric field effect transistor.