Patent ID: 11768721

Abstract:
The invention provides a technology for suppressing a delay in communication between a plurality of cores that perform parallel processing. In the invention, an ECU 302 of a vehicle control system 2 includes a plurality of cores 401 and a shared memory 405. When transmitting data in the inter-core communication, a transmission side core 401-1 writes a counter value updated according to the data and a writing order to a buffer unit 901 which is determined by a counter value managed for each communication system, which is stored in each of the plurality of buffer units 901 provided in the shared memory 405. When receiving data in the inter-core communication, a reception side core 401-2 reads data from the buffer unit 901 in which the latest data for each communication system is stored, which is determined by the counter value stored in each of the plurality of buffer units 901.