Patent ID: 10991761

Abstract:
First electrically conductive lines, first pillar structures, second electrically conductive lines, second pillar structures, third electrically conductive lines, third pillar structures, fourth electrically conductive lines, and fourth pillar structures are formed over a substrate. Each pillar structure includes a memory element. Interconnection structures are formed on the first electrically conductive lines. The first electrically conductive lines may have thinned segments located outside the area of the arrays of memory elements, and the interconnection structures may be formed on the thinned segments. Alternatively or additionally, the interconnection structures may include a vertical stack of a first conductive via structure contacting a respective one of the first electrically conductive lines, a conductive pad structure, and a second conductive via structure. Fifth electrically conductive lines may be formed on top surfaces of the second two-dimensional array of memory elements and on top surface of the interconnection structures.