Patent ID: 10325861

Abstract:
Dicing a semiconductor wafer into chips may include (and structures may result from) forming a lateral chip dicing pattern of vertical metal stack kerf (MSK) structures from a depth below an upper surface of a substrate of a wafer, up through metallization layers of the wafer, to a top surface of the wafer. This dicing pattern may separate or define the perimeters/edges of the chips to be diced. A protective layer over the wafer can be etched to form a pattern of openings to the pattern of MSK structures. Then, a wet etch through the pattern of openings in the protective layer removes the MSK structures and forms lateral chip dicing trench pattern to the depth below the upper surface of the substrate along the intended lateral dicing pattern. A bottom surface of the substrate can be ground to expose the bottom of the trench pattern and dice the chips.