Patent ID: 10468269

Abstract:
Interconnect structures and processes generally include creating point defects in exposed surfaces of the dielectric layer to create a point defect region at a relatively shallow depth, wherein the point defect region is a fraction of the dielectric layer and is created with exposure to silicon, carbon, nitrogen, oxygen, or mixtures thereof such that the point defect region contains Si, C, N O, or mixtures containing at least one of the foregoing. A seed layer can be deposited and includes at least one alloying element that is effective to form an in situ self-aligned liner layer with the Si, C, N O, or mixtures containing at least one of the foregoing within the point defect region, which is formed at a depth of less than 10 nanometers. The in situ liner layer within the dielectric layer maximizes the volume fraction of the conductor of the interconnect structure.