Patent ID: 10290627

Abstract:
The present invention provides an embedded high voltage LDMOS-SCR device with strong voltage clamp and ESD robustness, which can be used as the on-chip ESD protection for high voltage IC. Wherein said the device comprises a P substrate, a P well, a N well, a first field oxide isolation region, a first P+ injection region, a second field oxide isolation region, a first N+ injection region, a first fin polysilicon gate, a second N+ injection region, a second fin polysilicon gate, a third N+ injection region, a third fin polysilicon gate, a polysilicon gate, a fourth fin polysilicon gate, a second P+ injection region, a fifth fin polysilicon gate, a third P+ injection region, a sixth fin polysilicon gate, a fourth P+ injection region, a third oxygen isolation region, a fourth N+ injection region and a fourth field oxygen isolation region. Under the influence of ESD pulse, the ESD discharge current path with LDMOS-SCR structure and the RC coupling current path with embedded PMOS interdigital structure in the drain terminal and embedded NMOS interdigital structure in the source terminal are formed, in order to enhance the ESD robustness of the device and improve the voltage clamp capability.