Patent ID: 10222818

Abstract:
A circuit including a first PMOS (p-channel metal oxide semiconductor) transistor, a first NMOS (n-channel metal oxide semiconductor) transistor, a second PMOS transistor, and a second NMOS transistor. A source, a gate, and a drain of the first PMOS transistor connect to a first node, a second node, and a third node, respectively. A source, a gate, and a drain of the first NMOS transistor connect to a fourth node, the third node, and the second node, respectively. A source, a gate, and a drain of the second PMOS transistor connect to the third node, the fourth node, and the second node, respectively. Finally, a source, a gate, and a drain of the second NMOS transistor connect to the second node, the first node, and the third node, respectively.