Patent ID: 11847450

Abstract:
Systems, methods, and apparatuses relating to instructions to multiply values of zero are described. In one embodiment, a hardware processor includes a decoder to decode a single instruction into a decoded single instruction, the single instruction having a first field that identifies a first number, a second field that identifies a second number, and a third field that indicates a number format for the first number and the second number; and an execution circuit to execute the decoded single instruction to: cause a first comparison of the first number to a zero value in the number format of the first number, cause a second comparison of the second number to a zero value in the number format of the second number, provide as a resultant of the single instruction a value of zero when the second comparison indicates the second number equals the zero value in the number format of the second number, provide as the resultant of the single instruction the value of zero when the first comparison indicates the first number equals the zero value in the number format of the first number, and provide as the resultant of the single instruction a product of a multiplication of the first number and the second number when the first comparison indicates the first number does not equal the zero value in the number format of the first number and the second comparison indicates the second number does not equal the zero value in the number format of the second number.