Patent ID: 11533044

Abstract:
An apparatus for generating multi-signaling output voltage may include at least one output buffer, wherein the at least one the output buffer may include a first PMOS transistor, a second PMOS transistor, a first NMOS transistor, a second NMOS transistor, and a Zener diode along with a switchable current source. The apparatus may further include first logic circuitry, second logic circuitry, first voltage down level shifter circuitry, second voltage down level shifter circuitry, and a first voltage up level shifter circuitry. Outputs of the first voltage down level shifter circuitry, the second voltage down level shifter circuitry, and the first voltage up level shifter circuitry are combined using the output buffer to generate the desired output. The second NMOS transistor acts as isolation transistor for reducing and/or preventing diode current between a first supply voltage and the third supply voltage.