Patent ID: 10446645

Abstract:
A semiconductor device 1 includes: a well region 5 provided on a surface layer of a semiconductor substrate 2; a source region 14S and a drain region 15D disposed to be distant from each other on the surface layer of the well region 5; a channel region 6 provided between the source region 14S and the drain region 15D; and a gate electrode 8 provided over the channel region 6 with a gate insulator 7 interposed therebetween. A gate length of the gate electrode 8 is 1.5 μm or less, the channel region 6 includes indium as a channel impurity, a distance between a surface of the channel region 6 and a concentration peak position of the channel impurity is 20 nm to 70 nm, and a concentration of the channel impurity gradually decreases in a direction from the concentration peak position of the channel impurity to the surface of the channel region.