Patent ID: 11699496

Abstract:
An anti-fuse memory circuit includes: a memory array including multiple anti-fuse memory cells; bit lines, each connected to the anti-fuse memory cells arranged in extension direction of the bit line, each anti-fuse memory cell being electrically connected to respective one of bit lines through first switch transistor; word lines, each connected to first switch transistors arranged in extension direction of word line; a second switch transistor connects one of the bit lines to transmission wire; a reading circuit, having first input terminal connected to the transmission wire, second input terminal for receiving reference voltage, and sampling input terminal for receiving sampling signal; and a signal generation circuit for generating sampling signal according to precharge voltage and precharge signal, where precharge signal is used for instructing to precharge transmission wire to precharge voltage, and delay duration between sampling signal and precharge signal is positively correlated with voltage amplitude of precharge voltage.