Patent ID: 11664813

Abstract:
A delay circuit includes a state transition section configured to start state transition based on a trigger signal and output state information indicating the internal state and a transition-state acquisition section configured to latch and hold the state information. The state transition section includes a tapped delay line in which a plurality of delay elements are coupled, a logical circuit configured to generate a third signal based on a first signal based on the trigger signal and a second signal, which is an output signal of the delay element, and a synchronous transition section configured to count an edge of the third signal. The state information is having an output signal of the synchronous transition section and an output signal of the tapped delay line. A humming distance of the state information before and after the state transition is 1. A time from when the internal state transitions from a first internal state to a second internal state until when the internal state transitions to the first internal state again is longer than an interval of a time for updating the state information held by the transition-state acquisition section.