Patent ID: 10886899

Abstract:
Provided is a low-power-consumption Constant-On-Time (COT) timing circuit design method and a timing circuit. A Resistor-Capacitor (RC) circuit is adopted for timing, to eliminate static power consumption of a timer. A specific structure includes a fourth P-channel Metal Oxide Semiconductor (MOS) transistor M4 of which a source is connected to an input voltage VIN, a gate is connected to a COT control terminal TON_CONTROL and a drain is connected with one end of a fourth resistor R4. The other end of the fourth resistor R4 is connected with one end of a fourth capacitor C4. The other end of the fourth capacitor C4 is grounded. A negative input of a comparator VCMP is connected with a reference voltage, and a positive input is connected between the fourth capacitor C4 and the fourth resistor R4.