Patent ID: 11269806

Abstract:
A time deterministic computer is architected so that exchange code compiled for one set of tiles, e.g., a column, can be reused on other sets. The computer comprises: a plurality of processing units each having an input interface with a set of input wires, and an output interface with a set of output wires; a switching fabric connected to each of the processing units by the respective set of output wires and connectable to each of the processing units by the respective set of output wires and connectable to each of the processing units by the respective input wires via switching circuitry controllable by its associated processing unit; the processing units arranged in columns, each column having a base processing unit proximate the switching fabric and multiple processing units one adjacent the other in respective positions in the direction of the column, wherein to implement exchange of data between the processing units at least one processing unit is configured to transmit at a transmit time a data packet intended for a recipient processing unit onto its output set of connection wires, the data packet having no destination identifier of the recipient processing unit but destined for receipt at the recipient processing unit with a predetermined delay relative to the transmit time, wherein the predetermined delay is dependent on an exchange pathway between the transmitting and recipient processing units, wherein the exchange pathway between any pair of transmitting and recipient processing unit at respective positions in one column has the same delay as the exchange pathway between each pair of transmitting and recipient processing units at corresponding respective positions in the other columns.