Patent ID: 10186614

Abstract:
A semiconductor device in which parasitic capacitance is reduced is provided.A semiconductor device comprising a first insulating layer, a first oxide semiconductor layer over the first insulating layer, a second oxide semiconductor layer over the first oxide semiconductor layer, a source electrode layer and a drain electrode layer over the second oxide semiconductor layer, a second insulating layer over the first insulating layer, the source electrode layer, and the drain electrode layer, a third insulating layer over the second insulating layer, a third oxide semiconductor layer over the second oxide semiconductor layer, a gate insulating layer over the third oxide semiconductor, and a gate electrode layer over the gate insulating layer. The second insulating layer is an oxygen barrier layer and includes a region in contact with side surfaces of the first oxide semiconductor layer, the second oxide semiconductor layer, the source electrode layer, and the drain electrode layer. The third oxide semiconductor layer includes a region in contact with side surfaces of the second oxide semiconductor layer, the source electrode layer, the drain electrode layer, the second insulating layer, and the third insulating layer.