Patent ID: 10503859

Abstract:
A computer-implemented method of generating a layout of a circuit block of an integrated circuit comprises: receiving input data defining a logical operation of the circuit block; accessing a cell library providing a plurality of candidate cells; determining, with reference to the input data, a set of cells to be used to implement the circuit block, the cells defining circuit elements for fabrication on a substrate; and generating the layout by employing a place and route tool to determine a placement of the set of cells and performing a routing operation to interconnect interface terminals of the set of cells by determining routing paths to be provided within a plurality of metal layers including a lowest metal layer overlying the cells and within which interface terminals of the cells are provided and one or more further metal layers overlying the lowest metal layer; in which the step of determining routing paths comprises determining a routing path between interface terminals of a group of two or more cells by providing, in the generated layout, (i) an interconnection overlying the interface terminals of the group of two or more cells in one of the one or more further metal layers and (ii) via connections between the interconnection and the interface terminals of the group of two or more cells.