Patent ID: 11899608

Abstract:
A method and/or process of interface bridging device for providing a C physical layer (“C-PHY”) input output interface via a field programmable gate arrays (“FPGA”) is disclosed. The process, in one aspect, is capable of coupling a first wire of data lane 0 to a first terminal of first IO serializer of FPGA for receiving first data from a D-PHY transmitter of a first device and coupling a second wire of the data lane 0 to a second terminal of the first IO serializer of FPGA for receiving second data from the D-PHY transmitter. Upon activating a first scalable low-voltage signal to generate a first value on P channel and a second value on N channel in response to the first data and the second data, a first signal on first wire of trio 0 for a C-PHY output is generated based on the first value on the P channel.