Patent ID: 11239765

Abstract:
A multi-level circuit, a three-phase multi-level circuit, and a control method are provided. The multi-level circuit includes two groups of bus capacitors (C1 and C2) that are connected in series; a plurality of switching transistor branches that are connected in parallel to the capacitors, where each switching transistor branch includes a first half bridge (Q1 and Q2) and a second half bridge (Q3 and Q4), and a common terminal of the two half bridges is grounded (N); and two negative coupled inductors (L1 and L2), where each input terminal of each negative coupled inductor is connected to a common terminal (A1 and A2) of two switching transistors in the first half bridge in only one of the switching transistor branches. In this circuit, a quantity of groups of bus capacitors is decreased and circuit design complexity is reduced. Further, a dropout voltage of the switching transistors is reduced.