Patent ID: 11048845

Abstract:
An FPGA chip-based handler simulation test system is provided. The FPGA chip-based handler simulation test system includes a handler simulator, a PC and a tester. The handler simulator includes an FPGA, an RS232 interface, a GPIB interface, a RAM, a LED, a keypad and a soft-core processor. The soft-core processor includes a CPU, an SDRAM, a PIO, a UART and a JTAG. The firmware of the soft-core processor establishes the communication of the RS232 interface and the GPIB interface, as well as the display of the LED and reception of the keypad. The test system of the present invention simulates handler communication by using a small-sized and low-cost hardware circuit, and is easy to carry. In this way, an operator can debug the handler in the laboratory without damaging the handler, thus protecting the expensive handler.