Patent ID: 10169240

Abstract:
Systems and methods for managing memory access bandwidth include a spatial locality predictor. The spatial locality predictor includes a memory region table with prediction counters associated with memory regions of a memory. When cache lines are evicted from a cache, the sizes of the cache lines which were accessed by a processor are used for updating the prediction counters. Depending on values of the prediction counters, the sizes of cache lines which are likely to be used by the processor are predicted for the corresponding memory regions. Correspondingly, the memory access bandwidth between the processor and the memory may be reduced to fetch a smaller size data (e.g., half cache line) than a full cache line if the size of the cache line likely to be used is predicted to be less than that of the full cache line. Prediction counters may be incremented or decremented by different amounts depending on access bits corresponding to portions of a cache line. Mispredictions may be tracked and adjusting of the memory bandwidth may be flexibly enabled or disabled. A global prediction counter may also be used.