Patent ID: 11107918

Abstract:
A semiconductor structure is provided. The semiconductor structure includes a semiconductor substrate, an N-type well region over the semiconductor substrate, a FDSOI transistor formed over the N-type well region, a first shallow trench isolation (STI) region over the N-type well region, a first N-type doped region over the N-type well region, a second STI region over the semiconductor substrate, a first P-type doped region over the semiconductor substrate, and a first interconnection element over the first P-type doped region. The first P-type doped region is separated from the first N-type doped region by the second STI region. The first interconnection element is configured to connect the first P-type doped region to a ground. No interconnection element is formed over the first N-type doped region so that the first N-type doped region and the N-type well region are floating.