Patent ID: 10811329

Abstract:
The present invention relates to a ceramic substrate (100) comprising: a front side (100-1), which comprises: i) a power semiconductor (102-1, . . . , 102-n); and ii) a first metallic layer (104) comprising at least one first metallic plane contact (104-1, . . . , 104-n), which is configured to connect the power semiconductor (102-1, . . . , 102-n) to a first terminal (105-1, . . . , 105-n) on an edge (100-3) of the ceramic substrate (100); a back side (100-2), which comprises: i) a capacitor (103) which is attached to a ii) second metallic layer (108) comprising at least one second metallic plane contact (108-1, . . . , 108-n), which is configured to connect the capacitor (103) to a second terminal (107-1, . . . , 107-n) on the edge (100-3) of the ceramic substrate (100); and a metallic frame (110), which is configured to connect the first metallic layer (104) to the second metallic layer (108).