Patent ID: 11366603

Abstract:
The invention provides a storage structure and an erase method thereof, capable of performing an erase operation on a plurality of memory blocks. The storage structure includes: a first storage body, a second storage body, a third storage body, and a controller. Memory blocks that are consecutively numbered are sequentially alternately stored in the first memory bank, the second memory bank, and the third memory bank, and the controller is configured to control each memory block to sequentially undergo a first process, a second process and a third process. The erase method includes: when a memory block Bi undergoes the third process, a memory block Bi+1 undergoes the second process, and a memory block Bi+2 undergoes the first process at the same time; where i ∈ [1, n−2]. Three adjacent blocks undergo the first process, the second process, and the third process simultaneously.