Patent ID: 11527539

Abstract:
A semiconductor structure includes an SRAM cell that includes first and second pull-up (PU) transistors, first and second pull-down (PD) transistors, first and second pass-gate (PG) transistors, and bit line (BL) conductors. The first PU and the first PD transistors form a first inverter. The second PU and the second PD transistors form a second inverter. The first and the second inverters are cross-coupled to form two storage nodes that are coupled to the BL conductors through the first and the second PG transistors. The first and the second PU transistors are formed over an n-type active region over a frontside of the semiconductor structure. The first and the second PD transistors and the first and the second PG transistors are formed over a p-type active region over the frontside of the semiconductor structure. The BL conductors are disposed over a backside of the semiconductor structure.