Patent ID: 11201159

Abstract:
A semiconductor structure includes SRAM cells, bit-line edge cells, and word-line edge cells, wherein the SRAM cells are arranged in an array, bordered by the bit-line edge cells and the word-line edge cells, each of the SRAM cells including two inverters cross-coupled together and a pass gate coupled to the two inverters, and the pass gate includes a FET; a first bit-line of a first metal material, disposed in a first metal layer, and electrically connected to a drain feature of the FET; a first word-line of a second metal material, and electrically connected to a gate electrode of the FET, and disposed in a second metal layer; and a second bit-line of a third metal material, electrically connected to the first bit-line, and disposed in a third metal layer. The first metal material and the third metal material are different from each other in composition.