Patent ID: 10643013

Abstract:
A tie-high circuit includes: a p-type metal-oxide-semiconductor (PMOS) transistor connected to a power rail in a standard cell library; and a decoupling capacitor connected to a ground rail in the standard cell library and the PMOS transistor. The decoupling capacitor includes an n-type metal-oxide-semiconductor (NMOS) transistor having either one of a source and a drain of the NMOS transistor being connected to the ground rail via an active resistor. A tie-low circuit includes: an n-type metal-oxide-semiconductor (NMOS) transistor connected to a ground rail in a standard cell library; and a decoupling capacitor connected to a power rail in the standard cell library and the NMOS transistor. The decoupling capacitor of the tie-low circuit includes a PMOS transistor having either one of a source and a drain of the PMOS transistor being connected to the power rail via an active resistor.