Patent ID: 11392378

Abstract:
Circuitry comprises an instruction decoder to decode a gather load instruction having a vector operand comprising a plurality of vector entries, in which each vector entry defines, at least in part, a respective address from which data is to be loaded; the instruction decoder being configured to generate a set of load operations relating to respective individual addresses in dependence upon the vector operand, each of the set of load operations having a respective identifier which is unique with respect to other load operations in the set, and control circuitry to maintain a data item for the gather load instruction, the data item including a count value representing a number of load operations in the set of load operations awaiting issue for execution; and execution circuitry to execute the set of load operations; the control circuitry being configured, in response to a detection from the count value of the data item associated with a given gather load instruction that the set of load operations generated for the given gather load instruction has reached a predetermined stage relative to execution of all of that set of load operations, to control handling of a consumer instruction, being an instruction which depends upon the completion of the given gather load instruction.