Patent ID: 10811414

Abstract:
Semiconductor structures and fabrication methods are provided. An exemplary fabrication method includes providing a base substrate including a plurality of fins on a semiconductor substrate; forming a gate layer across the fins; forming a P-type doped epitaxial layer in the fins at both sides of the gate layer in a PMOS region of the semiconductor substrate; forming an N-region mask layer on top and sidewall surfaces of the fins in the NMOS region and covering the P-type doped epitaxial layer; forming an N-region trench; forming an N-type doped epitaxial layer by filling the N-region trench; forming an interlayer dielectric layer over the semiconductor substrate; forming a contact opening to expose the P-type doped epitaxial layer and the N-type doped epitaxial layer; and performing an N-type dopant segregated Schottky (DSS) doping process on a portion of the N-type doped epitaxial layer exposed by the contact opening.