Patent ID: 11442712

Abstract:
A method, apparatus and system required to realize an optimization opportunity are disclosed. If an expression involves unsequenced evaluations involving side-effects and optionally references, then the expression is translated into optimized code that may involve optimized register usage, or optimized use of the underlying vectorization hardware. An alias-analysis logic is able to identify must-not-alias relationships through such expression tree structures. These must-not-alias relationships are helpful not just in optimizing the performance of that particular expression (from which these must-not-alias relationships were derived) but also in the performance of any other surrounding program statements that access the state elements participating in these must-not-alias relationships. More specifically, if the order of evaluation is unspecified and the sub expressions generate side effects, then must-not-alias relationships are inferred between expressions which can be used while optimizing surrounding code, such as the instructions following this expression with unsequenced evaluation.