Patent ID: 11199455

Abstract:
A wafer-level integrated thermal detector comprises a first wafer and a second wafer (W1, W2) bonded together. The first wafer (W1) includes a dielectric or semiconducting substrate (100), a dielectric sacrificial layer (102) deposited on the substrate, a support layer (104) deposited on the sacrificial layer or the substrate, a suspended active element (108) provided within an opening (106) in the support layer, a first vacuum-sealed cavity (110) and a second vacuum-sealed cavity (106) on opposite sides of the suspended active element. The first vacuum-sealed cavity (110) extends into the sacrificial layer (102) at the location of the suspended active element (108). The second vacuum-sealed cavity (106) comprises the opening of the support layer (104) closed by the bonded second wafer. The thermal detector further comprises front optics (120) for entrance of radiation from outside into one of the first and second vacuum-sealed cavities, aback reflector (112) arranged to reflect radiation back into the other one of the first and second vacuum-sealed cavities, and electrical connections (114) for connecting the suspended active element to a readout circuit (118).