Patent ID: 10069004

Abstract:
A semiconductor device of an embodiment includes a p+-type region selectively disposed in a surface of an n-type silicon carbide epitaxial layer disposed on an n+-type silicon carbide substrate, an element structure that includes a source electrode and a p+-type region that form a metal-semiconductor junction on the n-type silicon carbide epitaxial layer, a p−-type region and another p−-type region that surround the periphery of the element structure, and an n+-type channel stopper region that surrounds the periphery of the p−-type regions so that the n-type silicon carbide epitaxial layer is therebetween. The n+-type channel stopper region has a second n+-type channel stopper region whose impurity concentration is high, and a first n+-type channel stopper region that encompasses the second n+-type channel stopper region and whose impurity concentration is lower than that of the second n+-type channel stopper region.