Patent ID: 10963608

Abstract:
A computer implemented method of passive verification of an electronic design, includes the steps of receiving a first electronic design file of a first electronic design comprised at least in part of a mixed signal or analog system, the first electronic design file including at least one first system and first subsystem, collecting first input data from at least one first system input and first subsystem input, analyzing a first parameter of the first input data, receiving a second electronic design file of a second electronic design comprised at least in part of a mixed signal or analog system, the second electronic design file including at least one second system and second subsystem that are comparable in function to the at least one first system and first subsystem of the first electronic design file, collecting second input data from at least one second system input and second subsystem input of the second design file, analyzing the first parameter of the second input data, comparing the analysis of the first parameter of the first input data of the at least one first system and first subsystem in said first design file to the analysis of the first input parameter of the second input data of the least one second system and second subsystem in the second design file and repeating the comparison for a series of input parameters to build a history of verification coverage of input parameters of the at least one second system and second subsystem of the second design file relative to the at least one first system and first subsystem of the first design file.