Patent ID: 10056393

Abstract:
Integrated devices comprising pinched hysteresis loop (PHL) materials in a capacitor or a transistor stack are disclosed. PHL materials include field induced ferroelectrics (FFE), anti-ferroelectric (AFE) and relaxor type ferroelectric (RFE) materials. Each integrated device includes a material stack with a PHL material layer disposed between two electrodes. Application of this material is dependent on inducing of an electric field bias over the stack. According to one option, electrodes having different workfunction values can be employed to induce the required built-in bias field and enable use of PHL materials. According to another option, a PHL material and charges, e.g., a charge interlayer, are disposed between two electrodes such that an induced built-in bias field appears. Integrated devices employing the PHL material stack include memories, transistors, and piezo- and pyroelectric devices.