Patent ID: 11222396

Abstract:
In one embodiment, an apparatus, coupled to a computing system, may include a first-level of data bus comprising first-level data lines. The apparatus may include second-level data buses each including second-level data lines. Each second-level data bus may be coupled to a memory unit. The second-level data lines of each second-level data bus may correspond to a subset of the first-level data lines. The apparatus may include third-level data buses each including third-level data lines. Each third-level data bus may be coupled to a sub-level memory unit. The third-level data lines of each third-level data bus may correspond to a subset of the second-level data lines of a second-level data bus along a structural hierarchy. The apparatus may be configured to allow the computing system to load a data block from the first-level data lines to sub-level memory units through the third-level data buses excluding multiplexing operations.