Patent ID: 10158375

Abstract:
A decimation filter including a Hadamard-Walsh transform circuit, a comparator, and an inverse Hadamard-Walsh transform circuit. The Hadamard-Walsh transform circuit includes an input receiving a pulse density modulation bitstream and an output providing a stream of digital samples. The comparator replaces each digital sample that has a magnitude below a predetermined threshold value with a zero value and provides adjusted digital samples. The inverse Hadamard-Walsh transform circuit has an input receiving the adjusted digital samples and has an output providing pulse code modulation data values. The decimation filter may further include a down-sampler that down samples the adjusted digital samples by before being provided to the inverse Hadamard-Walsh transform circuit. The decimation filter may include a low pass filter and another down-sampler at the output. The Hadamard-Walsh transform circuits may be implemented according to the fast Hadamard-Walsh transform so that only digital additions and subtractions are performed.