Patent ID: 10497724

Abstract:
The disclosure provides a manufacturing method for a thin film transistor, wherein a manufacturing method for a data line and a source/drain specifically includes: S21: respectively manufacturing a data line material film layer and a source/drain material film layer; S22: manufacturing a photoresist material film layer; S23: performing a half-tone method to etch the photoresist material film layer, forming a photoresist layer, and obtaining a first etching substrate; S24: performing a 4-mask process to etch the first substrate, forming the data line on a gate insulating layer, forming the source and the drain on an active layer, and forming a the back channel between the source and the drain to obtain the thin film transistor. The disclosure further provides a manufacturing method for an array substrate, wherein the manufacturing method for an array substrate includes the above-mentioned manufacturing method for a thin film transistor.