Patent ID: 11811401

Abstract:
A method for operating an integrated circuit chip including multiple tiles (202a-202d) includes determining a configuration for the tiles for execution of a computation. When the configuration for the tiles satisfies a first criterion, the integrated circuit is operated in a first mode, including concurrently receiving respective input data (208a, 208b) at each of the tiles (202a-202d). When the configuration for the tiles satisfies a second criterion, the integrated circuit is operated in a second mode, including: at a first time, concurrently receiving respective first input data (208a, 208b) at each tile (202a, 202b) of a first group of tiles; at the first time, storing respective second input data (208a, 208b) in each of multiple delay registers (212a, 212b), each delay register corresponding to a tile (202c, 202d) of a second group of tiles; at a second time, releasing the second input data from the delay registers (212a, 212b) and receiving the released respective second input data at each tile (202c, 202d) of the second group of tiles.