Patent ID: 11374573

Abstract:
The present disclosure provides a subthreshold ratioed logic circuit and a chip. The subthreshold ratioed logic circuit comprises a pull-up module, a voltage regulation module, a pull-up PMOS transistor and a pull-down module that is turned on or off corresponding to the pull-up module; the first end of the pull-up module is connected to an external circuit, the second end of the pull-up module is connected to the source of the pull-up PMOS transistor, and a power supply, the third end of the pull-up module is connected to the second end of the voltage regulation module; the first end of the voltage regulation module is connected with a compensation adjustment circuit, and the third end of the voltage regulation module is grounded; the drain of the pull-up PMOS transistor connected to the output of the subthreshold ratioed logic circuit.