Patent ID: 11139283

Abstract:
A microelectronic package may include a substrate having first and second surfaces each extending in first and second directions, a NAND wafer having a memory storage array, a bitline driver chiplet configured to function as a bitline driver, and a wordline driver chiplet configured to function as a wordline driver. The NAND wafer may be coupled to the first surface of the substrate, and the bitline and wordline driver chiplets may each be mounted to a front surface of the NAND wafer. The NAND wafer may have element contacts electrically connected with conductive structure of the substrate. The bitline and wordline driver chiplets may be elongated along the first and second directions, respectively. Front surfaces of the bitline driver chiplet and the wordline driver chiplet may be arranged in a single common plane and may be entirely contained within an outer periphery of the front surface of the NAND wafer.