Patent ID: 11276749

Abstract:
High density integrated circuit (IC) capacitor structures and fabrication methods that increase the capacitive density of integrated capacitors with little or no reduction in Q-factor by using a stacked high-density integrated capacitor structure that includes substrate-contact (“S-contact”) capacitor plates. Embodiments include a plurality of S-contact plates fabricated in electrical connection with a capacitor formed in a metal interconnect layer. Some embodiments include interstitial S-contact plates to provide additional capacitive density. Embodiments may also utilize single-layer transfer (SLT) and double-layer transfer (DLT) techniques to create ICs with high density, high Q-factor capacitors. Such capacitors can be beneficially combined with other structures made possible in SLT and DLT IC structures, such as metal interconnect layer capacitors and inductors, and one or more FETs having a conductive aligned supplemental gate. Embodiments are compatible with fabrication of CMOS SOI transistors, and are particularly suitable for radio frequency and analog applications.