Patent ID: 10649907

Abstract:
An apparatus is provided having processing circuitry for executing multiple items of supervised software under the control of a supervising element, and a set associative address translation cache having a plurality of entries, where each entry stores address translation data used when converting a virtual address into a corresponding physical address of a memory system comprising multiple pages. The address translation data is obtained by a multi-stage address translation process comprising a first stage translation process managed by an item of supervised software and a second stage translation process managed by the supervising element. Allocation circuitry is responsive to receipt of obtained address translation data for a specified virtual address, to allocate the obtained address translation data into an entry of a selected set of the address translation cache, where the selected set is identified using a subset of bits of the specified virtual address chosen in dependence on a final page size associated with the obtained address translation data. Filter circuitry is provided having a plurality of filter entries, and is responsive to detecting that a splinter condition exists for the obtained address translation data, to indicate in a chosen filter entry that the splinter condition has been detected for the specified item of supervised software that is associated with the obtained address translation data. The splinter condition exists when a first stage page size used in the multi-stage translation process exceeds the final page size. Maintenance circuitry is then responsive to a page invalidate request associated with an item of supervised software, to reference the filter circuitry to determine which entries of the address translation cache need to be checked in order to process the page invalidate request, in dependence on whether a filter entry of the filter circuitry indicates presence of the splinter condition for that item of supervised software.