Patent ID: 10177041

Abstract:
Disclosed are method embodiments for forming an integrated circuit (IC) structure with at least one first-type FINFET and at least one second-type FINFET, wherein the first-type FINFET has a first replacement metal gate (RMG) adjacent to a first semiconductor fin, the second-type FINFET has a second RMG adjacent to a second semiconductor fin, and the first RMG is in end-to-end alignment with the second RMG and physically and electrically isolated from the second RMG by a dielectric column. The method embodiments minimize the risk of the occurrence defects within the RMGs by forming the dielectric column during formation of the first and second RMGs and, particularly, after deposition and anneal of a gate dielectric layer for the first and second RMGs, but before deposition of at least one of multiple work function metal layers. Also disclosed herein are IC structure embodiments formed according to the above-described method embodiments.