Patent ID: 11411394

Abstract:
A voltage clamping circuit for protecting an internal circuitry comprising an input means for receiving Vin; a p-channel clamping transistor (PCT) coupled to input means for clamping Vin to prevent Vin from falling below a p-channel biasing voltage VbiasP; an n-channel clamping transistor (NCT) coupled to input means for clamping Vin to prevent Vin from rising above an n-channel biasing voltage VbiasN; and a plurality of output means for providing a first output voltage from PCT and a second output voltage from NCT; a p-channel bias circuit including a first, a second and a third bias transistor with each transistor possessing a threshold voltage Vth for providing a p-channel bias voltage to turn on PCT; and an n-channel bias circuit including a fourth, a fifth and a sixth bias transistor with each transistor possessing the threshold voltage Vth for providing an n-channel bias voltage to turn on NCT.