Patent ID: 10128829

Abstract:
Provided is a composite semiconductor device that has a low on-resistance and a high load-short-circuit resistance. In a composite semiconductor device (10) including a normally-on first FET (Q1) and a normally-off second FET (Q2) that are cascode-connected to each other. In a case where a voltage applied to a drain of the first FET (Q1) is 400 V, a relation of the following expression is satisfied: where a time elapsed after short circuit T represents a time elapsed after a time at which a load connected to the composite semiconductor device (10) starts to be short-circuited, RonQ2 represents a value of an on-resistance of the second FET, VTHQ1 represents a threshold voltage of the first FET, Idmax1 represents a drain current of the first FET in a saturated state of the first FET when a gate voltage of the first FET is 0 V, and Idmax represents a drain current limited to an extent that breakdown of the first FET is prevented for the time elapsed after short circuit T of at least 2 μsec.