Patent ID: 11158636

Abstract:
A semiconductor device includes a nanosheet device and a gate-all-around FIN-shaped (GAA-FIN) device. The nanosheet device includes n- and p-type field effect transistor (nFET and pFET) sections, each of which includes nanosheet stacks and work function metal (WFM). Each nanosheet stack includes lowermost and uppermost spacers, intermediate semiconductor layers and dielectric material surrounding the lowermost and uppermost spacers and the intermediate semiconductor layers. The WFM surrounds the nanosheet stacks and entirely fills suspension regions thereof. The GAA-FIN device includes nFET and pFET sections, each of which includes fin elements and WFM. Each fin element includes a lower spacer, a secondary intermediate layer of semiconductor material and dielectric material surrounding the lower spacer and the secondary intermediate layer of semiconductor material. The WFM surrounds each of the fin elements. A thickness of the WFM entirely filling the suspension regions exceeds a thickness of the WFM of the fin elements.