Patent ID: 11971641

Abstract:
An active matrix substrate includes a first TFT disposed in each of pixel regions, a first flattened layer covering the first TFT, and a pixel electrode provided on the first flattened layer. The first TFT includes a lower gate electrode, a lower gate insulating layer, an oxide semiconductor layer, an upper gate insulating layer, and an upper gate electrode. The active matrix substrate further includes a first connection electrode for electrically connecting a drain contact region of the oxide semiconductor layer and the pixel electrode. The first flattened layer includes a pixel contact hole formed so as to expose a part of the first connection electrode. The bottom face of the pixel contact hole at least partially overlaps, of a lower gate metal layer including a lower gate electrode and an upper gate metal layer including an upper gate electrode, at least the lower gate metal layer when viewed from the normal direction of the substrate. The first connection electrode is formed from a transparent conductive material.