Patent ID: 10482826

Abstract:
The present disclosure relates to a GOA driving circuit including N number of cascaded GOA units, wherein N is a natural number not smaller than four. The GOA unit at the i-th level includes a first controllable transistor (T1), a second controllable transistor (T2), a third controllable transistor (T3), a first capacitor (C1), and a first pull-down maintain unit, wherein 1≤i≤a and “a” is a natural number smaller than or equal to N/2. The GOA unit at the j-th level includes a fourth controllable transistor (T4), a fifth controllable transistor (T5), a second capacitor (C2), and a second pull-down maintain unit 20, wherein a+1≤j≤N. The GOA driving circuit may reduce the line buffer so as to reduce the cost of the GOA driving circuit.