Patent ID: 10090232

Abstract:
A bumpless fan-out chip stacking structure includes a first die disposed on the substrate, a first dielectric layer conformally covering on the first die, a first RDL disposed on the first dielectric layer, a first via plug electrically connecting the first die to the first RDL, a first capping layer conformally covering on the first RDL, a second die attached on the first capping layer, a second dielectric layer conformally covering on the second die, a second RDL disposed on the second dielectric layer, a second via plug electrically connecting the second die to the second RDL, a second capping layer conformally covering on the second RDL, a patterned conductive layer disposed on the second capping layer and an interlayer connection structure electrically connecting the patterned conductive layer to the first RDL and the second RDL respectively.