Patent ID: 11948978

Abstract:
Field-effect transistors (FETs) employing edge transistor current leakage suppression to reduce FET current leakage, and related methods, are disclosed. The FET includes a gate that includes extended-length edge gate regions overlapping semiconductor layer edges to form extended length edge conduction channels in edge transistors. In this manner, the threshold voltage of the edges transistors is increased, thus reducing current leakage of the edges transistors and overall current leakage of the FET. In another aspect, a body connection implant that is formed to short a source or drain region to a body of the FET is extended in length to form body connection implant regions underneath at least a portion of the edge gate regions. In this manner, the work functions of the edge gate regions are increased in voltage thus increasing the threshold voltage of the edge transistors and reducing current leakage of the edges transistors and the FET.