Patent ID: 10825736

Abstract:
A method is presented for attaining different gate threshold voltages across a plurality of field effect transistor (FET) devices without patterning between nanosheet channels. The method includes forming a first set of nanosheet stacks having a first intersheet spacing, forming a second set of nanosheet stacks having a second intersheet spacing, where the first intersheet spacing is greater than the second intersheet spacing, depositing a high-k (HK) layer within the first and second nanosheet stacks, depositing a material stack that, when annealed, creates an amorphous HK layer in the first set of nanosheet stacks and a crystallized HK layer in the second nanosheet stacks, depositing a dipole material, and selectively diffusing the dipole material into the amorphous HK layer of the first set of nanosheet stacks to provide the different gate threshold voltages for the plurality of FET devices.