Patent ID: 10996271

Abstract:
An IC includes testing circuitry including a Test Access Port (TAP) controller and Segment-Insertion-Bit circuits (SIBs) arranged in multiple hierarchy levels. Some of the SIBs are connected to hardware units, and some of the SIBs are root-SIBs that connect between neighbor hierarchy levels. A test bus runs in a daisy-chained loop path starting at the TAP controller, passing via at least some of the SIBs and ending at the TAP controller. Each root-SIB has an Open state and a Closed state. The TAP controller, for a selected subset of the hardware units that are to be tested, selects one or more root-SIBs that, when set to the Open state, make the selected subset of hardware units reachable by the test bus, and sends via the daisy-chained test bus a data stream comprising one or more instructions that set two or more of the selected root-SIBs to the Open state.