Patent ID: 10826490

Abstract:
A switch circuit includes FETs including a first FET group including m FETs, a second FET group including n FETs at a position away from the input terminal than the first FET group, and an intermediate FET between the first FET group and the second FET group, and capacitive elements including m capacitive elements, n capacitive elements, and an intermediate capacitive element, the capacitive element (C1i) (i is an integer between 1 and m inclusive) is connected in parallel to i consecutive FETs of the first FET group starting from a top closer to the input terminal, the capacitive element (C2j) (j is an integer between 1 and n inclusive) is connected in parallel to j consecutive FETs of the second FET group starting from a top closer to the input terminal, and the intermediate capacitive element is connected in parallel to the intermediate FET.