Patent ID: 11979145

Abstract:
A disclosed structure includes a section (e.g., an always on (AON) section) with at least one N-channel transistor (NFET) and at least one P-channel transistor (PFET). The structure further includes a switch with first and second inputs connected to receive positive and negative bias voltages, respectively, and first and second outputs connected to bias back gates of the NFET(s) and PFET(s), respectively, of the section. The structure is also configured to generate select signals for controlling the input-to-output connections established by the switch. In a power saving mode, these signals cause the switch to establish input-to-output connections resulting only in reverse back biasing of the NFET(s) and PFET(s) of the section. In a functional mode, these signals can cause the switch to establish input-to-output connections resulting in either forward back biasing or reverse back biasing. Also disclosed is a method of operating the structure.