Patent ID: 10014893

Abstract:
A receiver circuit comprising a beamformer and an MRC-block. The beamformer configured to: apply combination-weighting-values to a first-BF-input-signal and a second-BF-input-signal in order to provide a BF-combination-signal; and apply suppression-weighting-values to the first-BF-input-signal and the second-BF-input-signal in order to provide a BF-suppression-signal. The MRC-block comprising: a first-demodulator configured to demodulate the BF-combination-signal in order to provide a demodulated-combination-signal that comprises bit metrics; a second-demodulator configured to demodulate the BF-suppression-signal in order to provide a demodulated-suppression-signal that comprises bit metrics; and a combiner configured to combine the demodulated-combination-signal with the demodulated-suppression-signal in order to provide an MRC-output-signal.