Patent ID: 10892029

Abstract:
A processing device in a memory system identifies a first range of a plurality of write-to-read delay ranges for the memory component, wherein the first range represents a plurality of write-to-read delay times and has an associated read voltage level used to perform a read operation on a segment of the memory component having a write-to-read delay time that falls within the first range. The processing device further identifies a first set of the plurality of write-to-read delay times at a first end of the first range and determines a first directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times and a second directional error rate for the memory component corresponding to the first set of the plurality of write-to-read delay times. The processing device determines whether a correspondence between the first directional error rate and the second directional error rate satisfies a first threshold criterion and, responsive to the correspondence between the first directional error rate and the second directional error rate not satisfying the first threshold criterion, modifies the read voltage level associated with the first range.