Patent ID: 11257823

Abstract:
The disclosed technology generally relates to semiconductor devices, and more particularly to a static random access memory (SRAM) having vertical channel transistors and methods of forming the same. In an aspect, a semiconductor device includes a semiconductor substrate and a semiconductor bottom electrode region formed on the substrate and including a first region, a second region and a third region arranged side-by-side. The second region is arranged between the first and the third regions. A first vertical channel transistor, a second vertical channel transistor and a third vertical channel transistor are arranged on the first region, the second region and the third region, respectively. The first, second and third regions are doped such that a first p-n junction is formed between the first and the second regions and a second p-n junction is formed between the second and third regions. A connection region is formed in the bottom electrode region underneath the first, second and third regions, wherein the connection region and the first and third regions are doped with a dopant of a same type. A resistance of a path extending between the first and the third regions through the connection region is lower than a resistance of a path extending between the first and the third regions through the second region. A second aspect is a method of forming the semiconductor device of the first aspect.