Patent ID: 11342472

Abstract:
A device may include: a highly doped n+ Si region; an intrinsic silicon multiplication region disposed on at least a portion of the n+ Si region, the intrinsic silicon multiplication having a thickness of about 90-110 nm; a highly doped p− Si charge region disposed on at least part of the intrinsic silicon multiplication region, the p− Si charge region having a thickness of about 40-60 nm; and a p+ Ge absorption region disposed on at least a portion of the p− Si charge region; wherein the p+ Ge absorption region is doped across its entire thickness. The thickness of the n+ Si region may be about 100 nm and the thickness of the p− Si charge region may be about 50 nm. The p+ Ge absorption region may confine the electric field to the multiplication region and the charge region to achieve a temperature stability of 4.2 mV/° C.