Patent ID: 11061069

Abstract:
Apparatus and methods provide burn-in testing for semiconductors. A burn-in test apparatus (1) may include an outer housing forming an aperture with a test socket to receive a tile or wafer. The tile or wafer may include semiconductor device(s) for burn-in testing. The apparatus may include a thermal control unit to regulate testing temperature and/or drive electronics for powering the socket. The apparatus may include an inlet for gas pressure from a pressure source. The apparatus may include a lid covering the aperture when a tile/wafer is at the test socket. The apparatus may include a seal carrier in the aperture to form a pressure chamber with a surface of the tile. The pressure chamber may pneumatically couple with the inlet. Pressure of the pressure chamber may act upon the tile/wafer to urge a device under testing into thermal and/or electrical contact with the socket for conducting the burn-in test.