Patent ID: 10420088

Abstract:
Aspects of the disclosure provide a slot structure (e.g., the arrangement of channels and pilot signals within a slot) that can relax the processing timeline for a wireless communication device. For example, in the first or initial symbol of a slot, control information may be frequency division multiplexed (FDM) with a demodulation reference signal (DMRS) or with user data. In some cases, delayed-processing data may be sampled, and the samples may be buffered at the receiving device, for processing later, after control information needed to process the data has been received and processed. Further aspects provide for payload pre-tapering. That is, when a device delays the processing of data bits, this can cause a processing bottleneck after that buffering delay. By virtue of various pre-tapering techniques described herein, the processing load needed to process the delayed-processing data can be reduced. Other aspects, embodiments, and features are also claimed and described.