Patent ID: 10630310

Abstract:
An integrated charge redistribution successive approximate register (CR-SAR) analog-to-digital converter (ADC) includes a sample-and-hold switch, a digital-to-analog converter (DAC), a comparator and a logic circuit. The sample-and-hold switch obtains a sample input voltage (Vin). The DAC includes a plurality of digital multiplexers that selects between a superposition phase, which superimposes an analog offset voltage onto Vin, and a conversion phase which determines values for a digital output register which determines the input values to each control line. Each digital multiplexer presents input values to a control line. The comparator has two inputs coupled to the sample-and-hold switch and to the DAC such that the output of the converter determines a value of each successive bit in the digital output register. The logic circuit is coupled to the comparator and to digital multiplexers and includes the digital output register.