Patent ID: 10133499

Abstract:
Some embodiments provide a method for configuring unit memories to implement first and second sets of entries, the second set of which references the first set. The method configures a first pool of memories to implement the first set. Each first-set entry is located at a particular location in at least one of the first-pool memories. The method configures a second pool of memories to implement the second set of entries. Each second-set entry includes (i) a first set of bits for indicating a memory page that corresponds to one or more first-pool memories, (ii) a second set of bits for specifying a location in each of the one or more memories from which to retrieve data for the referenced first-set entry, and (iii) a third set of bits for specifying a sub-location within the retrieved data. The number of bits in the third set of bits is fixed for the second-set entries while a number of sub-locations varies for different locations specified by the second set of bits of different second-set entries.