Patent ID: 10692796

Abstract:
A semiconductor package (1, 1′, 1″), the package (1, 1′, 1″) comprising a first substrate (2) comprising at a front cavity side (5′) a plurality of cavities (6, 6′), each of the cavities (6, 6′) having a bottom wall (7) and side walls (8), and having a conductive path (10) forming an electric contact surface (9) located at the inner side of the bottom wall (7) of the cavity (6, 6′), a plurality of semiconductor elements (16, 7), each of the semiconductor elements (16, 17) comprising a first electric contact surface (9) on a first side (26) and a second electric contact surface (9) on a second side (28) opposite to the first side (26), wherein at least one of the semiconductor elements (16, 17) is placed within a corresponding cavity (6, 6′) at the front cavity side (5′) of the first substrate (2), wherein the first electric contact (27) of the semiconductor element (16, 17) and the electric contact surface (9) at the inner side of the bottom wall (7) of the corresponding cavity (6, 6′) are electrically conductive bonded in a material-locking manner, and a second substrate (3), the second substrate (3) being attached with a connection side (12, 13) to the front cavity side (5′) of the first substrate (2) thereby encapsulating the semiconductor elements (16, 17) located within the corresponding cavities (6, 6′) at the front cavity side (5′) of the first substrate (2).