Patent ID: 11792971

Abstract:
An SRAM cell includes: first, second, third, fourth, and fifth dielectric fins disposed in this order along a first direction and oriented lengthwise along a second direction, where the first and the fifth dielectric fins define two edges of the SRAM cell; a first n-type semiconductor fin structure disposed between the first and the second dielectric fins; a second n-type semiconductor fin structure disposed between the fourth and the fifth dielectric fins; a first p-type semiconductor fin structure disposed between the second and the third dielectric fins; a second p-type semiconductor fin structure disposed between the third and the fourth dielectric fins, where each of the first and the second n-type semiconductor fin structures and each of the first and the second p-type semiconductor fin structures is oriented lengthwise along the second direction; and gate structures oriented lengthwise along the first direction, where the gate structures engage with one or more of the dielectric fin.