Patent ID: 10872672

Abstract:
A nonvolatile memory device includes a memory cell array includes memory cells, a row decoder, a page buffer circuit and a control logic circuit. The row decoder is connected to the memory cells through word lines and includes switches configured to select the word lines, respectively. The page buffer circuit is connected to the memory cell array through bit lines. The control logic circuit is configured to perform operational functions when the row decoder turns on a switch corresponding to a particular word line among the word lines. The operational functions include supplying a charging voltage to the particular word line through the switch, stopping the supply of the charging voltage after the charging voltage is supplied to the particular word line, leaking a fixed current from the particular word line through the switch after stopping the supply of the charging voltage, and outputting, to an external device, time information about a time from when the fixed current is initially leaked to a time when a voltage of the particular word line becomes lower than a reference voltage.