Patent ID: 11347964

Abstract:
A hardware circuit in which integer numbers are used to represent fixed-point numbers having an integer part and a fractional part is disclosed. The hardware circuit comprises a multiply-accumulate unit configured to perform convolution operations using input data and weights and, in dependence thereon, to generate an intermediate result. The hardware circuit comprises a bias bit shifter configured to shift a bias value bitwise by a bias shift value so as to provide a bit-shifted bias value, a carry bit shifter configured to shift a carry value bitwise by a carry shift value so as to provide a bit-shifted carry value, an adder tree configured to add the intermediate result, the bit-shifted bias value and the bit-shifted carry value so as to provide a multiple-accumulate result and a multiply-accumulate bit shifter configured to shift the multiple-accumulate result bitwise by a multiply-accumulate shift value) to provide a bit-shifted multiply-accumulate result.