Patent ID: 10777549

Abstract:
An IGBT region in which an IGBT is disposed and a FWD region in which a FWD connected in antiparallel to the IGBT is disposed are provided in an active region of a semiconductor chip. In the active region, the FWD region is provided in plural separated from each other. The IGBT region is a continuous region between the FWD regions. In the IGBT region and the FWD region, first and second gate trenches are disposed in striped-shape layouts that are parallel to a front surface of the semiconductor chip and extend along a same first direction. The second gate trenches of the FWDs of the FWD regions are disposed separated from the first gate trenches of the IGBT in the IGBT region. This structure enables degradation of element characteristics to be prevented, and heat dissipation of the semiconductor chip and the degrees of freedom in design to be enhanced.