Patent ID: 10680632

Abstract:
A TI ADC circuit (30) comprises a plurality of L analog inputs (32-1, 32-2, 32-3) and a plurality of L digital outputs (34-1, 34-2, 34-3). The i:th analog input (32-i) is for receiving an i:th analog input signal. The i:th digital output (34-i) is for outputting an i:th digital output signal, which is a digital representation of the i:th analog input signal. TI ADC circuit (30) comprises a set (90) of sub ADCs (100-1—100-K). The TI ADC circuit (30) is configured to generate one sample of each of the L digital output signals per conversion cycle. Each sub ADC (100-1—100-K) is configured to generate a digital output sample in M conversion cycles, wherein M is an integer >1. The number K of sub ADCs in the set (90) of sub ADCs (100-1—100-K) exceeds L·M. TI ADC circuit (30) comprises a control circuit (120) configured to select, for each input sample of each of the L analog input signals, which available sub ADC (100-1—100-K) in the set (90) of sub ADCs that should operate on that input sample, such that at least some of the sub ADCs (100-1—100-K), over time, operate on input samples of each of the L analog input signals.