Patent ID: 10268556

Abstract:
The present disclosure relates to system(s) and method(s) for simulation results analysis and failures debug using a Descriptive Tracking Header. The method may comprise processing a set of input packets by a Design Under Verification or System Under Verification (DUV/SUV) and mimicking, by a prediction unit corresponding to the DUV/SUV, functionality of the DUV/SUV. The prediction unit may be a part of a testbench and is configured to process a set of input packets to predict a set of expected output packets. In one embodiment, each expected output packet from the set of expected output packets may be attached with a Descriptive Tracking Header. The Descriptive Tracking Header corresponds to metadata associated with the expected output packet. The Descriptive Tracking Header is further updated based on the result of the comparison of the expected output packet against the corresponding actual output packet and used for the generation of simulation results summary for the purpose of simulation results analysis and failures debug.