Patent ID: 10860772

Abstract:
The present disclosure provides methods and apparatus for designing an interconnection structure and methods for manufacturing an interconnection structure, and relates to the technical field of semiconductors. An implementation of the method may include: designing n virtual interconnection units according to a number of metal interconnection layers in a circuit area of a chip design drawing, where an ith virtual interconnection unit includes i metal interconnection layers, and where adjacent metal interconnection layers in a jth virtual interconnection unit are connected by using vias, and n≥2, 1≤i≤n, and 2≤j≤n; and filling an area in the chip design drawing outside the circuit area with virtual interconnection units, where the jth virtual interconnection unit is filled, and a (j−1)th virtual interconnection unit is not filled unless there is no space in the area for the jth virtual interconnection unit.