Patent ID: 10121442

Abstract:
The present disclosure relates to a driving method and a driving unit of GOA circuits. The driving unit includes a timing control chip and a GOA circuit including a plurality of cascaded GOA driving units. The timing control chip inputs first clock signals, second clock signals, and a constant-voltage potential to the GOA driving units at each of levels to drive the GOA driving units to output the scanning driving signals level-by-level, wherein scanning initial signals are further inputted to the GOA driving units at the first through the fourth level. The first clock signals and the second clock signals are two different clock signals selected from one clock signals set including eight high-frequency clock signals (CK1˜CK8), wherein CKm and CKm+4 are inverting signals. A period of each of the high-frequency clock signals is T, and a high-potential pulse width within the period (T) is T1 During a scanning driving process of each of frames, the high-potential pulse width of the high-frequency clock signals (CKm) is T1m, T1m<T1, m=1, 2, 3, and 4.