Patent ID: 10741611

Abstract:
A cross-bar array includes one or more input row lines, one or more output column lines, one or more resistive processing units (RPUs) coupled at one or more intersections of the input row lines and the output column lines, and a control circuit. A given one of the RPUs includes an analog memory element including a first terminal coupled to a given one of the input row lines and a second terminal coupled to a given one of the output column lines. The analog memory element includes a complementary metal-oxide-semiconductor structure including an n-type field-effect transistor and a p-type field-effect transistor. A gate of the n-type field-effect transistor is coupled to a gate of the p-type field effect transistor to provide a floating gate. The control circuit is configured to read a synaptic weight value of the given RPU by measuring a stored electrical charge of the floating gate.