Patent ID: 11662981

Abstract:
Methods, apparatuses, and truncated multiplication circuitry for truncated multiplication are provided. Truncated multiplication circuitry includes a control register that includes a first section configured to store a first value representing truncating a most significant bit (MSB) of a partial product of a multiplier and a multiplicand, and a second section configured to store a value representing a truncation mode. The truncated multiplication circuitry also includes control circuitry configured to truncate the MSB of the partial product based on the truncation mode if the first section stores the first value. A method includes: in response to receiving a multiplier and a multiplicand, determining a partial product of the multiplier and the multiplicand; receiving a first value representing truncating a most significant bit (MSB) of the partial product and a value representing a truncation mode; and truncating the MSB of the partial product based on the truncation mode.