Patent ID: 11595047

Abstract:
Described herein is a phase frequency detector (PFD) with a wide operational range. The PFD includes a first flip-flop to receive a reference clock and generate a first output signal based on differences between the reference clock and a feedback clock, a second flip-flop to receive the feedback clock and generate a second output signal based on differences between the reference the feedback clocks, a reset processing path connected to the first flip-flop and second flip-flop, the reset processing path having a reset delay to control a pulse width of a reset signal associated with the first flip-flop and second flip-flop, and an output processing path connected to the first flip-flop and second flip-flop, the output processing path having an output delay to control a pulse width of the first output signal and the second output signal, where the reset processing path and the output processing path are delay independent.