Patent ID: 10958269

Abstract:
A bridge output circuit of the present invention reduces the dead time.Upon receiving an input signal (SIN) for indicating on state of a high-side transistor (1H), a gate control signal generation circuit (4) outputs a low-side gate control signal (LGCTL) for turning off a low-side transistor (1L) to a low-side driver circuit (2L). On the other hand, a high-side gate control signal (HGCTL) for turning on the high-side transistor is generated from a signal delayed the low-side gate control signal and outputted to a high-side driver circuit (2H). The time of delay is controlled by the input signal (SIN), a signal (LGFB) indicating on/off state of the low-side transistor, and a signal (SOUT_L) indicating a level of an output signal.