Patent ID: 10606798

Abstract:
A method for configuring an address table in a field-programmable gate array (FPGA), an FPGA, and a network device applying the FPGA, where the FPGA includes k storage blocks, the k is greater than or equal to the two, and the FPGA is configured to obtain a key, where the key is generated based on a first packet of a data stream, and a length of the key is equal to a key bit width of the FPGA, obtain an index number corresponding to the key, where the index number is used to search for a forwarding entry of the data stream, divide the key into k sub-keys, where each of the k sub-keys corresponds to one of the k storage blocks, determine an address entry of each of the k sub-keys in a corresponding storage block, and write a storage address to the address entry based on the index number.