Patent ID: 10229914

Abstract:
A three-dimensional (3D) semiconductor memory device may include a substrate including a cell array region and a connection region, an electrode structure including pluralities of first and second electrodes that are vertically and alternately stacked on a surface of the substrate, extending in a first direction that is parallel to the surface of the substrate, and may include a stair step structure on the connection region, first and second string selection electrodes that extend in the first direction on the electrode structure and spaced apart from each other in a second direction that is parallel to the surface of the substrate and perpendicular to the first direction. The first and second string selection electrodes may each include an electrode portion on the cell array region and a pad portion that extends from the electrode portion in the first direction and on the connection region. Widths in the second direction of the pad portions may be different from widths in the second direction of the respective electrode portions.