Patent ID: 10505550

Abstract:
A synchronizing high-speed clock divider has a Clk input, a Clks input, and a reset input configured to correct phase misalignment on clock divider outputs caused by phase skew between a Clk input signal and a Clks input signal, and comprises a reset synchronizer configured to generate at least one synchronous internal reset signal in response to a reset signal and the Clk input signal, a first clock divider configured to receive the Clk input signal on the Clk input and a reset signal on a first clock divider reset input to provide a Clk out signal, a second clock divider configured to receive the Clks input signal on the Clks input and the reset signal on a second clock divider reset input to provide a Clks out signal, a phase skew detector configured to detect a phase alignment between the Clk out signal and the Clks out signal, and a phase skew corrector coupled to the phase skew detector and the second clock divider configured to change the phase alignment to be within a same phase as the first clock divider. A key aspect of the clock divider is that once phase misalignment between the Clk and Clks out signals is detected, the phase misalignment is corrected.