Patent ID: 11159133

Abstract:
A buffer circuit for a radio frequency (RF) signal includes a single leg and a feedback mesh. The single leg is coupled between a voltage supply and ground. The single leg includes a pMOS FET and an nMOS FET, and an output terminal defined at drain terminals of the pMOS FET and the nMOS FET. The buffer circuit includes an input terminal capacitively coupled to gates of the pMOS FET and the nMOS FET. The input terminal is configured to receive the RF signal, and a buffered signal is provided on the output terminal. The feedback mesh is coupled to the output terminal and coupled to the gates of the pMOS FET and the nMOS FET. The feedback mesh includes a series-coupled inductive-resistive feedback impedance, and a resistive feedback impedance in parallel with the series-coupled inductive-resistive feedback impedance.