Patent ID: 11237834

Abstract:
A memory device includes a memory array with at least one memory macro, a flag, and a controller. The controller is coupled to the memory array. Each bit of data stored in the at least one memory macro is presented as a first bit type or a second bit type. The controller is configured to select one of a first situation mode and a second situation mode as a selected situation mode according to a first retention time of the first bit type and a second retention time of the second bit type. The first situation mode is that a number of bits with the first bit type in data is larger than a number of bit with the second bit type in data, and the second situation mode is that the number of bit with the first bit type in data is not larger than the number of bits with the second bit type in data. In a write operation of the at least one memory macro, the controller determines that an input data is meet the selected situation mode or not. In response to the input data is meet the selected situation mode, the controller disables the flag and writes the input data into the at least one memory macro. In response to the input data is not meet the selected situation mode, the controller enables the flag, inverts the input data, and writes an inverted input data into the at least one memory macro.