Patent ID: 11087029

Abstract:
A decryption integrated circuit (IC) includes an interface configured to receive an encrypted block of data and a decryption datapath. The decryption datapath has a plurality of computational stages arranged in a pipeline configured to decrypt the encrypted block of data to form a decrypted block of data. A non-linear computational stage included in the pipeline of the decryption datapath includes multiple asymmetric logical paths and multiple bypassable latches. A first signal traverses a first logical path and a second signal traverses a second logical path having a greater number of logical units than the first logical path. Each bypassable latch is positioned in a respective logical path of the multiple asymmetric logical paths. The decryption IC further includes a controller configured to assign an individual random bit sequence to each bypassable latch to randomly activate or randomly disable each bypassable latch of the multiple bypassable latches.