Patent ID: 11398822

Abstract:
An output driver (1) comprises a driver transistor (MP0) having a gate node (GMP0) to apply a gate control voltage (GCV) and a gate control circuit (30) to control the gate node (GMP0) of the driver transistor (MP0). The output driver (1) is configured to be operable in a first operation mode and a second operation mode, the variable resistance of the current path of the driver transistor (MP0) being lower in the first operation mode than in the second operation mode. The gate control circuit (30) comprises a controllable resistor (RC), the controllable resistor (RC) being disposed between the gate node (GMP0) of the driver transistor (MP0) and an output node (QP) of the output driver (1), and a resistance of the controllable resistor (RC) being dependent on operating the output driver in the first or second operation mode.