Patent ID: 10121545

Abstract:
An operating method of a semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status, the operating method comprising: setting a first group of the memory cells, which have a first group of the program statuses as the target program status, to a program permit mode; setting a second group of the memory cells, which have a second group of the program statuses as the target program status, to a program inhibit mode; performing a program operation and a program verification operation to an i-th one of the “n” program statuses in ascending order of level of the program statuses; and changing one or more of the memory cells of the first group of the memory cells having the i-th program status from the program permit mode to the program inhibit mode, and one or more of the memory cells of the second group of the memory cells having an (i+k)th program status to from the program inhibit mode to the program permit mode, upon success of the program verification operation to the i-th program status.