Patent ID: 10037924

Abstract:
A method for fabricating a Fin-FET device includes forming fin structures with each having a gate structure on the top in both P-type regions and N-type regions, forming a first epitaxial layer on each fin structure on both sides of the gate structure in the P-type regions, forming a P-type doped first covering layer on each first epitaxial layer, forming a second epitaxial layer on each fin structure on both sides of the gate structure in the N-type regions, forming an N-type doped second covering layer on each second epitaxial layer, and forming a titanium-containing silicification layer on the first covering layer and the second covering layer. The method further includes performing a first annealing process to let titanium ions in the silicification layer diffuse into the first covering layer to form a first metal silicide layer and into the second covering layer to form a second metal silicide layer.