Patent ID: 11876125

Abstract:
Aspects of the present disclosure provide a 3D semiconductor apparatus and a method for fabricating the same. The 3D semiconductor apparatus can include a first semiconductor device including sidewall structures of a first gate metal sandwiched by dielectric layers, a first epitaxially grown channel surrounded by the sidewall structures; a second semiconductor device formed on the same substrate adjacent to the first semiconductor device that includes sidewall structures of a second gate metal sandwiched by dielectric layers, a second epitaxially grown channel surrounded by the sidewall structures; a salicide layer formed between the first and second semiconductor devices and metallization contacting each of the S/D regions and the gate regions. The 3D semiconductor apparatus may include a P+ epitaxially grown channel formed on the same substrate adjacent to an N+ epitaxially grown channel, the P+ epitaxially grown channel separated from N+ epitaxially grown channel by a diffusion break.