Patent ID: 10345378

Abstract:
A computer implemented method, and an apparatus, are provided for performing a scalability check on a Hardware Description Language (HDL) representation of a circuit. The HDL representation identifies a plurality of sink signals, where each sink signal is arranged to take a result value computed by performing an operation using as input one or more driver signals. The method comprises creating within a storage a mapping table to map drivers signals to sink signals, where each entry identifies a sink signal and an associated sink width indication, identifies each driver signal used in the computation of the result value for that sink signal along with an associated driver width indication for each driver signal, and an operation type indication for the operation used to compute the result value for the sink signal. A scalability check operation is then executed on processing circuitry for one or more selected entries in the mapping table that have at least one of the sink and driver width indications specified with reference to at least one parameter. The scalability check operation comprises determining, using the operation type indication and the driver width indication for each driver signal, a driver signal identifying an expected width for the sink signal, and determining using the sink width indication a sink formula to identify the width of the sink signal. The sink formula and the driver formula are then evaluated to determine whether the presence of the at least one parameter gives rise to a scalability issue. A result file is then output identifying each sink signal that has been detected to have a scalability issue.