Patent ID: 10274533

Abstract:
An apparatus for performing multi-tier domain pre-characterization for floating random walk capacitance extraction of a semiconductor structure includes a processor configured to recursively execute a floating random walk algorithm, over a plurality of points for a plurality of conductors, to permit determination of a potential at a plurality of points on a Gaussian surface around each of a plurality of conductors and determination of a coupling capacitance between the plurality of conductors, each iteration of the floating random walk algorithm comprising selection of a domain about an initial boundary point on the Gaussian surface of the respective one of the plurality of conductors and determination of a new boundary point on the new domain, from which a successive boundary point is selected with a corresponding successive domain centered thereabout, this process continuing until a corresponding successive domain terminates at a boundary having a known potential, whereupon the processor determines the potential at the initial boundary point on the Gaussian surface of the respective one of the plurality of conductors, wherein at least one domain during each floating random walk is matched by the processor to one of a plurality of pre-characterized domains, the matching of the selected domain with the one of a plurality of pre-characterized domains utilizing a smart sweep method, a single dielectric method, a two-dielectric method, a three-dielectric method or an averaging method.