Patent ID: 11469290

Abstract:
The present disclosure relates to the field of display technologies, and provides an array substrate, a manufacturing method thereof, and a display panel. In the array substrate, a substrate is provided with a first transistor and a second transistor, a first electrode of the first transistor is electrically connected to a gate of the second transistor; a conductive layer is disposed on the substrate, and includes a first conductor portion, a first semiconductor portion, a second conductor portion that are sequentially connected along a first direction; a first gate insulating layer is disposed on a side of the conductive layer away from the substrate; a first gate layer is disposed on a side of the first gate insulating layer away from the substrate to form the gate of the second transistor; a dielectric layer is disposed on the substrate to cover a part of the first conductor portion, a part of the second conductor portion and a part of the first gate layer, and an orthographic projection of a first via hole disposed on the dielectric layer on the substrate overlaps with orthographic projections of at least a part of the first conductor portion, at least a part of the second conductor portion and the first gate layer on the substrate; and a first source/drain layer is disposed on a side of the dielectric layer away from the substrate to cover the first via hole.