Patent ID: 11158632

Abstract:
A device includes a memory cell having a gate-all-around (GAA) transistor and the well strap cell having a dummy fin-like field effect transistor (FinFET). The GAA transistor includes a first fin extending along a first direction, and the dummy FinFET includes a second fin extending along the first direction. The GAA transistor includes first source/drain features over the first fin and suspended channel layers between the first source/drain features. The first source/drain features include a first type dopant. The suspended channel layers have a first channel width along a second direction different than the first direction. The dummy FinFET includes second source/drain features over the second fin and a fin channel layer between the second source/drain features. The second source/drain features include a second type dopant. The fin channel layer has a second channel width along the second direction. The second channel width is greater than the first channel width.