Patent ID: 10942853

Abstract:
A method, computer program product, and computer system are disclosed that in one or more embodiments includes issuing, from an issuing processor in the computer system, an address translation invalidation instruction with a return marker, wherein the address translation invalidation instruction is to invalidate one or more address translation entries in one or more storage locations in the computer system and wherein the return marker comprises an instruction to return information to the issuing processor indicating the identity of each processor where an invalidated entry was located. The method, product, and system in an embodiment further includes broadcasting the address translation invalidation instruction with the return marker to one or more storage locations of one or more of the processors in the computer system other than the issuing processor; invalidating the address translation entry corresponding to the broadcasted address translation invalidation instruction; and returning to the issuing processor information on each storage location corresponding to the invalidated address translation entry. In one or more embodiments, the returned information is used to determine the performance of the computing system, identifying the storage locations where data was located.