Patent ID: 11522287

Abstract:
A plurality of reception modules (1a,1b) receive signals from a plurality of antennas (2a,2b) respectively. A synthesizer (3) synthesizes output signals of the plurality of reception modules (1a,1b). Each of the plurality of reception modules (1a, 1b) includes a first sample-and-hold circuit (7a,7b) sampling and holding a received signal, a second sample-and-hold circuit (8a,8b) sampling and holding an output signal of the first sample-and-hold circuit (7a,7b), and a controller (9a,9b) controlling a timing at which the first sample-and-hold circuit (7a,7b) samples and holds the signal. Operation timings of the first sample-and-hold circuits (7a,7b) are set for the respective reception modules (1a,1b). Operation timings of the second sample-and-hold circuits (8a,8b) of the plurality of reception modules (1a,1b) are same.