Patent ID: 11206036

Abstract:
An integrated self-test mechanism for monitoring an analog-to-digital converter (ADC), a reference voltage (Vref) source associated with the ADC, a low-dropout regulator (LDO), or a power supply is provided. In one example, an ADC that is associated with an integrated circuit (IC) can monitor its own Vref, the voltage (VLBO) of an LDO associated with the IC, or the voltage (AVDD) provided to an electrical coupling mechanism in the IC that is coupled to a power supply associated with the IC. The ADC can generate a digital output code based, at least in part, on the Vref and one or more of the VLBO and the AVDD. The digital output code can be used to determine whether one or more of the ADC, the Vref source, the LDO, and the power supply is malfunctioning or nonoperational.