Patent ID: 10937753

Abstract:
A semiconductor device comprising: a semiconductor chip; and a wiring substrate having: a first region overlapping with the semiconductor chip, and a second region surrounding the first region in plan view. Also, the wiring substrate includes: a first wiring layer, a third wiring layer, and a plurality of data wirings arranged so as to straddle a border between the first region and the second region. Also, the plurality of data wirings includes: a first data wiring transmitting a first byte data signal, and a second data wiring transmitting a second byte data signal. Also, in the first wiring layer, the first data wiring is arranged so as to straddle the border. Also, in the third wiring layer, the second data wiring is arranged so as to straddle the border. Further, in plan view, the first data wiring and the second data wiring are overlapped with each other.