Patent ID: 11995447

Abstract:
A quick predictor override system and method for a microprocessor that enables a correction to a quick predictor, branch prediction by a branch target address cache (BTAC), and rapid update to the quick predictor. For example, the microprocessor includes a quick predictor that provides branch prediction based on a local pattern history, and a large predictor in the form of the BTAC, which provides for branch prediction using a global pattern history. Branch prediction by the BTAC is the prevailing prediction if different, for a fetched cache address, than the branch prediction by the smaller, quick predictor. Accordingly, the target and direction for conditional branches provided by the BTAC for fetching the next cache instruction are used in favor of the target and direction previously provided by the quick predictor, and the quick predictor is quickly updated with the target and direction from the BTAC during a BTAC stage.