Patent ID: 10374084

Abstract:
The disclosed technology generally relates to semiconductor devices and more particularly to vertical channel devices and a method of making the same. In one aspect, a method of forming vertical channel devices includes forming a first vertical channel structure extending from a first bottom electrode region and a second vertical channel structure extending from a second bottom electrode region. The first and the second vertical channel structures protrude from a dielectric layer covering the first and second bottom electrode regions. The method additionally comprises forming a first hole exposing the first bottom electrode region and a second hole exposing the second bottom electrode region, where the first and the second holes extending vertically through the dielectric layer. The method additionally includes forming a conductive pattern including a set of discrete pattern parts on the dielectric layer. Forming the conductive pattern includes forming a first pattern part including a first gate portion wrapping around a protruding portion of the first vertical channel structure, where a first bottom electrode contact portion is arranged in the second hole, and a first cross-coupling portion extending between the first bottom electrode contact portion and the first gate portion. Forming the conductive pattern additionally includes forming a second pattern part including a second gate portion wrapping around a protruding portion of the second vertical channel structure, where a second bottom electrode contact portion is arranged in the first hole, and a cross-coupling portion extending between the second bottom electrode contact portion and the second gate portion.