Patent ID: 10074576

Abstract:
A semiconductor device including a circuit that has a reduced area is provided. Alternatively, a semiconductor device including a circuit that can have a smaller power supply voltage variation is provided.The semiconductor device includes a first transistor, a second transistor, a first power supply wiring, and a second power supply wiring. The first transistor and the second transistor are stacked. The first power supply wiring and the second power supply wiring are stacked. The second power supply wiring and the first power supply wiring at least partly overlap with each other. The second power supply wiring and the first power supply wiring are substantially parallel to each other. A source electrode of the first transistor is electrically connected to the first power supply wiring. A source electrode of the second transistor is electrically connected to the second power supply wiring. The second transistor is an n-channel transistor, and a channel formation region is formed using an oxide semiconductor. The first transistor is a p-channel transistor, and a channel formation region is formed using silicon.