Patent ID: 10191853

Abstract:
An apparatus and method are provided for maintaining address translation data within an address translation cache. Each entry of the address translation cache is arranged to store address translation data used when converting a virtual address into a corresponding physical address of a memory system. Control circuitry is used to perform an allocation process to determine the address translation data to be stored in each entry. When performing the allocation process for a selected entry, the control circuitry is arranged to perform a page table walk process using a virtual address in order to obtain from a page table a plurality of descriptors including a descriptor identified using the virtual address. The control circuitry then determines whether predetermined criteria are met by the plurality of descriptors, the predetermined criteria comprising page alignment criteria and attribute match criteria. Each descriptor comprises physical address data and attribute data identifying a plurality of attributes, and the attribute match criteria allows the plurality of descriptors to have different values for a first subset of attributes when determining that the attribute match criteria is met. When the predetermined criteria are met, coalesced address translation data is generated from the plurality of descriptors and that coalesced address translation data is then stored in the selected entry. Otherwise, if the predetermined criteria is not met, address translation data is merely generated from the descriptor identified using the virtual address, and that address translation data is then stored in the selected entry. Such an approach significantly increases the effective capacity and performance of the address translation cache.