Patent ID: 10816589

Abstract:
A structure for testing a semiconductor device. A first resistor structure (R1) comprises a first active region (110) and a first polysilicon gate (130) disposed on the first active region (110); the width of the first active region (110) is greater than a predetermined width value; the predetermined width value is the critical value of the width of an active region of the semiconductor device when the step height of a shallow trench isolation structure of the semiconductor device affects the width of a polysilicon gate; the design width of the first polysilicon gate (130) is identical to that of the polysilicon gate of the semiconductor device; a second resistor structure (R2) is connected to the first resistor structure (R1) according to a predetermined circuit structure to form a test circuit, and comprises a second active region (210) and a second polysilicon gate (230) disposed on the second active region (210); the width of the second active region (210) is less than the predetermined width value; the design size of the second polysilicon gate (230) is identical to that of the first polysilicon gate (130); the total resistance of a branch circuit where the second resistor structure (R2) is located is equal to the total resistance of a branch circuit where the first resistor structure (R1) is located.