Patent ID: 10121965

Abstract:
An alternating stack of insulating layers and electrically conductive layers is formed over a substrate. Sidewalls of the electrically conductive layers are laterally recessed to form laterally recessed regions. After formation of a conformal barrier material layer in the laterally recessed regions and on the sidewalls of the insulating layers, an amorphous precursor memory material layer is deposited in lateral cavities and over the conformal barrier material layer. An anneal process is performed to selectively crystallize portions of the amorphous precursor memory material layer in the lateral cavities into crystalline memory material portions while not crystallizing portions of the amorphous precursor memory material outside the lateral cavities. Remaining amorphous portions of the amorphous precursor memory material layer are removed selective to the crystalline memory material portions. A vertical conductive line is formed on the crystalline memory material portions. The crystalline memory material portions are formed as discrete self-aligned material portions.