Patent ID: 11138126

Abstract:
Data processing apparatus comprises one or more processing elements to execute processing instructions; address translation circuitry to perform address translations between a virtual address space and a physical address space, the address translations being defined by a current hierarchical set of address translation tables selected from two or more hierarchical sets of address translation tables, the address translation circuitry being responsive to current table definition data providing at least a pointer to a memory location of the current hierarchical set of address translation tables; the one or more processing elements being configured to overwrite the current table definition data with second table definition data providing at least a pointer to a memory location of a second, different, hierarchical set of address translation tables of the two or more hierarchical sets of address translation tables; the one or more processing elements being configured to execute test instructions requiring address translation before and after the overwriting of the current table definition data by the control circuitry and to detect whether the address translations required by the test instructions are correctly performed.