Patent ID: 10204066

Abstract:
A system includes a multi-conductor bus, a master device coupled to the multi-conductor bus, and at least one slave device coupled to the multi-conductor bus. The multi-conductor bus has a clock line and a data line. The master device is arranged to transmit an address configuration sequence, and the at least one slave device is arranged to configurably determine its own address based on at least one portion of the address configuration sequence. The at least one slave device has a physical address configuration input coupled to either a fixed voltage potential or a changing voltage potential. The at least one slave device is arranged with a first address during a pre-initialization state and arranged with a second address during a post-initialization state. During the post-initialization state, the first address and the second address are a same address when the address configuration sequence represents the first address and the first address and the second address are different addresses when the address configuration sequence does not represent the first address.