Patent ID: 10840145

Abstract:
Device structures and methods are provided for fabricating vertical field-effect transistor devices with non-uniform thickness bottom spacers to achieve increased device performance. For example, a semiconductor substrate surface is etched to form semiconductor fins having bottom portions with concave sidewall surfaces that undercut upper portions of the fins. A doped epitaxial source/drain layer is formed on the concave sidewall surfaces, wherein portions of the doped epitaxial source/drain layer disposed between the fins have a raised curved surface. A bottom spacer layer is formed on the doped epitaxial source/drain layer, wherein portions of the bottom spacer layer disposed between the fins have a curved-shaped profile with a non-uniform thickness. A thermal anneal process is performed to drive dopants from the doped epitaxial source/drain layer into the bottom portions of the fins to form source/drain extension regions with sharp junctions between the source/drain extension regions and channel regions of the fins.