Patent ID: 10176289

Abstract:
A method for a semiconductor layout pattern decomposition includes following steps. (a) receiving a semiconductor layout pattern; (b) performing a first separation/decomposition to the semiconductor layout pattern to obtain a grille pattern and a non-grille pattern; (c) recognizing a plurality of intersection regions in the grille pattern and alternately marking the intersection regions with a first region and a second region; (d) performing a second separation/decomposition to the grille pattern to obtain a plurality of first sub-patterns and a plurality of second sub-patterns perpendicular to each other, the first sub-patterns including the first regions, the second sub-patterns including the second regions; and (e) introducing a plurality of first assistance features on the first regions in the first sub-patterns and on the second regions on the second regions in the second sub-patterns, respectively. The step (a) to the step (e) are implemented using a computer.