Patent ID: 10269955

Abstract:
A vertical FET includes a silicon carbide substrate having a top surface and a bottom surface opposite the top surface; a drain/collector contact on the bottom surface of the silicon carbide substrate; and an epitaxial structure on the top surface of the silicon carbide substrate having formed therein a first source/emitter implant. A gate dielectric is provided on a portion of the epitaxial structure. First source/emitter contact segments are spaced apart from each other and on the first source/emitter implant. A first elongated gate contact and a second elongated gate contact are on the gate dielectric and positioned such that the first source/emitter implant is below and between the first elongated gate contact and the second elongated gate contact. Inter-gate plates extend from at least one of the first elongated gate contact and the second elongated gate contact into spaces formed between the first source/emitter contact segments.