Patent ID: 10437668

Abstract:
According to one embodiment, a memory controller includes: a memory I/F that reads a codeword written in a NAND memory as any one of hard-bit information, first soft-bit information, and second soft-bit information; a codeword processor that generates a codeword of an first soft-decision value from the first soft-bit information, and generates a codeword of a second soft-decision value from the second soft-bit information; a first decoder that executes hard-decision decoding on a codeword of a hard-decision value configured from the hard-bit information; a second decoder that executes first soft-decision decoding on the codeword of the first soft-decision value; and a third decoder that executes second soft-decision decoding on the codeword of the second soft-decision value, wherein the first soft-bit information includes information having a first number of bits greater than the number of bits of the hard-bit information, and the second soft-bit information includes information having a second number of bits greater than the number of bits of the first soft-bit information.