Patent ID: 11081485

Abstract:
A monolithic integrated circuit device formed in a multi-layer structure comprises a low-pinch-off-voltage pHEMT and a high-pinch-off-voltage pHEMT. A Schottky layer in the multi-layer structure contains at least three stacked regions of semiconductor material, wherein each of the two adjacent stacked regions differs in material and provides a stacked region contact interface therebetween. The gate-sinking pHEMTs each includes a gate contact, a first gate metal layer, a gate-sinking region, and a gate-sinking bottom boundary. The first gate metal layers are in contact with the topmost stacked region of the Schottky layer. The gate-sinking regions are beneath the first gate metal layers. The gate-sinking bottom boundary of the high-pinch-off-voltage pHEMT, which is closer to the semiconductor substrate than the gate-sinking bottom boundary of the low-pinch-off-voltage pHEMT, locates within 10 Å above or below one of the stacked region contact interfaces of the Schottky layer.