Patent ID: 11996164

Abstract:
Within a memory control component, command/address circuitry transmits a first command/address value to a memory component during a first interval and a second command/address value to the memory component during a second interval, and timing circuitry transmits a data strobe to the memory component during the first interval and a data clock to the memory component during the second interval. The timing circuitry transitions the data strobe from a parked state to a toggling state during the first interval at a predetermined time relative to transmission of the first command/address value and toggles the data clock throughout the second interval regardless of time of transmission of the second command/address value. Data signaling circuitry transmits first write data to the memory component during the first interval synchronously with the write-data strobe signal and transmits second write data to the memory component during the second interval synchronously with the write-data clock signal.