Patent ID: 11121156

Abstract:
An array substrate includes first and second thin-film transistors formed on a base and spaced by a predetermined distance in a first direction that is parallel to the plane on which the base is located and set in parallel. The first thin-film transistor includes a first active layer, a first gate insulation layer, a first gate electrode, a first interlayer insulation layer, and first source/drain electrodes sequentially stacked on the base in a third direction that is perpendicular to the first direction. The first source/drain electrodes are electrically connected to the first active layer. The second thin-film transistor includes a second gate electrode, a second gate insulation layer, second source/drain electrodes, and a second active layer sequentially stacked on the base in the third direction. The first active layer and the first gate electrode are both formed of a poly-silicon material. The second active layer includes an oxide semiconductor material.