Patent ID: 11444027

Abstract:
A wafer-scale satellite bus and a manner of making the same include using wafer reconstruction techniques to stack functional diced circuits onto each other and bond them. The disclosed techniques allow for a variety of functions in each die, including providing, without limitation: ground-based communications, attitude and propulsion control, fuel tanks and thrusters, and power generation. The wafers are initially manufactured according to a common wafer design that provides electrical and power interconnects, then different wafers are further processed using subsystem-specific techniques. The circuits on differently-processed wafers are reconstructed into a single stack using e.g. wafer bonding. Surface components are mounted, and the circuitry is diced to form the final satellites. Mission-specific functions can be incorporated, illustratively by surface-mounting, to the bus at an appropriate stage of assembly, on-wafer circuitry or instrument packages for performing these functions.