Patent ID: 11329041

Abstract:
A semiconductor integrated circuit includes a first MOS transistor, a second MOS transistor, and a P+ region. The first MOS transistor is an NMOS transistor which has a first N-type region and a second N-type region and in which a first power supply voltage is supplied to the first N-type region. The second MOS transistor is an NMOS transistor which has a third N-type region and a fourth N-type region and in which a second power supply voltage higher than the first power supply voltage is supplied to the third N-type region. The P+ region is supplied with the first power supply voltage. In plan view of the semiconductor substrate, the first MOS transistor and the second MOS transistor are disposed to be adjacent to each other, and the P+ region is located between the first N-type region and the third N-type region.