Patent ID: 11182324

Abstract:
Mechanisms for Field Programmable Gate Array (FPGA) chaining and unified FPGA views to a composed system hosts and associated methods, apparatus, systems and software A rack is populated with pooled system drawers including pooled compute drawers and pooled FPGA drawers communicatively coupled via input-output (IO) cables. The FPGA resources in the pooled system drawers are enumerated, identifying a location of type of each FPGA and whether it is a chainable FPGA. Intra-drawer chaining mechanisms are identified for the chainable FPGAs in each pooled compute and pooled FPGA drawer. Inter-drawer chaining mechanism are also identified for chaining FPGAs in separate pooled system drawers. The enumerated FPGA and chaining mechanism data is aggregated to generate a unified system view of the FPGA resources and their chaining mechanisms. Based on available compute nodes and FPGAs in the unified system view, new compute nodes are composed using chained FPGAs. The chained FPGAs are exposed to a hypervisor or operating system virtualization layer, or to an operating system hosted by the composed compute node as a virtual monolithic FPGA or multiple local FPGAs.