Patent ID: 10510768

Abstract:
A 3D memory device comprises: a substrate; a plurality of U-shaped memory cells strings each including a first, bit line-side string portion or pillar, a second, source line-side string portion or pillar and a buried string portion formed in the substrate and connected to a first end of the first string portion and to a first end of the second string portion, the U-shaped memory cells strings including stacks of memory cells along the first and second string portions. Bit line selectors are arranged at a second end of the first string portions opposed to the first end, for the selective connection to respective bit lines; source line selectors are arranged at a second end of the second string portions opposed to the first end, for the selective connection to respective source lines. There are first groups of first string portions, wherein in each first group the first string portions are aligned along a first direction to form a respective first row of first string portions; there are second groups of second string portions, wherein in each second group the second string portions are aligned along the first direction to form a respective second row of second string portions. The first rows of first string portions and the second rows of second string portions follow one another, alternately or in pairs, along a second direction transversal to the first direction. First rows of first string portions and/or second rows of second string portions consecutive along said second direction are spaced apart from each other a respective distance. Between a first row of first string portions and a second row of second string portions being consecutive along the second direction and spaced apart a distance equal to or less than a minimum distance allowed by the resolution of the manufacturing technology a respective slit is formed that extends in a third direction, orthogonal to the first and second directions, from the second end down to the substrate, the slit, interrupting layers forming the bit line selectors and the source line selectors and control gates of the memory cells of the memory cells stacks, with dimension, along the second direction, less than, equal to or higher than the minimum distance, and walls of the slit lying in planes parallel to the first and third directions delimit the first and second string portions.