Patent ID: 11907091

Abstract:
Trace recording based on data influxes to an outer-level cache and cache coherence protocol (CCP) transitions between inner caches. Example computing device(s) include a plurality of processing units, a plurality of (N-1)-level caches, and an N-level cache that is associated with two or more of the (N-1)-level caches and that is a backing store for the two or more (N-1)-level caches. Based at least on detecting influx(es) of data to a location in the N-level cache during execution across the processing units, the computing device(s) causes the influx(es) of data to be logged. The computing device(s) also causes one or more (N-1)-level CCP transitions between the two or more (N-1)-level caches to be logged. The (N-1)-level CCP transitions result from the location being accessed by two or more of the processing units.