Patent ID: 11799024

Abstract:
A preparation method for semiconductor device, comprising: forming a body region (110) in the drift region (100), forming a first doped region (111) and a second doped region (112) in the body region (110); forming a first trench (171) penetrating the first doped region (111) and the body region (110) and extending to the drift region (100); forming an extension region (150) with a conductivity type opposite to that of the drift region (100) and surrounding the bottom wall of the first trench (171); filling the first trench (171) with a dielectric layer (130) formed on the sidewall of the trench, a first conductive structure (141) located at the bottom of the trench and a second conductive structure (142) located at the top of the trench; forming a second trench (172) penetrating the body region (110) and extending into the drift region (100); filling the second trench (172) with a third conductive structure (143) and a dielectric layer (130) formed on the inner wall of the trench. The second conductive structure (142) is electrically connected with the gate, and the first doped region (111), the second doped region (112), and the third conductive structure (143) are electrically connected with the first electrode (130).