Patent ID: 11726667

Abstract:
In certain aspects, a memory device includes an array of memory cells, an input/output (I/O) circuit, and control logic coupled to the I/O circuit. The array of memory cells includes N main banks and M redundant banks, where each of N and M is a positive integer, and N is great than M. The I/O circuit is coupled to the N main banks and the M redundant banks and configured to direct N pieces of data to or from N working banks, respectively. The control circuit is configured to determine the N working banks from the N main banks and the M redundant banks based on bank fail information indicative of K failed main banks of the N main banks. The N working banks include K redundant banks of the M redundant banks, where K is a positive integer not greater than M. The control circuit is further configured to control the I/O circuit to direct K pieces of data of the N pieces of data to or from the K redundant banks, respectively.