Patent ID: 11107937

Abstract:
The n-type amorphous semiconductor layers 4 are on parts of that one of the faces of the semiconductor substrate 1, there being provided no p-type amorphous semiconductor layers 5 in the parts. The electrodes 6 are disposed on the n-type amorphous semiconductor layers 4. The electrodes 7 are disposed on the p-type amorphous semiconductor layers 5. The p-type amorphous semiconductor layers 5 between those n-type amorphous semiconductor layers 4 which are adjacent along an in-plane direction of the semiconductor substrate 1 include, arranged along a first direction that points from the n-type amorphous semiconductor layers 4 toward the adjacent n-type amorphous semiconductor layers 4: first and second electrode-provided regions where the electrodes 7 are disposed; and a no-electrode-provided region, between the first and second electrode-provided regions, where there are provided no electrodes 7.