Patent ID: 11836128

Abstract:
Dynamic Random Access Memory (DRAM) and a logic layer having direct access to the DRAM which provides symbolic addressing services. These services are provided by sequencers in the logic layer. The sequencers maintain a DRAM row or row-pair in sorted order, find a location and insert a new data element into the row or row-pair, all while preserving the sorted order. The sequencer is a plurality sequencer groups, each a plurality of sequencer cells. The sequencer cells perform a highly parallel pipeline insertion of a new data element. The logic layer also defines a Self-Addressing Memory Central Processing Unit (SamPU) operatively coupled to, and configured to control, the sequencer. The logic layer provides program memory for SamPU and a memory cache to build an index database. The database is subject to mitosis to accommodate the overflow of any item in the index database.