Patent ID: 11058382

Abstract:
An apparatus (e.g., an imaging system) includes a circuit, including: a p-i-n diode having a cathode coupled to a cathode bias voltage or ground; a charge transistor having a first source/drain terminal coupled to an anode of the diode; a storage capacitor having a first terminal coupled to a second source/drain terminal of the charge transistor and a second terminal coupled to the cathode; an amplification transistor having a gate terminal coupled to the first terminal of the storage capacitor and a first source/drain terminal coupled to a reference voltage; a read transistor having a first source/drain terminal coupled to a second source/drain terminal of the amplification transistor; a data line having a first terminal coupled to a second source/drain terminal of the read transistor; and a readout circuit coupled to a second terminal of the data line, providing an output voltage corresponding to charge on the storage capacitor.