Patent ID: 11462622

Abstract:
According to various embodiments, a memory cell may include a substrate of a first conductivity type, the substrate having first and second regions of a second conductivity type spaced apart and defining a channel region therebetween. The memory cell may further include a word line arranged over a portion of the channel region nearer to the first region, an erase gate arranged over the second region, a floating gate arranged over another portion of the channel region nearer to the second region and between the word line and the erase gate, and a coupling gate arranged over a top end of the floating gate. The floating gate includes the top end, a bottom end, a first side extending from the top end to the bottom end and facing the erase gate, and a second side extending from the top end to the bottom end and facing the word line. A first lateral distance between the bottom end of the floating gate and the erase gate may be larger than a second lateral distance between the top end of the floating gate and the erase gate.