Patent ID: 11100847

Abstract:
A scan driver includes two or more scan signal output circuits (SSOC), each being coupled to a first scan line (FSL) and a second scan line (SSL), and including a driving circuit, a first buffer circuit (FBC), and a second buffer circuit (SBC). The driving circuit applies a first driving signal (DS) to a first driving node (DN) and applies a second DS to a second DN based on an input signal, a clock signal (CS), a display-on signal, and an on-level voltage. The input signal is a scan start signal or a previous scan signal. The FBC outputs a sensing signal to the SSL based on the first DS, the second DS, an off-level voltage, and a sensing CS. The SBC outputs a scan signal to the FSL based on the first DS, the second DS, the off-level voltage, and a scan CS.