Patent ID: 10354737

Abstract:
A non-volatile memory is configured to allow programming and erase at the sub-block level. In a sub-block erase, some of the memory cells can be selected for erase while others are not selected for erase, such as by leaving their word lines to float while applying the erase voltage to the well structure of the physical block to which the sub-blocks belong. Although a sub-block erase applies a lower electric field across the non-selected memory cells than the erase selected memory cells, it still places the non-selected memory cells under some degree of stress and can lead to erase disturb. To help manage this erase disturb, each sub-block has an associated erase disturb count, which is incremented when another sub-block of the same physical block is erased, but reset when the sub-block itself is erase. Once a count reaches a threshold value, the sub-block can be marked for remedial action, such as refresh or garbage collection.