Patent ID: 11444087

Abstract:
The present disclosure provides a semiconductor memory device with air gaps for reducing capacitive coupling between a bit line and an adjacent conductive feature and a method for preparing the semiconductor memory device. The semiconductor memory device includes a substrate; an isolation member defining an active region having a first P-type ion concentration in the substrate; a gate structure disposed in the substrate; a first doped region positioned at a first side of the gate structure in the active region; a second doped region positioned at a second side of the gate structure in the active region; a bit line positioned on the first doped region; an air gap positioned adjacent to the bit line; a capacitor plug disposed on the second doped region and a barrier layer on a sidewall of the capacitor plug; and a landing pad on a top portion of the capacitor plug, wherein the landing pad comprises a first silicide layer disposed over a protruding portion of the capacitor plug, and a second silicide layer disposed on a sidewall of the barrier layer.