Patent ID: 11940825

Abstract:
A voltage divider circuit includes at least two FDSOI transistors (TP1, TP2) of a first type connected to a first supply potential and arranged in a current mirror structure, two FDSOI transistors (TN1, TN2) of a second type and an electrical load (R), the drain of a first—respectively second—transistor (TN1) of the second type being connected to the drain of a first—respectively second—transistor (TP1) of the first type, the drain of the first transistor of the second type being connected to the front-face gate of this same transistor, the front-face gates of the first and second transistors of the second type being connected to one another, the source of the first transistor of the second type being connected to a second supply potential and the load being placed between the source of the second transistor of the second type and the second supply potential. The back-face gates of the first and second transistors of the second type (TN2) are connected to an external circuit applying an input voltage between these two back-face gates, the voltage across the terminals of the load (VRO) constituting an output voltage equal to a fraction of the input voltage.