Patent ID: 10978529

Abstract:
An active matrix substrate includes a first TFT of a peripheral circuit and a second TFT arranged in each pixel, wherein: the first TFT is a top gate or double gate TFT that includes an upper gate electrode on a portion of a first oxide semiconductor layer with a gate insulating layer interposed therebetween; the second TFT is a bottom gate TFT that includes a second lower gate electrode arranged on the substrate side of a second oxide semiconductor layer with a lower insulating layer interposed therebetween and includes no gate electrode on the second oxide semiconductor layer; the second TFT including: an island-shaped insulator layer that is arranged on a portion of the second oxide semiconductor layer so as to overlap with at least a portion of the second lower gate electrode, as seen from a direction normal to the substrate; an upper insulating layer that is arranged on the second oxide semiconductor layer and the island-shaped insulator layer; and a source electrode that is arranged on the upper insulating layer, wherein: a portion of the second oxide semiconductor layer that does not overlap with the island-shaped insulator layer is a low resistance region that has a lower specific resistance than a portion thereof that overlaps with the island-shaped insulator layer; and in an intersection between a source bus line and a gate bus line, the lower insulating layer and the upper insulating layer are located between these bus lines.