Patent ID: 11217290

Abstract:
A semiconductor device of the present disclosure includes: a first gate electrode that includes a first main line section and one or a plurality of first sub line sections, in which the first main line section extends in a first direction in a first active region of a semiconductor substrate, and segments the first active region into a first region and a second region, and the one or the plurality of first sub line sections extends from the first main line section in a second direction intersecting the first direction in the first region, and segments the first region into a plurality of sub regions including a first sub region and a second sub region; a first memory element that includes a first terminal, and a second terminal coupled to the first sub region of the semiconductor substrate, and is configured to be set in a first resistive state or a second resistive state; and a second memory element that includes a first terminal, and a second terminal coupled to the second sub region of the semiconductor substrate, and is configured to be set in the first resistive state or the second resistive state.