Patent ID: 10854283

Abstract:
A memory array includes a first memory cell and a second memory cell. Each of the first and the second memory cells includes a data storage element having a first terminal and a second terminal, a first access transistor coupled to the first terminal of the data storage element, and a second access transistor coupled to the second terminal of the data storage element. The memory array also includes a first word line and a second word line coupled to the first access transistor and the second access transistor, respectively, of the first memory cell, wherein the first word line and the second word line are operated independently during a read operation and activated at the same time during a write operation. The memory array further includes a first bit line coupled to the first access transistor of the first memory cell, a second bit line coupled to the second access transistor of the first memory cell, a third bit line coupled to the first access transistor of the second memory cell, and a first sense amplifier coupled to the first bit line and the third bit line.