Patent ID: 11004691

Abstract:
A method includes: forming source/drain epitaxy structures over a semiconductor fin; forming a first ILD layer covering the source/drain epitaxy structures; forming a gate structure over the semiconductor fin and between the source/drain epitaxy structures; forming a capping layer over the gate structure; thinning the capping layer; forming a hard mask layer over the capping layer; forming a second ILD layer spanning the hard mask layer and the first ILD layer; forming, by using an etching operation, a contact hole passing through the first and second ILD layers to one of the source/drain epitaxy structures, the etching operation being performed such that the hard mask layer has a notched corner in the contact hole; filling the contact hole with a conductive material; and performing a CMP process on the conductive material until that the notched corner of the hard mask layer is removed.