Patent ID: 11205590

Abstract:
MOL non-SAC structures and techniques for formation thereof are provided. In one aspect, a method of forming a semiconductor device includes: patterning fins in a substrate; forming gates over the fins and source/drains offset by gate spacers; lining upper sidewalls of the gates with a first dielectric liner; depositing a source/drain metal; lining upper sidewalls of the source/drain metal with a second dielectric liner; depositing a dielectric over the gates and source/drains; forming a first via in the dielectric which exposes the second dielectric liner over a select source/drain; removing the second dielectric liner from the select source/drain; forming a second via in the dielectric which exposes the first dielectric liner over a select gate; removing the first dielectric liner from the select gate; forming a source/drain contact in the first via; and forming a gate contact in the second via. A semiconductor device is also provided.