Patent ID: 11237833

Abstract:
The present invention discloses an instruction processing apparatus, comprising a first register adapted to store first source data, a second register adapted to store second source data, a third register adapted to store accumulated data, a decoder adapted to receive and decode a multiply-accumulate instruction, and an execution unit. The multiply-accumulate instruction indicates that the first register serves as a first operand, the second register serves as a second operand, the third register serves as a third operand, and a shift flag. The execution unit is coupled to the first register, the second register, the third register, and the decoder, and configured to execute the decoded multiply-accumulate instruction so as to acquire the first source data from the first register and acquire the second source data from the second register, perform a multiplication operation on the first source data and the second source data so as to obtain a multiplication result, shift the multiplication result according to the shift flag, and add the shifted multiplication result and the accumulated data in the third register so as to obtain a multiply-accumulate result. The present invention further discloses a corresponding instruction processing method, a computing system, and a system on chip.