Patent ID: 11024355

Abstract:
An MRAM bitline write control circuit including an MRAM array of a plurality of MTJ cells. Each MTJ cell is connected to a bitline between a bitline transfer gate and a transfer device. Each transfer device is connected to a sourceline and a sourceline transfer gate. A master bitline is connected to each bitline transfer gate. A first bitline control transistor is connected to VDD and to a source follower transistor that is connected to the master bitline and a gate connected to a write 0 bias voltage. A second bitline control transistor is connected to VSS and to the master bitline. A selected MTJ cell is biased to write a 0 when the transfer device, the bitline transfer gate and the source line transfer gate, associated with the selected MTJ cell, are enabled and the first bitline control transistor is enabled to connect the source follower transistor to VDD.