Patent ID: 10860485

Abstract:
The disclosure relates to embodiments, implemented at least partially in microcode, that use cache misses to trigger logging to a processor trace. One embodiment relies on tracking bits in a processor cache. During a transition from a non-logged context to a logged context, this embodiment invalidates or evicts cache lines whose tracking bits are not set. When logging, this first embodiment logs during cache misses, and sets tracking bits for logged cache lines. Another embodiment relies on way-locking. This second embodiment assigns first ways to a logged entity and second ways to a non-logged entity. The second embodiment ensures the logged entity cannot read cache lines from the second logging ways by flushing the second way during transitions from non-logging to logging, ensures the logged entity cannot read non-logged cache lines from the first ways, and logs based on cache misses into the first ways while executing a logged context.