Patent ID: 11355697

Abstract:
Example implementations include an electronic memory device with a metallic layer having a first planar crystalline structure, a first encapsulating layer including an encapsulating material having a second planar crystalline structure, and disposed adjacent to a first planar surface of the metallic layer, and a second encapsulating layer including the encapsulating material, and disposed adjacent to a second planar surface of the metallic layer. Example implementations also include a method of depositing graphite crystals onto a substrate to form a gate bottom layer, depositing BN crystals onto the graphite bottom layer to form a BN bottom layer, depositing tungsten ditelluride (WTe2) crystals onto the BN bottom layer to form a metallic layer, depositing the BN crystals onto the BN bottom layer and the metallic layer to form a BN top layer, and depositing the graphite crystals onto the BN top layer to form a gate top layer.