Patent ID: 11392160

Abstract:
A bias circuit includes a linear core circuit CC with first and second mutually type corresponding transistors (M1; M2) and a current mirror CM with third and fourth transistors (M3; M4) of opposite type of M1 and M2. To obtain an equilibrium with a constant transconductance of the first transistor, first and second negative feedback loops (L1; L2) are applied, one including the linear core circuit CC, the other including the current mirror CM. In a first setting one loop suppresses differences between first and second drain voltages (Vd1; Vd2) and the other loop suppresses differences between one of of the first and second drain voltage Vd1 and Vd2 and a reference voltage Vref. In the second setting, one loop suppresses differences between the first drain voltage Vd1 and the reference voltage Vref and the other loop differences between the second drain voltage Vd2 and the reference voltage Vref.