Patent ID: 11687365

Abstract:
A computational storage processor (CSP) is provided that includes the CSP comprising a plurality of submission queues (SQs), a plurality of computational storage functions (CSFs), a CSF controller, and a CSP controller, and a method of controlling the CSP is provided that includes directing a first submission queue entry (SQE) that is written to a first one of the plurality of SQs to the CSF controller, generating, by the CSF controller, one or more secondary SQEs based on the first SQE, each of the one or more secondary SQEs is directed to a respective one of the CSFs, writing, by the CSF controller, the one or more secondary SQEs to a second one of the plurality of SQs, directing each of the one or more secondary SQEs to an associated respective one of the CSFs, and for each of the one or more secondary SQEs, performing, by the associated respective one of the CSFs, an operation associated with the secondary SQE.