Patent ID: 10103841

Abstract:
A turbo decoder system decodes L-length digital data consisting of a systematic code and 1st and 2nd parity check codes, and includes a trellis controller obtaining the ratio of the bit-number Ep of the 1st/2nd parity check code to the bit-number D of an original systematic code and generating, based on the code rate of the digital data, a trellis control output indicating a target decoding trellis, which is selected by a turbo decoder to perform decoding operations. A zero-patch module patches zeros into the systematic code, and patches, based on the value of Ep/D, one or more zeros into the 1st/2nd parity check code so that parity check bits of the 1st/2nd parity check code and the zero-bit(s) form a periodically depunctured parity check code.