Patent ID: 10339200

Abstract:
A system for implementing a mixed radix fast fourier transformation is disclosed. The system includes a data source 202, a digit-reverse address generator 204, a data memory 206, a register array 208, a control unit 210, a butterfly extraction unit 212, a twiddle factor generator 214, and a computation unit 216. The data source 202 provides input data. The digit reverse address generator 204 processes the input data (i) to generate a digit reverse index and performs a digits reverse address calculation. The data memory 206 stores the input data. The register array 208 includes one or more registers that are configured to cache multiple data words. The control unit 210 includes of identifying butterfly operations and generate addresses for fetching/storing data. The butterfly extraction unit 212 extracts data samples. The twiddle factor generator 214 generates and outputs a twiddle factors based on the current radix and radix configuration. The computation unit 216 performs twiddle factor multiplications and the butterfly operations for current radix.