Patent ID: 10924122

Abstract:
A system and method for phase alignment of multiple PLLs are disclosed. The system comprises a plurality N of PLLs (PLL_1 . . . PLL_N) and a plurality N of phase detectors (DET_1 . . . DET_N). The plurality N of phase detectors and the plurality N of PLLs are connected in a loop such that an i-th phase detector (DET_i) is configured to receive an i-th feedback signal (FB_i) generated from the i-th PLL and an (i+1)-th feedback signal (FB_i+1) generated from the (i+1)-th PLL, and the N-th phase detector (DET_N) is configured to receive the first feedback signal (FB_1) generated from the first PLL and the N-th feedback signal (FB_N) generated from the N-th PLL. The an i-th phase detector (DET_i) is configured to generate an i-th adjustment signal indicating an i-th phase difference between the i-th and (i+1)-th feedback signals for adjusting a phase of the i-th or (i+1)-th PLL, wherein i=1, 2, 3, . . . N−1. The N-th phase detector (DET_N) is configured to generate a N-th adjustment signal indicating a N-th phase difference between the first and N-th feedback signals.