Patent ID: 10032906

Abstract:
The present invention concept relates to vertical field effect transistor and method of fabricating the same. A method of fabricating a vertical field effect transistor is provided as follows. A fin structure having a sidewall is formed on a substrate. A lower spacer, a gate pattern and an upper spacer surround a lower sidewall region, a center sidewall region and an upper sidewall region, respectively. The lower spacer, the gate pattern and the upper spacer are vertically stacked on each other along the sidewall of the fin structure. To form the lower spacer, a preliminary spacer layer is formed to surround the lower sidewall region of the fin structure; a doped region and an undoped region are formed in the preliminary spacer layer by doping partially impurities in the preliminary spacer using a directional doping process; and the undoped region of the preliminary spacer layer is removed so that the doped region of the preliminary spacer layer remains to form the lower spacer.