Patent ID: 10776280

Abstract:
A data storage device is provided. The data storage includes: a flash memory, a dynamic random access memory (DRAM), and a memory controller. The flash memory stores a logical-to-physical mapping (L2P) table that is divided into a plurality of group-mapping (G2P) tables, and includes a first logical unit number (LUN) and a second LUN that are respectively controlled by a first chip enable (CE) signal and a second CE signal. The memory controller receives a write command from a host, and forms super page data using logical pages of data in the write command. The memory controller reads one of the group-mapping tables from the first LUN or the second LUN to the DRAM after sequentially enabling the first CE signal and second CE signal to write a first portion and a second portion of the super page data to the first LUN and the second LUN.