Patent ID: 10192959

Abstract:
The present disclosure relates to a III-N based substrate for power electronic devices, comprising a base substrate, a III-N laminate above the base substrate and a buffer layer structure between the base substrate and the III-N laminate. The buffer layer structure comprises at least a first superlattice laminate and a second superlattice laminate above the first superlattice laminate. The first superlattice laminate comprises a repetition of a first superlattice unit which consists of a plurality of first AlGaN layers. The second superlattice laminate comprises a repetition of a second superlattice unit which consists of a plurality of second AlGaN layers. An average aluminum content of the first superlattice laminate is a predetermined difference greater than an average aluminum content of the second superlattice laminate, to improve the vertical breakdown voltage. The present disclosure also relates to a method for manufacturing a III-N based substrate for power electronic devices.