Patent ID: 10468426

Abstract:
A nonvolatile memory (“NVM”) bitcell with one or more active regions capacitively coupled to the floating gate but that are separated from both the source and the drain. The inclusion of capacitors separated from the source and drain allows for improved control over the voltage of the floating gate. This in turn allows CHEI (or IHEI) to be performed with much higher efficiency than in existing bitcells, thereby the need for a charge pump to provide current to the bitcell, ultimately decreasing the total size of the bitcell. The bitcells may be constructed in pairs, further reducing the space requirements of the each bitcell, thereby mitigating the space requirements of the separate capacitor/s. The bitcell may also be operated by CHEI (or IHEI) and separately by BTBT depending upon the voltages applied at the source, drain, and capacitor/s.