Patent ID: 10930737

Abstract:
A GaN field effect transistor (FET) including a plurality of transistor cells. A gate metal layer of a transistor cell includes a gate-drain overhang (width 0.2 um to 2.5 um) and a gate-source overhang (width 0.3 um to 1 um), and a widening at each narrow edge of the transistor cell, wherein the width of the widening of gate metal layer (150) is of 2-5 um. A metal (1) layer of the transistor sell extends beyond metal (0) layer. A last metal layer includes a drain plate and a source plate, each having a trapezoid form. More than two vias are located at a widening for connecting the gate metal layer to the gate bus. More than six vias distributed along the longitudinal dimension of the transistor cell connect metal (1) layer to metal (0) layer. A plurality of type 2 vias connect metal (1) layer to the last metal layer.