Patent ID: 10313157

Abstract:
An apparatus includes: a semiconductor die including a first I/O (input/output) pad, a second I/O pad, a switch, and an internal processor, wherein the switch is configured to short the first I/O pad to the second I/O pad when a logical signal is asserted; and a semiconductor package including a first bond pad configured to electrically connect to the first I/O pad, a second bond pad configured to electrically connect to the second I/O pad, a first port configured to electrically connect to a pin of a multi-lane, multi-mode connector, a second port configured to electrically connect to an external processor, a first routing path configured to electrically connect the first port to the first bond pad, and a second routing path configured to electrically connect the second port to the second bond pad, wherein the external processor is configured to process an electrical signal at the second port in accordance with a first protocol when the logical signal is asserted, and the internal processor is configured to process an electrical signal at the first I/O pad in accordance with a second protocol when the logical signal is de-asserted.