Patent ID: 10615225

Abstract:
A multi-layer cross point memory array includes a plurality of layers, each in turn with a plurality of word lines; a plurality of intersecting lines intersecting the word lines at a plurality of points; and a plurality of memory element-transistor stacks. Each of the latter is formed on the intersecting lines; each stack in turn includes a memory element; and a complementary pair of parallel-connected field effect selection transistors including a p-FET and an n-FET, each of which has a gate, a first drain-source terminal connected to a corresponding one of the intersecting lines, and a second drain-source terminal connected to a corresponding one of the memory elements. The gate of the p-FET and the gate of an n-FET in an adjacent stack are connected to the same word line; and the mirror image is true for the n-FET and a p-FET in the adjacent stack on the opposite side.