Patent ID: 10818334

Abstract:
A ferroelectric memory array includes (a) a driver circuit providing a first signal and a second signal; (b) word lines each providing a word line signal; and (c) memory array sections. Each memory array section may include: (a) bit lines; (b) plate line segments each associated with a corresponding one of the word line signals; (c) local plate line decoders, each local plate line decoder (i) being associated with one of the plate line segments, (ii) receiving the corresponding word line signal of the associated plate line segment, the first signal and the second signal, and (iii) providing predetermined voltages on the associated plate line segment according to the received word line signal, the first signal and the second signal; and (d) memory cells, each memory cells having one or more ferroelectric capacitor connected between one of the plate line segments and one of the bit lines. The predetermined voltages output from a local plate decoder may include a voltage of the word line signal, a power supply voltage, or one half the power supply voltage.