Patent ID: 11424757

Abstract:
A successive approximation register analog-to-digital converter (SAR ADC) with calibration function and a calibration method thereof are provided. The SAR ADC has at least one capacitor digital-to-analog converter (CDAC), having Nd capacitors corresponding to Nd bits; and a controller. The calibration method includes: coupling the capacitors of an i-th to an (Nd−1)-th bit to a first reference voltage, and generating a first digital code based an operation of the capacitors of an (i−1)-th bit to a 0-th bit; coupling the capacitors of an (i+1)-th bit to the (Nd−1)-th bit to the first reference voltage, coupling the capacitor of the i-th bit to a second reference voltage, and generating a second digital code based on the operation of the capacitors of the (i−1)-th bit to the 0-th bit; generating a capacitor weight of the capacitor of the i-th bit; and calibrating the SAR ADC based on the capacitor weight.