Patent ID: 11935960

Abstract:
Some embodiments include integrated memory. The integrated memory includes a first series of first conductive structures and a second series of conductive structures. The first conductive structures extend along a first direction. The second conductive structures extend along a second direction which crosses the first direction. Pillars of semiconductor material extend upwardly from the first conductive structures. Each of the pillars includes a lower source/drain region, an upper source/drain region, and a channel region between the lower and upper source/drain regions. The lower source/drain regions are coupled with the first conductive structures. Insulative material is adjacent sidewall surfaces of the pillars. The insulative material includes ZrOx, where x is a number greater than 0. The second conductive structures include gating regions which are spaced from the channel regions by at least the insulative material. Storage elements are coupled with the upper source/drain regions.