Patent ID: 10522388

Abstract:
An SOI IC includes a polysilicon/silicon plug extending through the buried insulation layer between a P-type handle layer and a P-type device layer. An N-type well region is formed in the device layer over the polysilicon/silicon plug, and then a high-voltage (HV) device is formed in the well region such that part of its drift region is located over the polysilicon/silicon plug. Doping of the well region, the polysilicon/silicon plug and the handle layer is coordinated to form a P-N junction diode that couples the HV device, by way of the polysilicon/silicon plug, to a ground potential applied to the handle layer, thereby increasing the HV device's breakdown voltage by expanding its depletion region to include the handle layer. The polysilicon/silicon plug grows in holes formed through the insulation layer during the epitaxial silicon growth process used to form the device layer.