Patent ID: 10410734

Abstract:
The present invention relates to a shift register configured of a plurality of stages applying two clock signals among four clock signals that are sequentially generated as an input and applying a start signal as the input, wherein a first stage charges the start signal to a P-node and outputs a first output signal and a first carry signal by using the voltage of the P-node as a driving voltage when a first clock signal is applied, and resets the P-node when a second clock signal is applied, a second stage pre-charges a start signal input to the first stage to the P-node, charges the first carry signal to the P-node, outputs a second output signal and a second carry signal by using the voltage of the P-node as the driving voltage when the second clock signal is applied, and resets the P-node when a third clock signal is applied, and a third stage and following stages pre-charge a carry signal of the second previous stage to the P-node, charge the carry signal of the previous stage to the P-node, output the output signal and the carry signal by using the voltage of the P-node as the driving voltage when the input clock signal secondly input to the P-node is input, and reset the P-node that is charged depending on the clock signal generated after the input clock signal.