Patent ID: 10148256

Abstract:
Provided are a signal generating circuit, a voltage conversion device, and a signal generating method configured to make a minimum unit of values that are respectively set in m (where m is a natural number equal to or greater than 2) generating units that periodically generate PWM signals corresponding to the setting values substantially smaller than an actual minimum unit. A CPU specifies, at every n periods of the PWM signals generated by the m generating units SG1, SG2, . . . SGm, a settable value closest to the sum of target values for n periods, determines (m×n) setting values for n periods based on a quotient and a remainder obtained by dividing the specified settable value by the product of m and n, and sets the determined values in the respective generating units SG1, SG2, . . . SGm, using phase-specific interrupt processes that are different from each other.