Patent ID: 10234932

Abstract:
The present disclosure describes methods, systems, and computer program products for a multiple-processor system. The multiple-processor system includes a plurality of central processing unit (CPU) cores. Each of the plurality of CPU cores is configured to operate in at least one of a plurality of CPU states. The plurality of CPU states includes a low-voltage memory retention (NAP) state, an active state, and a shut-off state. The NAP state includes a sleep state that retains state memory. The multiple-processor system also includes a voltage regulator that is configured to provide a NAP voltage to the plurality of CPU cores. The NAP voltage is sufficient for at least one of the plurality of CPU cores to retain state information and the NAP voltage is lower than an active state voltage. The multiple-processor system further includes a plurality of state control switches. Each of the plurality of state control switches connects the voltage regulator to one of the plurality of CPU cores.