Patent ID: 10593382

Abstract:
A memory device performs first training including a plurality of loop operations to align a main clock signal and a data clock signal, which are received from a memory controller. A method of operating the memory device includes generating division ratio information indicating a division ratio set based on a frequency ratio of the main clock signal to the data clock signal and transmitting the division ratio information to the memory controller to perform the first training. A first loop operation includes: receiving first phase control information, which is generated based on the division ratio information, from the memory controller, dividing the data clock signal based on the division ratio to generate a division data clock signal, selecting a first phase from among a plurality of phases based on the first phase control information, generating a first comparison target clock signal that is shifted from the division data clock signal by the first phase, comparing a phase of the first comparison target clock signal with a phase of the main clock signal, and transmitting a first phase comparison result to the memory controller.