Patent ID: 10879293

Abstract:
There is provided a solid-state imaging device capable of reducing the number of wiring layers and achieving downsizing with flexible layout designing. The solid-state imaging device includes a first semiconductor chip including a first electrode pad, first wiring connected to a first electrode pad through a first via, and a logic circuit, which are formed therein, and a second semiconductor chip connected to the first semiconductor chip and including a second electrode pad, second wiring connected to the second electrode pad through a second via, and a pixel array, which are formed therein. The first electrode pad and the second electrode pad are bonded as being shifted from each other on a bonding surface of the first semiconductor chip and the second semiconductor chip. A total length of the shifted and bonded first and second electrode pads in an extending-direction of the wiring having a longer pitch of the first and second wiring is twice or more of an extending-direction length of the wiring having the longer pith.