Patent ID: 11776628

Abstract:
The following disclosure is directed to mitigating issues related to semi-circle drain side select gate (SC-SGD) memory holes in memory structures. When a memory hole is cut, the channel and the charge trap layer of the memory hole cut. Further, the outer dielectric layer (used to shield the channel and the charge trap layer) is cut and partially removed. When the selected SC-SGD is selected for an operation (e.g., programming), the channel and the charge trap layer are exposed to neighboring electrical field from bias voltage applied to an unselected SC-SGD. To prevent or mitigate the effects of this electrical field, a negative bias voltage is applied to the unselected SC-SGD. Additionally, this disclosure is directed to self-compensating techniques for SC-SGD. For example, the memory structure can utilize the neighboring electric field during verify, program, and read operations, whether the neighboring electric field is relatively strong or weak.