Patent ID: 10074744

Abstract:
A control electrode GE1 is formed in a lower portion of a trench TR1 formed in a semiconductor substrate SUB, and a gate electrode GE2 is formed in an upper portion inside the trench TR1. An insulating film G1 is formed between the control electrode GE1 and a side wall and a bottom surface of the trench TR1, an insulating film G2 is formed between the side wall of the trench TR1 and the gate electrode GE2, and an insulating film G3 is formed between the control electrode GE1 and the gate electrode GE2. A region adjacent to the trench TR1 includes an n+-type semiconductor region NR for a source, a p-type semiconductor region PR for a channel formation, and a semiconductor region for a drain. A wiring connected to the control electrode GE1 is not connected to a wiring connected to the gate electrode GE2, and is not connected to a wiring connected to the n+-type semiconductor region NR for a source.