Patent ID: 10931291

Abstract:
An array of devices, such as transceivers on a satellite, each use a phase locked loop (PLL) system to maintain a local oscillator at a particular frequency that is synchronized to a reference clock signal (RCS), maintaining tight timing discipline among the PLL systems. Each PLL system includes a first delta sigma modulator (DSM) and a second DSM. During a first time, a divider uses output from the first DSM to divide output from a voltage controlled oscillator of the PLL system. The output from the divider is provided as feedback to a phase frequency detector (PFD) of the PLL system and is also provided to the clock input of the first DSM. The PFD accepts as input the RCS. The second DSM uses the RCS as clock input. At a second time, the PLL system transitions from the divider using output from the first DSM to the second DSM.