Patent ID: 11741641

Abstract:
A binary logic circuit for performing an interpolation calculation between two endpoint values E0 and E1 using a weighting index i for generating an interpolated result P, the values E0 and E1 being formed from Adaptive Scalable Texture Compression (ASTC) low-dynamic range (LDR) colour endpoint values C0 and C1 respectively, the circuit comprising: an interpolation unit configured to perform an interpolation between the colour endpoint values C0 and C1 using the weighting index i to generate a first intermediate interpolated result C2; and combinational logic circuitry configured to receive the interpolated result C2 and to perform one or more logical processing operations to calculate the interpolated result P according to the equation P=└((C2<<8)+C2+32)/64┘ when the interpolated result is not to be compatible with an sRGB colour space, and according to the equation P=└((C2<<8)+128·64+32)/64┘ when the interpolated result is to be compatible with an sRGB colour space.