Patent ID: 10872883

Abstract:
Memory circuit including a first word line, a first bit line, a second bit line, a first inverter, a second inverter, a P-type pass gate transistor and a pre-charge circuit. The first inverter is coupled to a first storage node. The second inverter is coupled to the first storage node and the first inverter. The P-type pass gate transistor is coupled between the first storage node and the first bit line. The P-type pass gate transistor is coupled to the first word line, the first inverter and the second inverter. The pre-charge circuit is coupled to the first bit line or the second bit line. The pre-charge circuit is configured to charge the first bit line or the second bit line to a pre-charge voltage responsive to a first signal. The pre-charge voltage is between a voltage of a first logical level and a voltage of a second logical level.