Patent ID: 11734017

Abstract:
Example embodiments relate to scheduling and processing sensor data across multiple digital signal processing (DSP) cores. A system may include DSP cores that are virtually arranged into a first segment and a second segment, each with DSP cores arranged in a linear order. The system may process sensor data using the DSP cores and a processing pipeline. DSP cores from the first segment are configured to initiate processing a first stage sequentially based on the linear order until all DSP cores are processing portions in parallel, collate outputs to produce a first stage output, and provide a first signal to the second segment based on producing the first stage output. Responsive to receiving the first signal, DSP cores from the second segment are configured to initiate processing the second stage sequentially based on the linear order until all DSP cores are processing portions in parallel, collate outputs to produce a second stage output, and provide a second signal based on producing the second stage output. The system may provide instructions based on a combination of the first stage output and the second stage output.