Patent ID: 10297296

Abstract:
A storage device capable of performing power gating is provided. A memory cell of the storage device includes a bistable circuit, a first transistor, a second transistor, and a backup circuit. The first transistor and the second transistor are electrically connected to a first bit line and a second bit line, respectively. A precharge circuit that precharges the first bit line and the second bit line with different voltages is provided. The backup circuit includes a retention node, an input node, an output node, a third transistor, a fourth transistor, and a capacitor. The third transistor controls electrical continuity between the retention node and the input node. A gate of the fourth transistor and a terminal of the capacitor are electrically connected to the retention node. The input node is electrically connected to one of nodes Q and Qb of the bistable circuit, and the output node is electrically connected to the other of the nodes Q and Qb of the bistable circuit.