Patent ID: 10438953

Abstract:
An integrated circuitry construction comprises a substrate comprising conductive nodes of integrated circuitry. A conductive line structure is above the conductive nodes. Elevationally-extending conductive vias are spaced longitudinally along the conductive line structure. The conductive vias individually directly electrically couple the conductive line structure to individual of the conductive nodes. The conductive line structure comprises conductive material directly electrically coupled to the conductive vias and extending between immediately-longitudinally-adjacent of the conductive vias. An upper insulative material is directly below the conductive material between the immediately-longitudinally-adjacent conductive vias. Doped or undoped semiconductor material directly is below the upper insulative material between the immediately-longitudinally-adjacent conductive vias. A lower insulative material is directly below the semiconductor material between the immediately-longitudinally-adjacent conductive vias. Other aspects, including method, are disclosed.