Patent ID: 10511467

Abstract:
An oscillator architecture with pulse-edge tuning to control the pulse rising and falling edges (such as for duty cycle correction), including a signal generator with a pull-up PMOS transistor coupled to a high rail, and a pull-down NMOS transistor coupled to a low rail. Pulse-edge tuning circuitry includes a high-side tuning PMOS transistor between the high rail and a source terminal of the pull-up PMOS transistor, and a low-side tuning NMOS transistor between the low rail and a source terminal of the pull-down NMOS transistor. Both tuning FETs are controlled for operation as a variable resistor by respective high-side and low-side DACs to provide tuning control signals to the tuning FETs. In an example application, the oscillator design is adapted for a direct conversion RF signal chain (TX and/or RX) including an I-Path and a Q-Path: the signal generator generates ±I and ±Q differential signal frequencies.