Patent ID: 10297507

Abstract:
A vertical FET structure includes a bottom source-drain region disposed on a substrate of the first type; a recessed first heterostructure layer disposed on the bottom source-drain region; a first fin disposed on the bottom source-drain region; a dielectric inner spacer disposed on the recessed first heterostructure; an outer spacer disposed on the inner spacer; a high-k and metal gate layer disposed on the outer spacer, the inner spacer, and the channel layer; an interlayer dielectric oxide disposed between the first fin and the outer spacer; a recessed second heterostructure layer disposed on top of the substrate of the first type and high-k and metal gate layer; a dielectric inner spacer disposed on the recessed second heterostructure layer; and a top source-drain region layer disposed on the dielectric inner spacer and recessed second heterostructure layer resulting in the vertical FET. A method for forming the vertical FET is also provided.