Patent ID: 11095275

Abstract:
Techniques are described for implementing a true-single-phase-clocking (TSPC) flop with loading functionality. For example, the a loadable TSPC flop can receive input signals, including at least a clock input signal, a SET signal, and a RESET signal. Responsive to one configuration of the input signals, the loadable TSPC flop operates in a normal mode, in which its output node toggles responsive to the clock input signal. Responsive to another configuration of the input signals, the loadable TSPC flop operates in a reset loading mode, such that the Qb output node is loaded and held to a predetermined reset value. Responsive to another configuration of the input signals, the loadable TSPC flop operates in a set loading mode, such that the Qb output node is loaded and held to a predetermined set value that is a complement of the predetermined reset value.