Patent ID: 10313001

Abstract:
A hybrid processor system for use on board a telecommunications multi-beam satellite is provided that is controllable by a network control center via one or more control channels. The system links to ground terminals by: providing uplink and downlink traffic channels on several satellite beams; routing atomic switched information blocks from the uplink traffic channels to the downlink traffic channels; and exchanging signaling data with the ground terminals on one or more uplink signaling channels and one or more downlink signaling channels. The atomic switched information blocks have the same given time duration and the same given baseband bandwidth. The hybrid processor system includes a burst switching processor and an on-board processor controller which is configured to store service information items indicative of: the given time duration and the given baseband bandwidth of the atomic switched information blocks; the respective uplink bandwidth, the respective uplink frequencies, a respective time length of the respective uplink time slots, and respective structure features of the respective uplink time frames and superframes of each uplink channel; the respective downlink bandwidth, the respective downlink frequencies, a respective time length of the respective downlink time slots, and respective structure features of the respective downlink time frames and superframes of each downlink channel; and quality of service and priority rules for serving the ground terminals. The on-board processor controller is further configured to extract, from incoming signaling data capacity requests sent by the ground terminals by demodulating and decoding the incoming signaling data.