Patent ID: 11139834

Abstract:
Disclosed herein is a decoder 10 for decoding a family of L rate compatible parity check codes, said family of parity check codes comprising a first code that can be represented by a bipartite graph having variable nodes, check nodes, and edges, and L−1 codes of increasingly lower code rate, among which the i-th code can be represented by a bipartite graph corresponding to the bipartite graph representing the (i−1)-th code, to which an equal number of ni variable nodes and check nodes are added, wherein the added check nodes are connected via edges with selected ones of the variable nodes included in said i-th code, while the added variable nodes are connected via edges with selected added check nodes only. The decoder comprising L check node processing units 14, among which the i-th check node processing unit processes only the check nodes added in the i-th code over the (i−1)-th code, wherein said L check node processing units 14 are configured to operate in parallel.