Patent ID: 11705485

Abstract:
A lateral double-diffused metal-oxide-semiconductor (LDMOS) transistor including a breakdown voltage clamp includes a drain n+ region, a source n+ region, a gate, and a p-type reduced surface field (PRSF) layer including one or more bridge portions. Each of the one or more bridge portions extends below the drain n+ region in a thickness direction. Another LDMOS transistor includes a drain n+ region, a source n+ region, a gate, an n-type reduced surface field (NRSF) layer disposed between the source n+ region and the drain n+ region in a lateral direction, a PRSF layer disposed below the NRSF layer in a thickness direction orthogonal to the lateral direction, and a p-type buried layer (PBL) disposed below the PRSF layer in the thickness direction. The drain n+ region is disposed over the PBL in the thickness direction.