Patent ID: 10720421

Abstract:
In a circuit portion, a p+-type diffusion region penetrates, in the depth direction, an n−-type base region on the front side of a base substrate and surrounds a MOSFET. In a protective element portion on the same substrate, a p++-type contact region, an n+-type diffusion region, and a p+-type diffusion region are selectively provided in a p+-type diffusion region on the front side of the base substrate. The p+-type diffusion region penetrates the p−-type diffusion region in the depth direction, on the outer periphery of the p−-type diffusion region. An n+-type source region, the p+-type diffusion region, the p++-type contact region, and the n+-type diffusion region are connected to a GND terminal. The rear surface of the substrate is connected to a VCC terminal. A snapback start voltage of a parasitic bipolar element of the protective element portion is lower than that of the circuit portion.