Patent ID: 10453860

Abstract:
Embodiments of methods of forming staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a first dielectric layer is formed on a substrate, and a first photoresist layer is formed on the first dielectric layer. A recess is patterned through the first dielectric layer to the substrate by cycles of trim-etch the first dielectric layer. Dielectric/sacrificial layer pairs are formed on the first dielectric layer and filling in the recess. A second photoresist layer is formed on the dielectric/sacrificial layer pairs. The dielectric/sacrificial layer pairs are patterned by cycles of trim-etch the dielectric/sacrificial layer pairs. A second dielectric layer is formed on the first dielectric layer and covering the patterned dielectric/sacrificial layer pairs. A memory stack including conductor/dielectric layer pairs is formed by replacing, with conductor layers, the sacrificial layers in the patterned dielectric/sacrificial layer pairs and the dielectric/sacrificial layer pairs in the recess.