Patent ID: 10930568

Abstract:
A semiconductor structure includes at least one non-self-aligned contact in a metallization layer and a fabrication method for forming the same are disclosed. The method includes forming gate metal in a gate stack on a substrate and forming a source-drain contact in a source-drain stack on the substrate. The gate stack and the source-drain stack are separated by a sidewall spacer. The method recesses the sidewall spacer thereby forming a trench. In the trench, a first outer metal liner and a second outer metal liner are recessed, horizontally enlarging the trench to form a widened trench over respective top surfaces of the recessed first outer metal liner, second outer metal liner, and sidewall spacer. The method then deposits dielectric material filling the widened trench and contacting the first inner metal core, the second inner metal core, the first outer metal liner, the second outer metal liner, and the sidewall spacer.