Patent ID: 11182236

Abstract:
A method of determining a probabilistic metric for random hardware failure for an electronic system, such as a microcontroller, which comprises element and safety mechanisms (SMs) is disclosed. The safety mechanisms include first layer safety mechanisms (FL-SMs) and second layer safety mechanisms (SL-SMs). A first layer safety mechanism may provide at least partial coverage of failure of a part and a second layer safety mechanism may provide at least partial coverage of failure of a first layer safety mechanism. The method comprises calculating a first set of probabilities (KSM_i) associated with the first layer safety mechanisms, calculating a second set of probabilities (KDVF_n) associated with direct violation faults in the parts and calculating a third set of probabilities (KIVF_n) associated with indirect violation faults in the parts. The method includes obtaining the value of probabilistic metric for random hardware failure in dependence on the first, second and third sets of probabilities.