Patent ID: 10515601

Abstract:
The present invention involves a GOA circuit for preventing clock signals from missing. The GOA circuit comprises a plurality of cascaded GOA units. The N-th stage GOA unit comprises a pull-high stage-transfer unit, a pull-down unit, and a pull-down sustain unit, which are respectively connected with a first node (Q(N)) and a gate signal output terminal (G(N)) of the N-th stage GOA unit. The pull-high control unit is connected with the first node (Q(N)) of the N-th stage GOA unit. From a specific stage, each of the GOA unit further comprises an additional circuit for preventing clock signals from missing. The additional circuit is connected with the pull-down sustain unit. When the clock signal is missing, the additional circuit utilizes the start signal (STV), a first low-frequency clock signal (LC1), and the second low-frequency clock signal (LC2) which are capable of lowering the potential of the first node (Q(N)) of the N-th stage GOA unit. The GOA circuit for preventing clock signals from missing of the present invention, which is capable of solving the problem that the display signal is damaged due to the disappearance of the clock signal.