Patent ID: 10050025

Abstract:
A power converter (100) comprising a semiconductor chip (101) with a first (101a) and a parallel second (101b) surface, and through-silicon vias (TSVs, 110). The chip embedding a high-side (HS) field-effect transistor (FET) interconnected with a low side (LS) FET. Surface (101a) includes first metallic pads (111) as inlets of the TSVs, and an attachment site for an integrated circuit (IC) chip (150). Surface (101b) includes second metallic pads (115) as outlets of the TSVs, and third metallic pads as terminals of the converter: Pad (123a) as HS FET inlet, pad (122a) as HS FET gate, pad (131a) as LS FET outlet, pad (132a) as LS FET gate, and gate (140a) as common HS FET and LS FET switch-node. Driver-and-controller IC chip 150) has the IC terminals connected to respective first pads.