Patent ID: 11943940

Abstract:
A nanostructured cross-wire memory architecture is provided that can interface with conventional semiconductor technologies and be electrically accessed and read. The architecture links lower and upper sets of generally parallel nanowires oriented crosswise, with a memory element that has a characteristic conductance. Each nanowire end is attached to an electrode. Conductance of the linkages in the gap between the wires encodes the information. The nanowires may be highly-conductive, self-assembled, nucleic acid-based nanowires enhanced with dopants including metal ions, carbon, metal nanoparticles and intercalators. Conductance of the memory elements can be controlled by sequence, length, conformation, doping, and number of pathways between nanowires. A diode can also be connected in series with each of the memory elements. Linkers may also be redox or electroactive switching molecules or nanoparticles where the charge state changes the resistance of the memory element.