Patent ID: 10916544

Abstract:
The present invention provides a Gate-All-Around nano-sheet complementary inverter, comprising: P-type semiconductor transistors and N-type semiconductor transistors, wherein the P-type semiconductor transistors comprise P-type semiconductor nano-sheet channels, a first gate dielectric layer fully surrounding the P-type semiconductor nano-sheet channels, a first gate electrode layer fully surrounding the first gate dielectric layer, a first source region and a first drain region, connected to two ends of the P-type semiconductor nano-sheet channel respectively, the N-type semiconductor transistors comprise N-type semiconductor nano-sheet channels, a second gate dielectric layer fully surrounding the N-type semiconductor nano-sheet channels, a second gate electrode layer fully surrounding the second gate dielectric layer, a second source region and a second drain region, connected to two ends of the N-type semiconductor nano-sheet channel respectively; and a common electrode fully surrounding the first gate electrode layer and the second gate electrode layer; wherein the P-type semiconductor nano-sheet channels and the N-type semiconductor nano-sheet channels are laterally aligned, and the width of the P-type semiconductor nano-sheet channel is greater than that of the N-type semiconductor nano-sheet channel The structure of the disclosed device is compact enough to increase the density and improve the performance and simple enough to produce.