Patent ID: 10546645

Abstract:
A non-volatile memory system includes an array of bit cells arranged in rows and columns and configured to store bits of data, a reference bit cell, a plurality of bit lines connectable to the bit cells in the array and connecting to the reference bit cell, and a bit line controller. The bit line controller comprises a plurality of sense amps connected to the bit cells by the bit lines. The bit line controller determines the contents of the bit cells based on times tcell compared to a time tref, where tcell is the time required for a current Icell generated by one of the bit cells to raise a voltage Vsense of one of the sense amps by an amount ΔV, and tref is the time required for a current Iref generated by the reference bit cell to raise the voltage Vsense of another one of the sense amps by the same ΔV. ΔV increases monotonically as a function of Iref.