Patent ID: 11403518

Abstract:
A neural network circuit includes: a storage portion that includes memristors; D/A converters; drive amplifiers; I/V conversion amplifiers; A/D converters; and offset correctors. The offset corrector includes a first latch circuit, a second latch circuit, a subtractor that subtracts latch data, and a controller. In performing a bias setting operation, the controller controls a bias application amplifier to output the bias voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output a reference voltage, and also cause the first latch circuit to latch the output data. In performing a normal operation, the controller controls the bias application amplifier to output the reference voltage, controls each of the D/A converters to cause the drive amplifier other than the bias application amplifier to output the signal voltage, and also cause the second latch circuit to latch the output data.