Patent ID: 10211092

Abstract:
Fabricating a transistor includes receiving a semiconductor structure including a source/drain, a gate, and a spacer disposed between the source/drain and the gate, a trench contact disposed on the source/drain, a self-aligned cap disposed on the gate, and an interlevel dielectric layer disposed on the spacer, self-aligned cap, and trench contact. A source/drain contact is formed within the interlevel dielectric layer in contact with the trench contact and forming a gate contact in contact with the gate. The interlevel dielectric layer is removed from the spacer, self-aligned cap, and source/drain contact. The self-aligned cap and the spacer is selectively etched. A dielectric liner of a first dielectric material is deposited upon a top of the gate, the trench contact and the S/D contact. The first dielectric material of the dielectric liner pinches off a gap between the gate and the trench contact to form an air spacer therebetween.