Patent ID: 10319730

Abstract:
A memory device according to an embodiment includes: a stacked film having a plurality of semiconductor films, and a plurality of insulating films each provided between the semiconductor films; a first electrode provided above the stacked film; a second electrode provided above the stacked film; a plurality of first conductive pillars penetrating through the stacked film and having one end electrically connected to the first electrode and another end not connected and positioned below the stacked film; a plurality of memory cells each provided between each of the first conductive pillars and each of the semiconductor films; a plurality of second conductive pillars electrically connected to each of the semiconductor films and the second electrode; a peripheral circuit board provided above the first electrode and the second electrode; a third electrode provided between the first electrode and the peripheral circuit board, the third electrode electrically connected to the first electrode; a fourth electrode provided between the second electrode and the peripheral circuit board, the fourth electrode electrically connected to the second electrode; and a transistor electrically connected to the third electrode or the fourth electrode, the transistor provided in the peripheral circuit board.