Patent ID: 10831959

Abstract:
An advanced timing mode has a path that originates from a host application-specific integrated circuit (ASIC) and terminates at a register inside an embedded field programmable gate array (FPGA), bypassing interface cluster registers. The terminating register may be present at a boundary between the host ASIC and the embedded FPGA or deep inside the embedded FPGA. In a clock trunk input with internal divergence timing scenario, a clock output from a phase-locked loop (PLL) in the host ASIC is driven through a clock trunk into the embedded FPGA and, from there, diverges into interface cluster registers and the boundary adjacent to the host ASIC. A clock trunk input with external divergence timing scenario is similar to the internal divergence scenario except that a clock divergence occurs before the clock enters a clock trunk of the embedded FPGA. In a boundary clock input scenario, a PLL drives both the host ASIC and the embedded FPGA interface clusters.