Patent ID: 10644835

Abstract:
An apparatus includes: a cyclic redundancy check (CRC) encoder configured to receive k information bits and generate p parity bits corresponding to the k information bits, k and p being positive integers; and an interleaver configured to output an interleaved bit sequence, in which the k information bits are interleaved with the p parity bits. The interleaved bit sequence includes a first subset of the k information bits appended with a first parity bit of the p parity bits and a second subset of the k information bits appended with a second parity bit of the p parity bits. The first subset of the k information bits is located earlier than the second subset of the k information bits in the interleaved bit sequence. The second subset of the k information bits and all of preceding information bits in the interleaved bit sequence including the first subset of the k information bits deterministically correlate the second parity bit of the p parity bits.