Patent ID: 10812100

Abstract:
A DAC (60) is disclosed. It comprises an input port comprising N input terminals p1, p2, . . . , pN configured to receive voltages representing N input bits b1, b2, . . . , bN, respectively, wherein the significance of bj is higher than for bj−1 for j=2, 3, . . . , N. Furthermore, it comprises a capacitor ladder circuit (100) comprising N capacitors C1, C2, . . . , CN with capacitance C, each having a first terminal and a second terminal. Capacitor Cj is connected with its first terminal to the terminal pj of the input port. For each j=1, 2, . . . , N−1, the capacitor ladder circuit (100) comprises a capacitor (150j) with capacitance xC connected between the second terminal of capacitor Cj and the second terminal of capacitor Cj+1. The DAC (60) also comprises an input circuit (140) connected to the input port comprising at least one capacitor (1601-160N), each connected between a unique one of the input terminals p1, p2, . . . , pN of the input port and signal ground.