Patent ID: 10880511

Abstract:
An image sensor is proposed to have a stack with at least a pixel array tier and a control logic tier. The pixel array tier comprises an array of pixels which are arranged into pixel columns n, each pixel column n comprising a number of N sub-columns: Each sub-column is denoted by N(n,i) with 1≤i≤N. The control logic tier comprises an array of analog-to-digital-converters which are arranged into ADC columns m, wherein each analog-to-digital converter comprises a number of M stages. Each stage is denoted by M(m,j) with 1≤j≤M, Furthermore, each respective sub-column N(n,i) is electrically connected to a dedicated stage M(m,j=i) and the stages M(m,j) are electrically interconnected to form the analog-to-digital converters, respectively. The control logic tier is arranged to sequentially read out the sub-columns N(n,i), wherein the stages M(m,j=i) dedicated to the sub-columns N(n,i) are arranged as input stages to sequentially receive signal levels of the pixels in the sub-columns N(n,i), respectively. The input stages are arranged to perform on the sequentially received signal levels a coarse first analog-to-digital conversion. The remaining stages M(m,j≠i) are arranged to sequentially perform finer analog-to-digital conversions of the received signal levels.