Patent ID: 11965961

Abstract:
For direct chip-on-array for a multi-dimensional transducer array, the generally rigid and conductive dematching layer is extended beyond a footprint of the transducer array. The ASIC is directly connected to the dematching layer on one side, while the other side provides for electrical connection to the elements of the array and I/O pads for connections (e.g., flex-to-dematching layer) to the ultrasound imaging system. By using the dematching layer rigidity, the ASIC may be protected during formation of the acoustic stack. By using the dematching layer conductivity, any mis-alignment is compensated by the routing through the dematching layer, and/or a large flat region is provided for I/O, allowing for good low temperature asperity contact connections with larger area than flip-chip solder bumps. By providing the I/O for the system connections on a different side of the dematching layer than the ASIC, a large keep-out distance due to underfill may be avoided.