Patent ID: 11587872

Abstract:
Configurations of metal layers of interconnect structures are disclosed herein that can improve memory performance, such as static random-access memory (SRAM) memory performance, and/or logic performance. For example, embodiments herein place bit lines in a metal one (M1) layer, which is a lowest metallization level of an interconnect structure of a memory cell, to minimize bit line capacitance, and configure bit lines as the widest metal lines of the metal one layer to minimize bit line resistance. In some embodiments, the interconnect structure has a double word line structure to reduce word line resistance. In some embodiments, the interconnect structure has a double voltage line structure to reduce voltage line resistance. In some embodiments, jogs are added to a word line and/or a voltage line to reduce its respective resistance. In some embodiments, via shapes of the interconnect structure are configured to reduce resistance of the interconnect structure.