Patent ID: 10663821

Abstract:
An array board includes input terminals, a first interlayer insulating film, a first planarization film, terminal lines, a second planarization film, and protective members. A first interlayer insulating film edge section and a first planarization film edge section are disposed between the input terminals and the display area. The terminal lines in a layer upper than the first planarization film and extending to cross the first interlayer insulating film edge section and the first planarization film edge section are connected to the input terminals. The second planarization film in a layer upper than the terminal lines includes a second planarization film edge section disposed closer to the input terminals relative to the first interlayer insulating edge section and the first planarization film edge section. The protective members in a layer upper than the second planarization film cover sections of the terminals lines not overlapping the second planarization film, respectively.