Patent ID: 10418101

Abstract:
In one embodiment, a device includes a memory cell for storing “0” or “1” as stored data, and a control circuit for reading out the stored data. The memory cell includes area C1/C3 where a cell current increases as a voltage across the cell increases, area C2/C4 where the current is larger than that in C1/C3 and the voltage decreases while the current increases, and area C5 where the current is larger than that in C2/C4 and increases as the voltage increases. The control circuit performs first processing of reading out the stored data such that the current when the data is “0” and the current when the data is “1” take values in C1/C3, and second processing of reading out the stored data such that the current when the data is “0” or the current when the data is “1” takes a value in C2/C4 or C5.