Patent ID: 10649732

Abstract:
This application relates to apparatus and methods for the multiplication of signals. A multiplication circuit (100) has first and second time-encoding modulators (103a, 103b) configured to receive first and second combined signals (SC1, SC2) respectively, and generate respective first and second PWM signals (SPWM1, SPWM2), each with a cycle frequency that depends substantially on the square of the value of the input combined signal. The first combined signal (SC1) corresponds to a sum of a first and second input signals (S1, S2) and the second combined signal (SC2) corresponds to the difference between the first and second input signals (S1, S2). First and second time-decoding converters (104a, 104b) receive the first and second PWM signals and provide respective first and count values (D1, D2) based on a parameter related to the frequency of the respective first or second PWM signal. A subtractor (105) determine a difference between the first and second count values (D1, D2) and provides an output signal (DOUT) based on this difference.