Patent ID: 10804400

Abstract:
This disclosure relates to a semiconductor structure for, e.g., a high-k metal gate fin field-effect transistor, and a manufacturing method therefor. The method may include providing a substrate structure including a first portion for forming a first PMOS device and a second portion for forming a second PMOS device; forming a first P-type work function adjustment layer on the substrate structure; forming a protective layer on the first P-type work function adjustment layer; patterning the protective layer to expose the first P-type work function adjustment layer on the first portion; oxidizing the exposed first P-type work function adjustment layer on the first portion; removing the protective layer; and forming a second P-type work function adjustment layer on the first P-type work function adjustment layer. Because the first P-type work function adjustment layer on the first portion is oxidized, gate voltage thresholds of the first portion and the second portion are different even when the thicknesses of metal layers on the first portion and the second portion are the same.