Patent ID: 10373795

Abstract:
Provided are new techniques for fault analysis in IC semiconductor devices, including system designs and methods to enable the probing of circuitry within an IC device under test (DUT) using electron beam (e-beam) techniques while the DUT is being stimulated electrically, or while the device is active on its own or within a host system mounted in a circuit board or other module. The DUT could be a packaged IC, or an IC in some unpackaged form. To create a local evacuated volume immediately outside the e-beam tool, a sealing element is sealed against or around the DUT for a localized seal. Such an arrangement obviates the need for vacuum feedthroughs of possibly thousands of signals required to operate and monitor the DUT, and further enables probing of a DUT while it is operating in its normal environment, such as installed on a circuit board in its system, or on a tester.