Patent ID: 11894301

Abstract:
A vertical memory device includes a cell stacked structure, a wiring connection structure, and a first insulating interlayer. The cell stacked structure may include insulation layers and gate patterns repeatedly and alternately stacked on a first region of a substrate. The wiring connection structure may contact side walls of the cell stacked structure. The wiring connection structure may include a first staircase structure having one side of a stepped shape, a second staircase structure having one side of a stepped shape and disposed below the first staircase structure, and a first dummy staircase structure between the first and second staircase structures. The first and second staircase structures may be spaced apart from each other in the first direction, and both sides in the first direction of the first dummy staircase structure may have stepped shapes. The first insulating interlayer may be on the substrate to cover the wiring connection structure.