Patent ID: 11664824

Abstract:
According to certain embodiments, a method is provided for fast layered decoding for Low-density Parity-Check (LDPC) codes with a Parity-Check Matrix (PCM) that includes at least a first layer and a second layer. The method includes reading, from a memory, Variable Node (VN) soft information, wherein the VN soft information is associated with a message from a VN to a Check Node (CN) of the second layer of the PCM. A new CN to VN message is calculated from the CN of the second layer of the PCM. New VN soft information is calculated for the VN. The new VN soft information is calculated based on the VN soft information and a new CN to VN message from a CN of the first layer to the VN and an old CN to VN message from the CN of the first layer to the VN such that the updating of new VN soft information is delayed by at least one layer. The fast layered decoding has lower decoding latency and utilizes the decoding hardware more efficiently than standard layered decoding techniques. This may be achieved by keeping the memory access and processing hardware units active simultaneously to avoid excess decoding latency. More specifically, certain embodiments may carry out memory access and computation process simultaneously, without any effort to make the row layers mutually orthogonal to each other. Another technical advantage may be that the proposed decoding algorithm adjusts the LLRs to partially account for deviations from the layered decoding due to non-orthogonal rows.