Patent ID: 10102000

Abstract:
An apparatus and method are described for performing split lock operations in a multi-core processor. For example, one embodiment of a processor comprises: a plurality of cores to execute instructions, each core comprising a core cache to cache data during instruction execution; a shared cache to be shared by two or more of the plurality of cores; a locking agent on a first core to initiate a split lock operation in response to detecting a transaction targeting at least two cache lines, the locking agent to transmit a request for the two cache lines to be set to an Exclusive state; at least one coherence enforcement engine to receive the request from the locking agent and to responsively cause any copies of the two cache lines in other cores to be invalidated; the locking agent to permit the transaction targeting the two cache lines to complete upon receipt of an indication that the cache lines are in the Exclusive state and, upon completion of the transaction, to transmit an indication that the transaction is complete to the coherence enforcement engine.