Patent ID: 11749225

Abstract:
A unit circuit constituting each stage of a shift register serving as a gate driver of a display device charges an internal node to an H level via a transistor T2 when an output signal G(n−4) of a preceding stage turns to the H level and sets the internal node to an L level via a transistor T3 when an output signal G(n+8) of a succeeding stage turns to the H level. Each of the unit circuits of last eight stages in the gate driver is provided with a transistor T4 including a gate terminal to which the signal G(n−4) is applied and a drain terminal connected to the internal node. A signal is applied to a source terminal of the transistor T4, the signal being at the H level during a period when the internal node of any of the last eight stages is to be set to the H level, and being the L level during the other periods. This suppresses a voltage fluctuation generated in the internal node when a stabilization circuit does not normally function.