Patent ID: 10862496

Abstract:
Apparatus and associated methods relate to a logic circuit having a number of unit circuits performing buffering and data storage functionalities in parallel. In an illustrative example, a logic circuit may include N unit circuits for data storage and N−1 unit circuits for buffering. During a conversion cycle, only an ith unit circuit of the N unit circuits and an (i−1)th unit circuit of the N−1 unit circuits may be enabled. Output status of the ith unit circuit of the N unit circuits may be monitored to disable the ith unit circuit, and also enable an (i−1)th unit circuit of the N unit circuits and an (i−2)th unit circuit of the N−1 unit circuits. By performing buffering and data storage in parallel, propagation delays in the SAR logic circuit may advantageously be reduced, and thus, conversion time of a successive-approximation-register (SAR) analog-to-digital converter (ADC) may be advantageously reduced.