Patent ID: 11488981

Abstract:
An array of vertical transistors comprises spaced pillars of individual vertical transistors that individually comprise an upper source/drain region, a lower source/drain region, and a channel region vertically there-between. The upper source/drain region comprises a conductor oxide material in individual of the pillars. The channel region comprises an oxide semiconductor material in the individual pillars. The lower source/drain region comprises a first conductive oxide material in the individual pillars atop and directly against a second conductive oxide material in the individual pillars. Horizontally-elongated and spaced conductor lines individually interconnect a respective multiple of the vertical transistors in a column direction. The conductor lines individually comprise the second conductive oxide material atop and directly against metal material. The first conductive oxide material, the second conductive oxide material, and the metal material comprise different compositions relative one another. The second conductive oxide material of the conductor lines is below and directly against the second conductive oxide material of the lower source/drain region of the individual pillars of the respective multiple vertical transistors. Horizontally-elongated and spaced conductive gate lines are individually operatively aside the oxide semiconductor material of the channel region of the individual pillars and individually interconnect a respective plurality of the vertical transistors in a row direction. A conductive structure is laterally-between and spaced from immediately-adjacent of the spaced conductor lines in the row direction. The conductive structures individually comprise a top surface that is higher than a top surface of the metal material of the conductor lines. Other embodiments, including method, are disclosed.