Patent ID: 11329652

Abstract:
Techniques are described for implementing counter architectures to support high-speed, high-resolution pixel conversions, such as for CMOS image sensor applications. Embodiments implement a counter block that uses loadable true-signal-phase-clocking (L-TSPC) flops for at least a portion of the counter flops. Some embodiments support efficient two-phase pixel conversion by integrating counting, subtraction, and shifting out in the counter. For example, embodiments can perform a first high-speed pixel conversion phase to obtain a first conversion count. Prior to a second phase, the initial counter can be pre-subtracted by the amount of the first conversion count. Embodiments can then perform a second high-speed pixel conversion phase to obtain a second conversion count. As the second conversion count already has the first conversion count pre-subtracted, the second conversion count represents the final two-phase conversion result. Embodiments can read out this final two-phase conversion result as a digital output of the counter.