Patent ID: 11756794

Abstract:
A method of fabricating an IC includes forming a layer stack thereon including silicon nitride layer on a first silicon oxide layer, with a second silicon oxide layer thereon on a substrate including a semiconductor material. The layer stack is etched to form ≥1 trench that is at least 2 microns deep into the semiconductor material. A dielectric liner is formed on sidewalls and a bottom of the trench. A polysilicon layer is formed on the dielectric liner that fills the trench and extends lateral to the trench. Chemical mechanical planarization (CMP) processing stops on the silicon nitride layer to remove the polysilicon layer and the second silicon oxide layer to form a trench structure having a polysilicon fill. After the CMP processing, thermal oxidation oxidizes exposed regions of the polysilicon layer to form a polysilicon oxide layer. After the thermal oxidizing, the silicon nitride layer is removed.