Patent ID: 11683039

Abstract:
A NOT logic circuit is provided comprising: one or more memory devices; wherein a first memory address location of the one or more memory devices stores first content data, wherein the first content data includes a first ternary value and a corresponding first priority value, wherein the first ternary value includes a continuous sequence of X-state values that represent a first range of non-X ternary values; wherein a second memory address of the one or more memory device stores second content data that includes a second ternary value and a corresponding second priority value, wherein the second ternary value includes a continuous sequence of non-X state values represent a non-X ternary value that is within the first range of non-X ternary values; an interface is coupled to receive a ternary value from a processing device; comparator circuitry operable to compare a received ternary key with the outputted first ternary value and to compare the received ternary key with the outputted second ternary value; priority encoder logic operable to, return the outputted first priority value on a condition that the received ternary key matches the first ternary value and the received ternary key does not match second ternary value, and return the outputted second priority value on a condition that the received ternary key matches the first ternary value and that the received ternary key matches the second ternary value; and detection logic operable to send a return to the processing device on a condition of a return of the first priority value.