Patent ID: 10141440

Abstract:
Apparatus and associated methods relate to controlling an electric field profile within a drift region of an LDMOS device using biased field plates to deplete majority carriers from a drift region between a body/drift-region metallurgical junction and a drain contact. Such field plates are located in trenches that longitudinally extend within the drift region. Field plates are laterally spaced apart from each other at a distance that permits substantial depletion of majority carriers between adjacent field plates. Trenches have trench bottoms located within a drift-region/substrate metallurgical junction so as to permit substantial depletion of majority carriers between trench bottoms and the drift-region/substrate metallurgical junction. Between adjacent trenches, dopant concentrations can be increased up to a threshold that can be substantially depleted under specified bias conditions. Such control of the electric field profile within the drift region may advantageously optimize a breakdown-voltage/on-resistance characteristic of the LDMOS device.