Patent ID: 10234892

Abstract:
A method and circuit are provided to reduce power consumption of high-speed clocks that are distributed across an integrated circuit (IC). Example implementations seek to reduce the amount of power dissipated in typical clock distribution networks by turning the combination of a multi-port electrical network and transmission line into a multi-resonant structure. In an implementation, the multi-port electrical network is coupled between first and second segments of the transmission line. The multi-port electrical network includes series and shunt reactive circuit elements, such as series inductive reactance and a shunt inductive susceptance, configured to produce first and second resonances that cooperate to create a bandpass response across clock distribution frequencies. This bandpass response is created by the multi-resonant structure, which is a combination of the transmission line and the multi-port electrical network. Various implementations are provided, including single-ended, differential, multi-section, multi-output, and point-to-multi-point implementations, each with an optional low-speed mode switch.