Patent ID: 11710634

Abstract:
A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.