Patent ID: 11322491

Abstract:
An integrated grid cell on an integrated circuit (IC) is disclosed. The integrated grid cell corresponds to at least one of an integrated one-grid cell and an integrated two-grid cell. The integrated grid cell includes various polysilicon layers, metal-0 oxide diffusion (M0OD) layers, and a metal-0 polysilicon (M0PO) layer. The polysilicon layers, the M0OD layers, and the M0PO layer are formed such that potential differences are created between one or more polysilicon layers and one or more M0OD layers. Such potential differences between the one or more polysilicon layers and the one or more M0OD layers lead to formation of various parasitic capacitors between the one or more polysilicon layers and the one or more M0OD layers. The parasitic capacitors correspond to decoupling capacitors that mitigate a dynamic IR drop and a supply noise associated with the IC.