Patent ID: 11011416

Abstract:
A semiconductor structure and a method for forming a semiconductor structure are provided. One form of the method includes: providing a base, a bottom dielectric layer formed on the base, and an interconnecting wire located within the bottom dielectric layer, where the bottom dielectric layer exposes a top of the interconnecting wire; etching a portion of a thickness of the bottom dielectric layer, along an extending direction of the interconnecting wire, where adjacent interconnecting wires and a remainder of the bottom dielectric layer form a groove; forming an etch stop layer at least in the groove, the etch stop layer sealing a top of the groove; forming a top dielectric layer covering the interconnecting wire, the etch stop layer, and the bottom dielectric layer; forming a via within top dielectric layers on both sides of the groove, the via exposing the top of the interconnecting wire; forming a via interconnecting structure filling the via, the via interconnecting structure being electrically connected to the interconnecting wire. Embodiments and implementations of the present disclosure provide reliability and stability of the semiconductor structure while enlarging a process window for forming the via and improving a degree of freedom of a layout design of the via interconnecting structure.