Patent ID: 10607887

Abstract:
Embodiments of methods and structures for forming a 3D integrated wiring structure are disclosed. The method can include forming a dielectric layer in a contact hole region at a front side of a first substrate; forming a semiconductor structure at the front side of the first substrate and the semiconductor structure having a first conductive contact, forming a recess at a backside of the first substrate to expose at least a portion of the dielectric layer; and forming a second conductive layer above the exposed dielectric layer to connect the first conductive contact. The 3D integrated wiring structure can include a first substrate having a contact hole region; a dielectric layer disposed in the contact hole region; a semiconductor structure formed at the front side of the first substrate, having a first conductive contact; a recess formed at the backside of the first substrate to expose at least a portion of the dielectric layer; and a second conductive layer above the exposed dielectric layer.