Patent ID: 11362173

Abstract:
Present disclosure provide a capacitor includes: a semiconductor substrate; a laminated structure including n conductive layers and m dielectric layer(s), the i-th conductive layer being provided with at least one i-th isolation trench, the (i+1)-th conductive layer being provided above the i-th conductive layer and in the i-th isolation trench, isolation trenches in odd-numbered and even-numbered conductive layers having a first and a second overlap region in a vertical direction respectively, and the first overlap region not overlapping the second overlap region, where m, n, and i are positive integers, n≥2, and 1≤i≤n−1; at least one first external electrode electrically connected to all odd-numbered conductive layer(s) through a first conductive via structure in the second overlap region; and at least one second external electrode electrically connected to all even-numbered conductive layer(s) through a second conductive via structure in the first overlap region.