Patent ID: 10978298

Abstract:
Disclosed is a process for producing semiconductor nanowires having a diameter or thickness from 2 nm to 100 nm, the process comprising: (A) preparing a semiconductor material particulate having a size from 50 nm to 500 μm, selected from Ga, In, Ge, Sn, Pb, P, As, Sb, Bi, Te, a combination thereof, a compound thereof, or a combination thereof with Si; (B) depositing a catalytic metal, in the form of nanoparticles having a size from 1 nm to 100 nm or a coating having a thickness from 1 nm to 100 nm, onto surfaces of the semiconductor material particulate to form a catalyst metal-coated semiconductor material; and (C) exposing the catalyst metal-coated semiconductor material to a high temperature environment, from 100° C. to 2,500° C., for a period of time sufficient to enable a catalytic metal-assisted growth of multiple semiconductor nanowires from the particulate.