Patent ID: 10840251

Abstract:
A static random access memory device includes a write circuit, a read port circuit, and a substrate. The write port circuit includes a first inverter, a second inverter cross-coupled with the first inverter, a first pass-gate transistor coupled to the first inverter, and a second pass-gate transistor coupled to the second inverter. The read port circuit includes a read pull-down transistor and a read pass-gate transistor that are coupled in series to each other. The substrate includes a standard threshold voltage (STV) region and a low threshold voltage (LVT) region abutting the STV region. The write port circuit is formed within the STV region, and the read port circuit is formed within the LVT region. The LVT region has a first boundary at an edge of a gate of the first pass-gate transistor, or approaching the edge of the gate of the first pass-gate transistor.