Patent ID: 11081411

Abstract:
A semiconductor structure (100; 200) is provided. The semiconductor structure (100; 200) comprises a substrate (5); a plurality of test structures (101, 102, 201, 202) on the substrate, wherein the plurality of test structures comprise a first set of test structures (101, 102) and a second set of test structures (201, 202); a plurality of test electrodes (10, 20, 30) provided on the substrate, wherein the test electrodes comprise a first set of electrodes (10) operatively connected to the first set of test structures (101, 102), and a second set of electrodes (20) operatively connected to the second set of test structures (201, 202), wherein the first set of electrodes (10) are spaced apart from one another by a predetermined pitch and are configured to be operatively connectable to a probe card (8) having a plurality of probe pins (7) spaced apart from one another by the predetermined pitch to test the first set of test structures, and wherein the second set of electrodes (20) are spaced apart from one another by the predetermined pitch and are configured to be operatively connectable to the probe card (8) to test the second set of test structures; and wherein at least one electrode within the second set of electrodes (20) is disposed between adjacent electrodes within the first set of electrodes (10) along a length of the first set of electrodes (V).