Patent ID: 10461764

Abstract:
A system and method are provided for calibrating an interleaved digital-to-analog converter (DAC). Sets of sub-DACs are enabled, and by creating a high frequency fundamental signal, spurs can be driven down sufficiently low in frequency to be sampled and digitally converted. By minimizing the power of these digital signals, the duty cycles of the different clock phases are calibrated. Then, sets of sub-DACs are enabled and high pass filtered, so that the spurs can be downconverted using corresponding phases of the clock, to a frequency low enough to sampled and digitally converted. The power of the digital signals is minimized as a first step in phase calibration. As a final step, all the sub-DACs are enabled, the high pass filter removed, and a high frequency fundamental signal is downconverted using at least two clock phases, so that the phase difference can be measured and corrected.