Patent ID: 11069694

Abstract:
A semiconductor structure and a method for forming same are provided. In one form a method includes: providing a substrate with a discrete first gate laminated structure formed on the substrate; forming, on a portion of the substrate exposed from the first gate laminated structure, a unit dielectric layer covering a portion of a side wall of the first gate laminated structure, where the first gate laminated structure and the unit dielectric layer enclose a unit groove; forming an isolation spacer layer on a side wall of the unit groove, where the isolation spacer layer is in contact with the unit dielectric layer; forming a metal layer conformally covering the isolation spacer layer, the first gate laminated structure, and the unit dielectric layer; and annealing the metal layer to form a metal silicide layer. In implementations of the present disclosure, the metal layer is isolated from the first gate laminated structure at a bottom corner of the unit groove using the isolation spacer layer, to prevent a metal silicide layer from being formed at the bottom corner of the unit groove, so that the metal silicide layer is unlikely to have a protruded sharp portion, thereby increasing a breakdown voltage of a unit memory area. Therefore, electrical performance of the semiconductor structure is optimized.