Patent ID: 10903204

Abstract:
A lateral transient voltage suppressor device is provided, comprising a doped substrate, a lateral clamping structure disposed on the doped substrate, a buried doped layer disposed between the doped substrate and the lateral clamping structure for isolation, at least one diode module, and at least one trench arranged in the doped substrate, having a depth not less than that of the buried doped layer, and being disposed between the lateral clamping structure and the at least one diode module for electrical isolation. The doped substrate and the buried doped layer have opposite conductivity types such that the doped substrate is electrically floating. The buried doped layer can be further disposed to separate the diode module from the doped substrate. By employing the proposed invention, the lateral transient voltage suppressor device is advantageous of maintaining both a lower clamping voltage as well as a reduced dynamic resistance.