Patent ID: 10110237

Abstract:
A detection system and a detection method for detecting the loss of lock between a PLL reference clock signal and a PLL feedback clock signal. The detection system includes a pseudorandom bit sequence generator; a first shift register; a second shift register; a third shift register; a first synchronizer; a second synchronizer; a third synchronizer; a first comparator; a second comparator; and an alarm control unit. The method comprises the steps of, generating an n-bit wide pseudorandom bit sequence; sampling the sequence with PLL reference clock signal, PLL feedback clock signal and inverse of PLL feedback clock signal; re-sampling and re-synchronizing the sampled sequences; comparing re-sampled and re-synchronized sequence, previously sampled with PLL reference clock signal, with re-sampled and re-synchronized sequences, previously sampled PLL feedback clock signal and inverse of PLL feedback clock signal; generating a flag signal if the comparisons give no match.