Patent ID: 10622368

Abstract:
Azimuthally-split metal-semiconductor alloy floating gate electrodes can be formed by providing an alternating stack of insulating layers and spacer material layers, forming a dielectric separator structure extending through the alternating stack, and forming memory openings that divides the dielectric separator structure into a plurality of dielectric separator structures. The spacer material layers are formed as, or are replaced with, electrically conductive layers, which are laterally recessed selective to the insulating layers and the plurality of dielectric separator structures to form a pair of lateral cavities at each level of the electrically conductive layers in each memory opening. After formation of a blocking dielectric layer, a pair of physically disjoined metal-semiconductor alloy portions are formed in each pair of lateral cavities as floating gate electrodes. A tunneling dielectric layer and a semiconductor channel layer is subsequently formed in each memory opening.