Patent ID: 10665692

Abstract:
A method for forming a silicon structure. The method includes forming a trench silicide contact between two spacers, each spacer beside respective high-k metal gates. The method planarizes the trench silicide contact, the spacers, and the high-k metal gates. An inner layer dielectric is deposited over the trench silicide contact, the spacers, and the high-k metal gates. A first opening is patterned in the inner layer dielectric for a gate contact over the high-k metal gate, one of the spacers and a portion of the trench silicide contact. The method recesses the portion of the trench silicide contact and deposits a liner within the recessed portion of the trench silicide contact and on sidewalls of the first opening of the inner layer dielectric. A metallization layer is deposited in the opening in the inner layer dielectric to form the gate contact.