Patent ID: 11132283

Abstract:
Present implementations include an electronic device with a system processor (SP) region connectable to an SP, a primary device region connectable to a first electronic device, and a secondary device region disposed between the SP device region and the primary device region, and connectable to a second electronic device. Present implementations further include a debugger region including a debugger unit and disposed adjacent to the primary device region and the secondary device region. Present implementations also include obtaining a debug selection including a debugger selection and a system processor (SP) selection, entering a first debug mode in accordance with a determination that the debugger selection satisfies a debugger criterion and the SP selection satisfies an SP criterion, and entering a second debug mode in accordance with a determination that the debugger selection satisfies the debugger criterion and the SP selection does not satisfy the SP criterion, and entering a third debug mode in accordance with a determination that the debugger selection does not satisfy the debugger criterion.