Patent ID: 10318243

Abstract:
A computer-implemented method of generating an integrated circuit design comprises: using a computer, detecting communication paths between data handling nodes, the data handling nodes comprising data source nodes, data sink nodes and data routing nodes operating according to respective power domains, clock domains and data traffic parameters, in a network of the data handling nodes; using the computer, for a given communication path in a direction of data flow from a data source node to a data sink node, for each given data routing node in the given communication path to which data is communicated in the direction of data flow by a set of one or more other data handling nodes, to perform the following steps: (i) detecting a power domain and data traffic parameters of each data handling node of the set of one or more other data handling nodes communicating data to said each given data routing node; (ii) assigning a power domain to said each given data routing node in dependence upon the detected power domains and the detected data traffic parameters of the set of one or more other data handling nodes; and (iii) assigning a clock domain to said each given data routing node, from a set of one or more candidate clock domains applicable to the assigned power domain, so that said each given data routing node, operating in the assigned clock domain, provides data routing according to the detected data traffic parameters of at least those of the set of one or more other data handling nodes operating according to the assigned power domain of said each given data routing node.