Patent ID: 10763346

Abstract:
Provided is a semiconductor device in which, in a case where a metallic plate (a conductive member) is bonded by being sintered to a semiconductor chip having an IGBT gate structure, an excess stress is less likely to be generated in a gate wiring section of the semiconductor chip even when pressure is applied in a sinter bonding process, so that a characteristic failure is reduced. The semiconductor device according to the present invention is characterized by: being provided with a semiconductor chip having a gate structure represented by an IGBT; including first gate wiring and second gate wiring formed on the surface of the semiconductor chip; and including an emitter electrode disposed so as to cover the first gate wiring and a sintered layer disposed above the emitter electrode, wherein a multilayer structure formed by including at least the emitter electrode and the sintered layer on the surface of the semiconductor chip continuously exists over a range including an emitter electrode connecting contact and gate wiring regions.