Patent ID: 11868642

Abstract:
Disclosed is a system that comprises a memory device and a processing device, operatively coupled with the memory device, to perform operations that include receiving, by the processing device, a trim command on the memory device, wherein the trim command references a range of logical block addresses (LBAs). The operations performed by the processing device further include identifying a group of memory cells corresponding to the range of LBAs, wherein the group of memory cells comprises one or more management units (MUs). The operations performed by the processing device further include updating a data structure associated with the group of memory cells to reference the request; receiving a memory access command with respect to the group of memory cells. The operations performed by the processing device further include responsive to determining that the data structure associated with the group of memory cells references the trim command, blocking the memory access command; performing, on the group of memory cells, a trim operation specified by the trim command; updating the data structure to indicate the completion of the trim operation; and responsive to determining that the data structure indicates the completion of the trim operation, performing a memory access operation specified by the memory access command.