Patent ID: 11094819

Abstract:
A first vertical T-FET has a source heavily doped with a source concentration of a source-type dopant, a drain doped with a drain concentration of a drain-type dopant, and a channel between the source and drain. The source, channel, and drain are stacked vertically in a fin or pillar perpendicular to a substrate. A gate stack encompasses the channel sides and has a drain overlap amount overlapping the drain sides and a source overlap amount overlapping the source sides. External contacts electrically connect the gate and source and/or drain. The source-type dopant and the drain-type dopant are opposite dopant types. In some embodiments, a second vertical T-FET is stacked on the first vertical T-FET. Different VT-FET devices are made by changing the materials, doping types and levels, and connections to the sources, channels, and drains. Device characteristics are designed/changed by changing the amount of source and drain overlaps of the gate stack(s).