Patent ID: 10037800

Abstract:
Apparatus including: memory cell unit(s) having a variable-resistance channel component (CC) extending between first and second supply terminals for supplying read and write (R/W) signals to the unit in respective R/W modes, and resistive memory elements (RMEs) arranged along the CC, RME includes resistive memory material (RMM), extending along a respective channel segment (CHS) of the CC in contact therewith, in which respective lengths along that CHS of high- and low-resistance regions is variable in write mode, and a gate terminal provided on that CHS for controlling resistance of the CHS in response to control signal(s) (CS) applied to the gate terminal; and circuitry configured to apply the CS such that, in read mode, a RME(s) is selected by applying a CS producing CHS with resistance between the resistance regions of the RMM; and remaining RME(s) are deselected by applying CS producing CHS having resistance less than the low-resistance region.