OR gate
A full adder can also be constructed from two half adders by connecting "A" and "B" to the input of one half adder, then taking its sum-output "S" as one of the inputs to the second half adder and "C"in as its other input, and finally the carry outputs from the two half-adders are connected to an OR gate. The sum-output from the second half adder is the final sum output ("S") of the full adder and the output from the OR gate is the final carry output ("C"out). The critical path of a full adder runs through both XOR gates and ends at the sum bit "s". Assumed that an XOR gate takes 1 delays to complete, the delay imposed by the critical path of a full adder is equal to