julilili42/papers huggingface dataset:
A hardware platform for VLIW based emulation of digital designs
2002-11-07

The concept of a very long instruction word (VLIW) processor based system to emulate synthesized RT-level descriptions has often been presented. The RAVE System (RT-Architecture-VLIW-Emulator) overcomes many of the problems common to FPGA based emulation and prototyping systems. Particularly, these are area problems in conjunction with large data paths, long turnaround times and low emulation clock frequencies. This abstract briefly describes the hardware of the RAVE System.
On the complexity of some problems on groups input as multiplication tables
2002-11-07

The Cayley group membership problem (CGM) is to input a groupoid (binary algebra) G given as a multiplication table, a subset X of G, and an element t of G, and to determine whether t can be expressed as a product of elements of X. For general groupoids CGM is P-complete, and for associative algebras (semigroups) it is NL-complete. Here we investigate CGM for particular classes of groups. The problem for general groups is in SL (symmetric log space), but any kind of hardness result seems difficult because it would require constructing the entire multiplication table of a group. We introduce the complexity class FOLL, or FO(log log n), of problems solvable by uniform polysize circuit families of unbounded fan-in and depth O(log log n). Since parity is not in FOLL, no problem in FOLL can be complete for any class containing parity, such as NC/sup 1/, L, or SL. But FOLL is not known to be contained even in SL. We show that CGM for cyclic groups is in FOLL/spl cap/L and that CGM for abelian groups is in FOLL. We then partially extend our method to solvable groups, showing that CGM for groups of constant solvability class is in FOLL and that CGM for nilpotent groups can be solved by poly-size circuits of depth O((log log n)/sup 2/). (Thus the latter problem is provably not complete for any class containing parity) We also consider the problem of testing for various properties of a group input as a table: we prove that cyclicity and nilpotency can each be tested in FOLL/spl cap/L. Finally, we examine the implications of our results for the complexity of iterated multiplication, powering, and division of integers, in the context of the recent results of Chiu, Davida, and Litow.
A ray queueing and sorting design for real time ray casting
2002-11-07

This paper presents a hardware design that processes several rays simultaneously to improve the memory access and compositing performance for three dimensional image synthesis using ray casting. By processing multiple rays, the memory access coherence of a group of neighbouring rays can be exploited and fewer page misses in a modern SDRAM memory device are encountered. Tracing multiple rays also avoids the data hazard that occurs when tracing the path of a single ray. Implementation of the presented design in a real time volume rendering system improves the performance of the system by increasing the number of frames rendered per second.
Embedded system architecture design based on real-time emulation
2002-11-07

This paper presents a new approach to the design of embedded systems. Due to restrictions that state-of-the-art methodologies contain for hardware/software partitioning, we have developed an emulation based method using the facilities of reconfigurable hardware components, such as field programmable gate arrays (FPGA). Our own emulation environment called the SPYDER tool set was used; it is best suited for the emulation of hardware designs for embedded systems.
Target architecture oriented high-level synthesis for multi-FPGA based emulation
2002-11-07

This paper presents a new approach on combined high-level synthesis and partitioning for FPGA-based multi-chip emulation systems. The goal is to synthesize a prototype with maximal performance under the given area and interconnection constraints of the target architecture. Interconnection resources are handled similarly to functional resources, enabling the scheduling and the sharing of inter-chip connections according to their delay. Moreover, data transfer serialization is performed completely or partially, depending on the mobility of the data transfers, in order to satisfy the given interconnection constraints. In contrast to conventional partitioning approaches, the constraints of the target architecture are fulfilled by construction.
Simulation meets verification-checking temporal properties in SystemC
2002-11-07

Due to the increasing complexity of VLSI circuit designs, errors are likely to happen at all stages in the design cycle. Already today, more then 70% of the development time is spend on circuit debugging. This number is even expected to grow in future and imposes yet unsolved challenges on tomorrow's EDA industry. Therefore, the verification of systems (hardware or embedded hardware/software systems) is one of the most important tasks in the design process. To cope with the increasing complexity, various attempts have been made to increase productivity. Among those, one is to provide better suited system description languages (SDLs) supporting the designer at all levels of abstraction. Another important issue is the development of tailored validation and verification techniques. In the past, most verification techniques have been based on simulation and test methods. Recently, formal methods such as temporal property checking has become increasingly popular. However, their industrial applicability is currently restricted to small or medium sized design or to a specific phase in the design cycle. The author describe a simulation based method for verifying temporal properties of systems described in SystemC/sup TM/. The method allows the user to specify properties about the system in a finite version of linear time temporal logic (FLTL). These properties are then checked on-the-fly during each simulation run, and each violation is immediately signaled to the designer.
Analyzing real-time systems
2002-11-07

Temporal logic model checking is a technique for the automatic verification of systems against specifications. Besides the correctness of safety and liveness properties it is often important to determine critical answer and delay times of systems, especially if they are embedded in a real-time environment. In this paper we present an approach which allows the verification as well as the timing analysis of real-time systems. The systems are described as networks of communicating time-extended finite state machines (I/O-interval structures). We use a compact symbolic representation to obtain efficient analysis algorithms.
Exploiting hierarchy for multiple error correction in combinational circuits
2002-11-07

Summary form only given. Multiple error rectification is a challenging task since the search space grows exponentially with the number of design errors. This method is a symbolic method for multiple error rectification of combinational circuits and further development that can correct single errors, only. The main characteristics of our approach are summarized.
Can automatic design error correction be applied to large circuits?
2002-11-07

Boolean equivalence checking has turned out to be a powerful method for verifying combinational circuits and is already an integrated part of the design cycle. If equivalence checking fails, Design Error Diagnosis and Correction (DEDC) is performed which can locate and correct design errors fully automatically in many cases. However DEDC algorithms always have to consider the circuit as a whole and cannot be applied locally to a small sub portion of the design. Thus, the size of rectifiable circuits is often limited which is a hard restriction for applying DEDC in industrial environments. We address the problem of how to make DEDC applicable to larger circuits. We show how a small sub circuit can be safely extracted from a bigger circuit under consideration of its environment. Our extraction method surrounds the extracted component with automatically derived logic such that the rectification of the newly constructed, much smaller circuit yields the same results as rectifying the original, much bigger circuit. In addition, we compare the extraction method with the circuit abstraction method presented by D.W. Hoffmann and T. Kropf (1999).
Java based object oriented hardware specification and synthesis
2002-11-07

Abstract — In this contribution we show how the object oriented programming language Java can be used for the specification of synthesizable hardware. In this context the JavaBeans component model plays an important role. We show an integration of the JavaBeans model which allows the specification of hardware from different views and on different levels of abstraction. Furthermore we point out restrictions of the language necessary to perform high level synthesis. I.
Embedded Java
2002-11-07

Summary form only given. The increasing complexity of embedded systems also results in a rapid growth of the software part, which tends to be developed in object oriented programming languages like C++ or Java. Originally planned for embedded systems, Java plays a more important role in the context of embedded systems from different points of views. Especially platform independence, multithreading parallelism, and Internet embedding are important advantages and contribute to the increasing importance of Java. Different aspects of Java are discussed, as well as their roles, contributions and impacts, especially for embedded system design.
The Nitrate Reductase and Nitrite Reductase Operons and the narT Gene of Staphylococcus carnosus Are Positively Controlled by the Novel Two-Component System NreBC
2002-11-08

ABSTRACT In Staphylococcus carnosus , the nreABC (for nitrogen regulation) genes were identified and shown to link the nitrate reductase operon ( narGHJI ) and the putative nitrate transporter gene narT . An nreABC deletion mutant, m1, was dramatically affected in nitrate and nitrite reduction and growth. Transcription of narT , narGHJI , and the nitrite reductase ( nir ) operon was severely reduced even when cells were cultivated anaerobically without nitrate or nitrite. nreABC transcripts were detected when cells were grown aerobically or anaerobically with or without nitrate or nitrite. NreA is a GAF domain-containing protein of unknown function. In vivo and in vitro studies showed that NreC is phosphorylated by NreB and that phospho-NreC specifically binds to a GC-rich palindromic sequence to enhance transcription initiation. This binding motif was found at the narGHJI , nir , and narT promoters but not at the moeB promoter. NreB is a cytosolic protein with four N-terminal cysteine residues. The second cysteine residue was shown to be important for NreB function. In vitro autophosphorylation of NreB was not affected by nitrate, nitrite, or molybdate. The nir promoter activity was iron dependent. The data provide evidence for a global regulatory system important for aerobic and anaerobic metabolism, with NreB and NreC forming a classical two-component system and NreB acting as a sensor protein with oxygen as the effector molecule.
Efficient design error correction of digital circuits
2002-11-08

Equivalence checking of two circuits is performed at several stages in the design cycle of hardware designs and various commercial equivalence checkers, mostly based on Boolean logic, are already in the market. Design Error Diagnosis and Correction (DEDC) methods come into play when equivalence checking has proven two circuits to be different. In many cases, DEDC methods can locate and correct design errors fully automatically. In this paper, we present an efficient symbolic method for automatic error correction of both combinational and synchronous sequential circuits. We first address the problem of rectifying combinational circuits and then show how the problem of rectifying sequential circuits can be reduced to a combinational problem without unrolling the combinational logic parts. In addition, we introduce several optimizations to our algorithm. All optimizations are safe, meaning that they neither affect the number of computed solutions nor do they neither affect the number of computed solutions nor do they decrease the quality of results. Our experimental results show that the discussed optimization strategies can make the rectification procedure 2 to 16 times faster than the unoptimized algorithm.
Extracting regions of interest applying a local watershed transformation
2002-11-08

We present a new technique for extracting regions of interest (ROI) applying a local watershed transformation. The proposed strategy for computing catchment basins in a given region of interest is based on a rain-falling simulation. Unlike the standard watershed algorithms, which flood the complete (gradient magnitude of an) image, the proposed approach allows us to perform this task locally. Thus, a controlled region growth is performed, saving time and reducing the memory requirement especially when applied on volume data. A second problem arising from the standard watershed transformation is the over-segmented result and the lack of sound criteria for merging the computed basins. For overcoming this drawback, we present a basin-merging strategy introducing four criteria for merging adjacent basins. The threshold values applied in this strategy are derived from the user input and match rather the attributes of the selected object than of all objects in the image. In doing so, the user is not required to adjust abstract numbers, but to simply select a coarse region of interest. Moreover, the proposed algorithm is not limited to the 2D case. As we show in this work, it is suitable for volume data processing as well. Finally, we present the results of applying the proposed approach on several example images and volume data sets.
A methodology and tool for automated transformational high-level design space exploration
2002-11-08

Objective of the methodology presented in this paper is to perform design space exploration on a high level of abstraction by applying high-level transformations. The paper concentrates on algorithmic approaches on controlling the iterative process of transformation selection. A novel modular algorithm for transformation control is presented and its effectiveness is experimentally validated. In combination with a large set of transformation algorithms and mechanisms for high-level estimation of transformation quality, there results a methodology for automated high-level design space exploration. All the concepts are summarized in a software tool called ExTra (Design Space Exploration Using Transformations). Finally, the results of the application of ExTra to the JPEG encoding algorithm are presented.
Four-dimensional non-linear ray tracing as a visualization tool for gravitational physics
2002-11-08

General relativistic ray tracing is presented as a tool for gravitational physics. It is shown how standard three-dimensional ray tracing can be extended to allow for general relativistic visualization. This visualization technique provides images as seen by an observer under the influence of a gravitational field and allows to probe space-time by null geodesics. Moreover, a technique is proposed for visualizing the caustic surfaces generated by a gravitational lens. The suitability of general relativistic ray tracing is demonstrated by means of two examples, namely the visualization of the rigidly rotating disk of dust and the warp drive metric.
The Java CAN API-a Java gateway to field bus communication
2002-11-08

Object oriented problem analysis and software design is becoming more common in the field of industrial control. We present the Java CAN API which provides a convenient, object oriented programming framework for rapid CAN field bus tool development. It provides a hierarchy of classes and interfaces to access arbitrary CAN/CANopen devices via the Java Native Interface. In order to access Windows-based CAN drivers a native dynamic link library has been developed featuring high performance message filtering and asynchronous message notification. The created Java class hierarchy encapsulates the CANopen layer 7 communication objects as well as generic CAN layer 2 messages. Further classes provide access to the CANopen network management services. The paper also briefly presents some practical uses of the Java CAN APl for teleservice, distance education and CAN system management.
Scalability and interoperability in service-centric architectures for the Web
2002-11-08

The Internet provides a computing infrastructure that is highly distributed by nature. In the future the number of actively and cooperatively interacting parties on the Internet, such as traditional computers, embedded devices or various service providers in the field of electronic commerce, will increase further. In such an environment, traditional client/server architectures reach the limit of their capability. Decentralized, distributed software architectures which actively support the object and code migration paradigm, are more suitable. We present a sophisticated approach to a scalable and interoperable service architecture for the Web. We propose a loosely coupled network of service nodes which supports scalability, integration and management of heterogenous services in an uniform way. Our proposed service infrastructure provides a platform to easily locate, connect, integrate and use services of any type. It addresses issues of bandwidth, security, distribution and integration, which are particularly important within the Web, at a general framework level.
Methods based on Petri net for resource sharing estimation
2002-11-08

This work presents two approaches for computing the number of functional units in hardware/software codesign context. The proposed hardware/software codesign framework uses Petri net as common formalism for performing quantitative and qualitative analysis. The use of Petri net as an intermediate format allows to analyze properties of the specification and formally compute performance indices which are used in the partitioning process. This paper is devoted to describe the algorithms for functional unit estimation. This work also proposes a method of extending the Petri net model in order to take into account causal constraints provided by the designers. However, an overview of the general hardware/software codesign method is also presented.
The randomized sample tree
2002-11-11

We present a new data structure for rendering highly complex virtual environments of arbitrary topology. The special feature of our approach is that it allows an interactive navigation in very large scenes (30 GB/400 million polygons in our benchmark scenes) that cannot be stored in main memory, but only on a local or remote hard disk. Furthermore, it allows interactive rendering of substantially more complex scenes by instantiating objects.For the computation of an approximate image of the scene, a sampling technique is used. In the preprocessing, a so-called sample tree is built whose nodes contain randomly selected polygons from the scene. This tree only uses space that is linear in the number of polygons. In order to produce an image of the scene, the tree is traversed and polygons stored in the visited nodes are rendered. During the interactive walkthrough, parts of the sample tree are loaded from local or remote hard disk.We implemented our algorithm in a prototypical walkthrough system. Analysis and experiments show that the quality of our images is comparable to images computed by the conventional z-buffer algorithm regardless of the scene topology.
The CANopen Markup Language representing fieldbus data with XML
2002-11-11

This paper presents the CANopen Markup Language (CoML). CoML is an XML application developed to represent controller area network (CAN) fieldbus system and process data in a generic and platform independent manner. Due to the intrinsic interchangeability of XML structured data, fieldbus data becomes accessible not only by dedicated CoML tools but also by a wide variety of common general purpose XML tools like XML editors or XML databases. Since XML documents are especially well suited to be deployed on the WWW, this approach also facilitates the convenient use of CoML information in a distributed client/server architecture. CoML documents are used to describe CAN device interfaces and CAN system information, to hold CAN process data, and to configure monitoring attributes and (remote) access privileges at the finest granularity. This paper also outlines some practical uses of CoML for fieldbus monitoring and remote fieldbus management.
Remote fieldbus system management with Java and XML
2002-11-11

This paper introduces CANINSIGHT which was developed to create a device and platform independent fieldbus management system for highly distributed enterprises. System data are represented as XML documents which are instances of the CANopen Markup Language (CoML). CoML is an XML application for Controller Area Network (CAN) device profiles, setup information, and process data. The system uses a CoML-based Java client/server architecture to access arbitrary CANopen fieldbus devices via the Internet. The CANINSIGHT client, realized as a Java applet, provides convenient, interactive access to CANopen automation systems at remote locations. The CoML documents which are used for the client/server communication can also be exported to remote database systems and form a central process information repository for an entire manufacturing enterprise. It is possible to use standard database clients to request specific CoML information which can be processed either by dedicated CoML tools or a wide variety of general purpose XML tools.
Fuzzy inference systems for segmented attenuation correction in positron emission tomography
2002-11-11

Segmented attenuation maps can be either calculated from transmission data or with a limited accuracy from emission data. The authors developed two new methods based on adaptive fuzzy inference systems for the transmission segmentation (TSF, Transmission Segmentation by Fuzzy Inference) and for the segmentation of FDG emission images (ESF, Emission Segmentation by Fuzzy Inference). TSF: The main problem, which is the adaptation of the membership functions to the measured data, was solved by adjusting the system with the histogram fitting approach used in the authors' routine segmentation. The fuzzy system allows for a scan time reduction down to 40 s-50 s per bed position and is limited by a local bias in the center of the attenuation map. This system was additionally combined with local thresholding operators based on a fuzzy edge detection leading to accurate results even at 30 s. ESF: In uncorrected FDG emission images the lungs appear with a positive intensity compared to the background, which is almost zero. Based on this effect, ESF allows for an automatic segmentation of 18-FDG emission scans with an error of 10-15% in image quantification. Both methods were evaluated with the same phantom and simulated data, and compared with the authors' standard (Histogram Fitting Segmentation).
Femtosecond dynamics of active semiconductor waveguides-microscopic analysis and experimental investigations
2002-11-11

Summary form only given. We present theoretical and experimental results of the nonlinear amplification and propagation of short optical pulses (250 fs) in semiconductor lasers. The theoretical description is based on spatially resolved Maxwell-Bloch-Langevin equations taking into account the waveguiding structure, spatial variations leading to diffraction, self-focusing and carrier diffusion as well as microscopic coupling between the carrier system and the propagating optical fields.