A VHDL Primer
VHDL is an IEEE standard as well as an ANSI standard language for describing digital designs--but it is a large and verbose language with many complex constructs that have complex semantic meaning, and is difficult to understand initially. (VDHL is often quoted as an acronym for Very Hard Description Language!) This primer--updated to include the new standard just released by the IEEE (IEEE Std 1076-1993)--uses a subset of the language to introduce VDHL to readers at the beginner's level. It explains the complex constructs of the language using an example-based approach. Covers topics such as basic language elements, behavioral modeling, dataflow modeling, structural modeling, generics and configurations, subprograms and overloading, packages and libraries, advanced features, model simulation, and hardware modeling examples. For both hardware and software designers interested in learning VHDL.--This text refers to an out of print or unavailable edition of this title.