Pentium Pro and Pentium II System Architecture (2nd Edition)
The MindShare Architecture SeriesThe MindShare Architecture book series includes: ISA System Architecture, EISA System Architecture, 80486 System Architecture, PCI System Architecture, Pentium System Architecture, PCMCIA System Architecture, PowerPC System Architecture, Plug-and-Play System Architecture, CardBus System Architecture, Protected Mode Software Architecture, USB System Architecture, Pentium Pro and Pentium II System Architecture, and FireWire System Architecture: IEEE 1394. The book series is published by Addison-Wesley.Rather than duplicating common information in each book, the series uses the building-block approach. ISA System Architecture is the core book upon which most of the others build. The figure below illustrates the relationship of the books to each other.Cautionary NoteThe reader should keep in mind that MindShare's book series often deals with rapidly-evolving technologies. This being the case, it should be recognized that each book is a "snapshot" of the state of the targeted technology at the time that the book was completed. We attempt to update each book on a timely basis to reflect changes in the targeted technology, but, due to various factors (waiting for the next version of the spec to be "frozen," the time necessary to make the changes, and the time to produce the books and get them out to the distribution channels), there will always be a delay.What This Book CoversThe purpose of this book is to provide a detailed description of the Pentium Pro and Pentium II processors both from the hardware and the software perspectives. As with our other x86 processor books, this book builds upon and does not duplicate information provided in our books on the previous generation processors. As an example, our Pentium Processor System Architecture book provided a detailed description of the APIC module, while this book only describes differences between the two implementations.What this Book Does not CoverThis book does not describe the x86 instruction repertoire. There are a host of books on the market that already provide this information. It does, however, describe the new instructions added to the instruction set.Organization of This BookPentium Pro and Pentium II System Architecture extends MindShare's coverage of x86 processor architecture to the Pentium Pro and Pentium II processors. The author considers this book to be a companion to the MindShare books entitled 80486 System Architecture, Pentium Processor System Architecture, and Protected Mode Software Architecture (all published by Addison-Wesley). The book is organized as follows:   Part 1: System Overview Chapter 1: System Overview Part 2: Processor's Hardware Characteristics    Hardware Section 1: The Processor Chapter 2: Processor Overview Chapter 3: Processor Power-On Configuration Chapter 4: Processor Startup Chapter 5: The Fetch, Decode, Execute Engine Chapter 6: Rules of Conduct     Hardware Section 2: Bus Intro and Arbitration Chapter 8: Bus Electrical Characteristics Chapter 9: Bus Basics Chapter 10: Obtaining Bus Ownership    Hardware Section 3: The Transaction Phases Chapter 11: The Request and Error Phases Chapter 12: The Snoop Phase Chapter 13: The Response and Data Phases    Hardware Section 4: Other Bus Topics Chapter 14: Transaction Deferral Chapter 15: IO Transactions Chapter 16: Central Agent Transactions Chapter 17: Other Signals Part 3: Pentium II Processor Chapter 18: Pentium II Processor Part 4: Processor's Software Characteristics Chapter 19: Instruction Set Enhancements Chapter 20: Register Set Enhancements Chapter 21: BIOS Update Feature Chapter 22: Paging Enhancements Chapter 23: Interrupt Enhancements Chapter 24: Machine Check Architecture Chapter 25: Performance Monitoring and Timestamp Chapter 26: MMX: Matrix Math Extensions Part 5: Overview of Intel Pentium Pro Chipsets Chapter 27: 450GX and KX Chipsets Chapter 28: 440FX ChipsetWho this Book is ForThis book is intended for use by hardware and software design and support personnel. Due to the clear, concise explanatory methods used to describe each subject, personnel outside of the design field may also find the text useful.Prerequisite KnowledgeIt is highly recommended that the reader have a good knowledge of x86 processor architecture. Detailed descriptions of the 286 and 386 processors can be found in the MindShare book entitled ISA System Architecture. Detailed descriptions of the 486 and Pentium processors can be found in the MindShare books entitled 80486 System Architecture and Pentium Processor System Architecture, respectively. Detailed descriptions of both real and protected mode operation can be found in the MindShare book entitled Protected Mode Software Architecture. All of these books are published by Addison-Wesley.Documentation ConventionsThis document utilizes the following documentation conventions for numeric values.Hexadecimal NotationAll hex numbers are followed by an "h." Examples:9A4Eh0100hBinary NotationAll binary numbers are followed by a "b." Examples:0001 0101b01bDecimal NotationNumbers without any suffix are decimal. When required for clarity, decimal numbers are followed by a "d." The following examples each represent a decimal number:16255256d128dSignal Name RepresentationEach signal that assumes the logic low state when asserted is followed by a pound sign (#). As an example, the HITM# signal is asserted low when a snoop agent has a hit on a modified line in its caches.Signals that are not followed by a pound sign are asserted when they assume the logic high state.WarningThe majority of the processor's signal pins are active low signals (e.g., all of the pins involved in a transaction). All tables in the Intel Pentium Pro Volume One data book, however, represent an asserted signal (in other words, in the electrically low state) with a one, while deasserted signals (electrically high) are represented by a zero in table entries. In other words, a "logical" one in a table indicates that the respective signal pin is asserted (in the electrically low state).As an example, when a table entry indicates a one for the HITM# signal state, this indicates that it is asserted (electrically low).Identification of Bit Fields (logical groups of bits orsignals)All bit fields are designated in little-endian bit ordering as follows:X:Y,where "X" is the most-significant bit and "Y" is the least-significant bit of the field. As an example, the IOPL field in the EFLAGS register consists of bits 13:12, where bit 13 is the most-significant and bit 12 the least-significant bit of the field.Register Field ReferencesBit fields in registers are frequently referred to using the form Regfield name. As an example, the reference CR4DE refers to the Debug Extensions bit in Control Register 4.ResourcesThe Intel Developers' web site contains many documents available for download that provide excellent reference materials. We have a hot-link to their web site on our web site (see next section).Visit Our Web SiteOur Web site contains a listing of all of our courses and books. In addition, it contains errata for a number of the books, a hot link to our publisher's web site, course outlines, and hot links to other useful web sites.mindshareOur publisher's web page contains a listing of our currently-available books and includes pricing and ordering information. Their MindShare page is accessible at:awl/cseng/mindshare/We Want Your FeedbackMindShare values your comments and suggestions. You can contact us via mail, phone, fax or internet email.Phone:  (972) 231-2216 and, in the U.S., (800) 633-1440Fax:  (972) 783-4715E-mail:  tshanley@interservFor information on MindShare seminars, books, book errata, etc., check our web site.Mailing Address:MindShare, Inc.2202 Buttercup DriveRichardson, Texas 750820201309734P04062001