Timing  Verification of Application-Specific Integrated Circuits (ASICs)
PrefaceThis book describes the theory and applications of timing verification of application-specific integrated circuits (ASICs). Timing verification is a relatively new concept, which is why most books on digital systems do not cover the issue. This book lays out the fundamental principles of effective timing verification, and it makes good use of the examples that reflect the current issues facing logic designers.The following items characterize this book:Timing verification as opposed to functional verification is the primary focus. (Functional simulation has been adequately covered in other books.)Principles and techniques as opposed to specific tools are emphasized. Once designers understand the underlying principles of timing analysis, they can apply them with various timing tools.Design flow for deep-submicron ASICs and FPGA designs are fully covered.Numerous design examples and HDL codes to illustrate the concepts discussed in the book are provided.This book is to be used for self-study by practicing engineers. Design and verification engineers who are working with ASICs and FPGAs will find the book very useful. Upper-level undergraduate and graduate students in electrical engineering can use it as a reference book in design courses in timing analysis and related topics.The material covered in this book requires some understanding of the Electronic Design Automation (EDA) tools and an initial course in logic design.The book is organized into two parts:Part I (chapters 1 and 2) introduces the fundamental concepts involved in timing verification. Including clock definitions, multicycle paths, false paths, and phase-locked loops.Part II (chapters 3 and 4) covers specific timing issues related to ASICs and FPGAs, respectively.Chapter 1 gives an overview of timing verification and static timing analysis. It contrasts timing verification with functional verification. Typical goals of timing verification in digital systems are presented. This chapter ends with an example of interface timing analysis.Chapter 2 introduces the concepts of timing analysis with design examples. It specifically discusses such clocking methods as gated clocks, multifrequency clocks, and multiphase clocks. It introduces the concepts of multicycle paths, false paths, and timing constraints (such as setup, hold, recovery, and pulse width).Chapter 3 discusses the deep submicron ASIC design flow and application of timing analysis in the design process. It includes discussion of prelayout and postlayout timing verification. The chapter also discusses behavioral and structural RTL coding for timing, synthesis and timing constraint, and the ASIC sign-off checklist. We make the concepts concrete with numerous examples.Chapter 4 discusses timing concepts in programmable logic-based designs. It covers design flow, timing parameters, timing analysis, and HDL synthesis and software development systems. We present the most commonly used programmable logic devices (Actel, Altera, and Xilinx) and associated timing issues.Appendices A, B, and C discuss the EDA timing tools of PrimeTime, Pearl, and TimingDesigner respectively.Appendix D covers some concepts of transistor-level timing verification.— Farzad Nekoogar