Function at 0x1000c240
Capabilities:
Resolve function by parsing pe exports

Disassembly:
sub esp, 0x60
push ebx
push ebp
mov ebp, dword [esp + 0x6c]
push esi
push edi
push 0xa0
mov ebx, eax
mov eax, dword [esp + 0x80]
push 0
push eax
call fcn.100457d0
mov ecx, dword [esp + 0x90]
push 0xa0
push 0
push ecx
call fcn.100457d0
fld1
or eax, 0xffffffff
movzx edx, ax
mov eax, edx
shl edx, 0x10
or eax, edx
mov dword [ebx], eax
mov dword [ebx + 4], eax
mov word [ebx + 8], ax
mov eax, ebp
lea ecx, [esp + 0x60]
add esp, 0x18
sub eax, ecx
mov dword [esp + 0x74], 0
mov dword [esp + 0x30], eax
jmp 0x1000c2aa
mov eax, dword [esp + 0x30]
mov edx, dword [esp + 0x74]
lea eax, [eax + edx*4]
mov esi, dword [esp + eax + 0x48]
mov eax, 0x66666667
imul esi
sar edx, 1
mov eax, edx
shr eax, 0x1f
add eax, edx
lea ecx, [eax + eax*4]
mov edx, esi
sub edx, ecx
mov ecx, dword [esp + 0x78]
movsx edi, ax
fld dword [ecx + esi*4]
movsx eax, dx
mov dword [esp + 0x2c], eax
call fcn.10047640
test ax, ax
mov eax, dword [esp + 0x7c]
fld dword [eax + esi*4]
jle 0x1000c301
mov edx, dword [esp + 0x74]
fadd st(1)
mov dword [esp + edx*4 + 0x48], 1
fstp dword [eax + esi*4]
jmp 0x1000c315
fsub st(1)
add edi, 8
fstp dword [eax + esi*4]
mov eax, dword [esp + 0x74]
mov dword [esp + eax*4 + 0x48], 0xffffffff
mov esi, dword [esp + 0x2c]
movzx eax, word [ebx + esi*2]
test ax, ax
jge 0x1000c328
mov word [ebx + esi*2], di
jmp 0x1000c35f
movsx ecx, ax
mov edx, ecx
xor edx, edi
test dl, 8
jne 0x1000c343
cmp ecx, edi
jle 0x1000c35a
mov word [ebx + esi*2 + 0xa], ax
mov word [ebx + esi*2], di
jmp 0x1000c35f
mov edx, edi
and ecx, 7
and edx, 7
cmp cl, dl
jg 0x1000c35a
mov word [ebx + esi*2 + 0xa], ax
mov word [ebx + esi*2], di
jmp 0x1000c35f
mov word [ebx + esi*2 + 0xa], di
mov eax, dword [esp + 0x74]
inc eax
cmp eax, 0xa
mov dword [esp + 0x74], eax
jl 0x1000c2a6
mov ecx, dword [ebp + 0x20]
fstp st(0)
fild dword [esp + 0x48]
lea eax, [ecx*4]
mov edx, eax
mov eax, dword [esp + 0x80]
sub eax, edx
fstp dword [esp + 0x34]
fild dword [esp + 0x4c]
mov edx, ecx
sub edx, dword [ebp + 0x24]
mov dword [esp + 0x30], 4
lea edx, [eax + edx*4 + 8]
fstp dword [esp + 0x38]
fild dword [esp + 0x50]
mov dword [esp + 0x18], edx
mov edx, ecx
sub edx, dword [ebp + 0x1c]
fstp dword [esp + 0x3c]
fild dword [esp + 0x54]
lea edx, [eax + edx*4 + 8]
mov dword [esp + 0x14], edx
mov edx, ecx
sub edx, dword [ebp + 0x18]
fstp dword [esp + 0x40]
fild dword [esp + 0x58]
lea edx, [eax + edx*4 + 8]
mov dword [esp + 0x10], edx
fstp dword [esp + 0x44]
mov edx, ecx
sub edx, dword [ebp + 0x14]
fild dword [esp + 0x5c]
lea edx, [eax + edx*4 + 8]
mov dword [esp + 0x80], edx
fstp dword [esp + 0x1c]
fild dword [esp + 0x60]
mov edx, ecx
sub edx, dword [ebp + 0x10]
lea edx, [eax + edx*4 + 8]
fstp dword [esp + 0x20]
fild dword [esp + 0x64]
mov dword [esp + 0x74], edx
mov edx, ecx
sub edx, dword [ebp + 0xc]
fstp dword [esp + 0x24]
fild dword [esp + 0x68]
lea ebx, [eax + edx*4 + 8]
mov edx, ecx
sub edx, dword [ebp + 8]
fstp dword [esp + 0x28]
fild dword [esp + 0x6c]
lea edi, [eax + edx*4 + 8]
mov edx, ecx
sub edx, dword [ebp + 4]
sub ecx, dword [ebp]
fstp dword [esp + 0x2c]
fld dword [esp + 0x34]
lea esi, [eax + edx*4 + 8]
fld dword [esp + 0x38]
lea edx, [eax + ecx*4 + 8]
mov ecx, dword [esp + 0x84]
fld dword [esp + 0x3c]
fld dword [esp + 0x40]
add ecx, 8
fld dword [esp + 0x44]
fld dword [edx - 8]
mov ebp, dword [esp + 0x74]
fmul st(5)
fld dword [esi - 8]
fmul st(5)
faddp st(1)
fld dword [edi - 8]
fmul st(4)
faddp st(1)
fld dword [ebx - 8]
fmul st(3)
faddp st(1)
fld dword [ebp - 8]
mov ebp, dword [esp + 0x80]
fmul st(2)
faddp st(1)
fld dword [ebp - 8]
mov ebp, dword [esp + 0x10]
fmul dword [esp + 0x1c]
faddp st(1)
fld dword [ebp - 8]
mov ebp, dword [esp + 0x14]
fmul dword [esp + 0x20]
faddp st(1)
fld dword [ebp - 8]
mov ebp, dword [esp + 0x18]
fmul dword [esp + 0x24]
faddp st(1)
fld dword [eax]
fmul dword [esp + 0x28]
faddp st(1)
fld dword [ebp - 8]
mov ebp, dword [esp + 0x74]
fmul dword [esp + 0x2c]
faddp st(1)
fstp dword [ecx - 8]
fld dword [edx - 4]
fmul st(5)
fld dword [esi - 4]
fmul st(5)
faddp st(1)
fld dword [edi - 4]
fmul st(4)
faddp st(1)
fld dword [ebx - 4]
fmul st(3)
faddp st(1)
fld dword [ebp - 4]
mov ebp, dword [esp + 0x80]
fmul st(2)
faddp st(1)
fld dword [ebp - 4]
mov ebp, dword [esp + 0x10]
fmul dword [esp + 0x1c]
faddp st(1)
fld dword [ebp - 4]
mov ebp, dword [esp + 0x14]
fmul dword [esp + 0x20]
faddp st(1)
fld dword [ebp - 4]
mov ebp, dword [esp + 0x18]
fmul dword [esp + 0x24]
faddp st(1)
fld dword [eax + 4]
fmul dword [esp + 0x28]
faddp st(1)
fld dword [ebp - 4]
fmul dword [esp + 0x2c]
faddp st(1)
fstp dword [ecx - 4]
fld st(4)
fmul dword [edx]
fld st(4)
fmul dword [esi]
faddp st(1)
fld st(3)
fmul dword [edi]
faddp st(1)
fld st(2)
fmul dword [ebx]
faddp st(1)
mov ebp, dword [esp + 0x74]
fld st(1)
fmul dword [ebp]
mov ebp, dword [esp + 0x80]
faddp st(1)
fld dword [esp + 0x1c]
fmul dword [ebp]
mov ebp, dword [esp + 0x10]
faddp st(1)
fld dword [esp + 0x20]
fmul dword [ebp]
mov ebp, dword [esp + 0x14]
faddp st(1)
fld dword [ebp]
mov ebp, dword [esp + 0x18]
fmul dword [esp + 0x24]
faddp st(1)
fld dword [eax + 8]
fmul dword [esp + 0x28]
faddp st(1)
fld dword [esp + 0x2c]
fmul dword [ebp]
mov ebp, dword [esp + 0x74]
faddp st(1)
fstp dword [ecx]
fld dword [edx + 4]
fmul st(5)
fld dword [esi + 4]
fmul st(5)
faddp st(1)
fld dword [edi + 4]
fmul st(4)
faddp st(1)
fld dword [ebx + 4]
fmul st(3)
faddp st(1)
fld dword [ebp + 4]
mov ebp, dword [esp + 0x80]
fmul st(2)
faddp st(1)
fld dword [ebp + 4]
mov ebp, dword [esp + 0x10]
fmul dword [esp + 0x1c]
faddp st(1)
fld dword [ebp + 4]
mov ebp, dword [esp + 0x14]
fmul dword [esp + 0x20]
faddp st(1)
fld dword [ebp + 4]
mov ebp, dword [esp + 0x18]
fmul dword [esp + 0x24]
faddp st(1)
fld dword [eax + 0xc]
fmul dword [esp + 0x28]
faddp st(1)
fld dword [ebp + 4]
mov ebp, dword [esp + 0x74]
fmul dword [esp + 0x2c]
faddp st(1)
fstp dword [ecx + 4]
fld dword [edx + 8]
fmul st(5)
fld dword [esi + 8]
fmul st(5)
faddp st(1)
fld dword [edi + 8]
fmul st(4)
faddp st(1)
fld dword [ebx + 8]
fmul st(3)
faddp st(1)
fld dword [ebp + 8]
mov ebp, dword [esp + 0x80]
fmul st(2)
faddp st(1)
fld dword [ebp + 8]
mov ebp, dword [esp + 0x10]
fmul dword [esp + 0x1c]
faddp st(1)
fld dword [ebp + 8]
fmul dword [esp + 0x20]
faddp st(1)
mov ebp, dword [esp + 0x14]
fld dword [ebp + 8]
mov ebp, dword [esp + 0x18]
fmul dword [esp + 0x24]
faddp st(1)
fld dword [eax + 0x10]
fmul dword [esp + 0x28]
faddp st(1)
fld dword [ebp + 8]
mov ebp, dword [esp + 0x74]
fmul dword [esp + 0x2c]
faddp st(1)
fstp dword [ecx + 8]
fld dword [edx + 0xc]
fmul st(5)
fld dword [esi + 0xc]
fmul st(5)
faddp st(1)
fld dword [edi + 0xc]
fmul st(4)
faddp st(1)
fld dword [ebx + 0xc]
fmul st(3)
faddp st(1)
fld dword [ebp + 0xc]
mov ebp, dword [esp + 0x80]
fmul st(2)
faddp st(1)
fld dword [ebp + 0xc]
mov ebp, dword [esp + 0x10]
fmul dword [esp + 0x1c]
faddp st(1)
fld dword [ebp + 0xc]
mov ebp, dword [esp + 0x14]
fmul dword [esp + 0x20]
faddp st(1)
fld dword [ebp + 0xc]
mov ebp, dword [esp + 0x18]
fmul dword [esp + 0x24]
faddp st(1)
fld dword [eax + 0x14]
fmul dword [esp + 0x28]
faddp st(1)
fld dword [ebp + 0xc]
mov ebp, dword [esp + 0x74]
fmul dword [esp + 0x2c]
faddp st(1)
fstp dword [ecx + 0xc]
fld dword [edx + 0x10]
fmul st(5)
fld dword [esi + 0x10]
fmul st(5)
faddp st(1)
fld dword [edi + 0x10]
fmul st(4)
faddp st(1)
fld dword [ebx + 0x10]
fmul st(3)
faddp st(1)
fld dword [ebp + 0x10]
mov ebp, dword [esp + 0x80]
fmul st(2)
faddp st(1)
fld dword [ebp + 0x10]
mov ebp, dword [esp + 0x10]
fmul dword [esp + 0x1c]
faddp st(1)
fld dword [ebp + 0x10]
mov ebp, dword [esp + 0x14]
fmul dword [esp + 0x20]
faddp st(1)
fld dword [ebp + 0x10]
mov ebp, dword [esp + 0x18]
fmul dword [esp + 0x24]
faddp st(1)
fld dword [eax + 0x18]
fmul dword [esp + 0x28]
faddp st(1)
fld dword [ebp + 0x10]
fmul dword [esp + 0x2c]
faddp st(1)
mov ebp, dword [esp + 0x74]
fstp dword [ecx + 0x10]
fld dword [edx + 0x14]
fmul st(5)
fld dword [esi + 0x14]
fmul st(5)
faddp st(1)
fld dword [edi + 0x14]
fmul st(4)
faddp st(1)
fld dword [ebx + 0x14]
fmul st(3)
faddp st(1)
fld dword [ebp + 0x14]
mov ebp, dword [esp + 0x80]
fmul st(2)
faddp st(1)
fld dword [ebp + 0x14]
mov ebp, dword [esp + 0x10]
fmul dword [esp + 0x1c]
faddp st(1)
fld dword [ebp + 0x14]
mov ebp, dword [esp + 0x14]
fmul dword [esp + 0x20]
faddp st(1)
fld dword [ebp + 0x14]
mov ebp, dword [esp + 0x18]
fmul dword [esp + 0x24]
faddp st(1)
fld dword [eax + 0x1c]
fmul dword [esp + 0x28]
faddp st(1)
fld dword [ebp + 0x14]
mov ebp, dword [esp + 0x74]
fmul dword [esp + 0x2c]
faddp st(1)
fstp dword [ecx + 0x14]
fld dword [edx + 0x18]
fmul st(5)
fld dword [esi + 0x18]
fmul st(5)
faddp st(1)
fld dword [edi + 0x18]
fmul st(4)
faddp st(1)
fld dword [ebx + 0x18]
fmul st(3)
faddp st(1)
fld dword [ebp + 0x18]
mov ebp, dword [esp + 0x80]
fmul st(2)
faddp st(1)
fld dword [ebp + 0x18]
mov ebp, dword [esp + 0x10]
fmul dword [esp + 0x1c]
faddp st(1)
fld dword [ebp + 0x18]
mov ebp, dword [esp + 0x14]
fmul dword [esp + 0x20]
faddp st(1)
fld dword [ebp + 0x18]
mov ebp, dword [esp + 0x18]
fmul dword [esp + 0x24]
faddp st(1)
fld dword [eax + 0x20]
fmul dword [esp + 0x28]
faddp st(1)
fld dword [ebp + 0x18]
fmul dword [esp + 0x2c]
faddp st(1)
fstp dword [ecx + 0x18]
fld dword [edx + 0x1c]
fmul st(5)
fld dword [esi + 0x1c]
fmul st(5)
faddp st(1)
fld dword [edi + 0x1c]
fmul st(4)
faddp st(1)
fld dword [ebx + 0x1c]
mov ebp, dword [esp + 0x74]
fmul st(3)
add dword [esp + 0x74], 0x28
add ecx, 0x28
faddp st(1)
add eax, 0x28
fld dword [ebp + 0x1c]
mov ebp, dword [esp + 0x80]
fmul st(2)
add dword [esp + 0x80], 0x28
add edx, 0x28
add esi, 0x28
faddp st(1)
add edi, 0x28
fld dword [ebp + 0x1c]
mov ebp, dword [esp + 0x10]
fmul dword [esp + 0x1c]
add dword [esp + 0x10], 0x28
add ebx, 0x28
faddp st(1)
fld dword [ebp + 0x1c]
mov ebp, dword [esp + 0x14]
fmul dword [esp + 0x20]
add dword [esp + 0x14], 0x28
faddp st(1)
fld dword [ebp + 0x1c]
mov ebp, dword [esp + 0x18]
fmul dword [esp + 0x24]
add dword [esp + 0x18], 0x28
sub dword [esp + 0x30], 1
faddp st(1)
fld dword [eax - 4]
fmul dword [esp + 0x28]
faddp st(1)
fld dword [ebp + 0x1c]
fmul dword [esp + 0x2c]
faddp st(1)
fstp dword [ecx - 0xc]
jne 0x1000c464
fstp st(4)
pop edi
fstp st(2)
pop esi
fstp st(0)
pop ebp
fstp st(0)
pop ebx
fstp st(0)
add esp, 0x60
ret