Function at 0x1000ffe0
Capabilities:
Resolve function by parsing pe exports

Disassembly:
sub esp, 0x10
fld dword [edi]
push esi
fstp dword [esp + 8]
mov esi, eax
fld dword [edi + 4]
lea ecx, [edx + 0xc]
fstp dword [esp + 0xc]
lea eax, [esi + 4]
fld dword [esp + 8]
sub edx, esi
fld st(0)
mov esi, 4
fld qword [0x1007ffd8]
fmul st(1), st(0)
fld dword [esp + 0xc]
fld qword [0x1007ffd0]
fmul st(1), st(0)
fld qword [0x1007ffc8]
jmp 0x10010026
fxch st(2)
fxch st(4)
fld dword [ecx - 0xc]
fmul st(1)
fsubrp st(5)
fxch st(4)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fld st(0)
fmul st(4)
fadd st(6), st(0)
fxch st(6)
fstp dword [esp + 4]
fld dword [edx + eax]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fmul st(1)
fld dword [esp + 0xc]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax - 4]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax]
fld dword [ecx - 4]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 8]
fld dword [esp + 8]
fld st(0)
fmul st(4)
fadd st(3), st(0)
fxch st(3)
fstp dword [esp + 4]
fld dword [ecx]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 0xc]
fld dword [esp + 0xc]
fmul st(1)
fld dword [esp + 0x10]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 4]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 8]
fld dword [ecx + 4]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fld st(0)
fmul st(4)
fadd st(6), st(0)
fxch st(6)
fstp dword [esp + 4]
fld dword [ecx + 8]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fmul st(1)
fld dword [esp + 0xc]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0xc]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x10]
fld dword [ecx + 0xc]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 8]
fld dword [esp + 8]
fld st(0)
fmul st(4)
fadd st(3), st(0)
fxch st(3)
fstp dword [esp + 4]
fld dword [ecx + 0x10]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 0xc]
fld dword [esp + 0xc]
fmul st(1)
fld dword [esp + 0x10]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x14]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x18]
fld dword [ecx + 0x14]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fld st(0)
fmul st(4)
fadd st(6), st(0)
fxch st(6)
fstp dword [esp + 4]
fld dword [ecx + 0x18]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fmul st(1)
fld dword [esp + 0xc]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x1c]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x20]
fld dword [ecx + 0x1c]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 8]
fld dword [esp + 8]
fld st(0)
fmul st(4)
fadd st(3), st(0)
fxch st(3)
fstp dword [esp + 4]
fld dword [ecx + 0x20]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 0xc]
fld dword [esp + 0xc]
fmul st(1)
fld dword [esp + 0x10]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x24]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x28]
fld dword [ecx + 0x24]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fld st(0)
fmul st(4)
fadd st(6), st(0)
fxch st(6)
fstp dword [esp + 4]
fld dword [ecx + 0x28]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fmul st(1)
fld dword [esp + 0xc]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x2c]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x30]
fld dword [ecx + 0x2c]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 8]
fld dword [esp + 8]
fld st(0)
fmul st(4)
fadd st(3), st(0)
fxch st(3)
fstp dword [esp + 4]
fld dword [ecx + 0x30]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 0xc]
fld dword [esp + 0xc]
fmul st(1)
fld dword [esp + 0x10]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x34]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x38]
fld dword [ecx + 0x34]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fld st(0)
fmul st(4)
fadd st(6), st(0)
fxch st(6)
fstp dword [esp + 4]
fld dword [ecx + 0x38]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fmul st(1)
fld dword [esp + 0xc]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x3c]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x40]
fld dword [ecx + 0x3c]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 8]
fld dword [esp + 8]
fld st(0)
fmul st(4)
fadd st(3), st(0)
fxch st(3)
fstp dword [esp + 4]
fld dword [ecx + 0x40]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 0xc]
fld dword [esp + 0xc]
fmul st(1)
fld dword [esp + 0x10]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x44]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x48]
fld dword [ecx + 0x44]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fld st(0)
fmul st(4)
fadd st(6), st(0)
fxch st(6)
fstp dword [esp + 4]
fld dword [ecx + 0x48]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fmul st(1)
fld dword [esp + 0xc]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x4c]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x50]
fld dword [ecx + 0x4c]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 8]
fld dword [esp + 8]
fld st(0)
fmul st(4)
fadd st(3), st(0)
fxch st(3)
fstp dword [esp + 4]
fld dword [ecx + 0x50]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 0xc]
fld dword [esp + 0xc]
fmul st(1)
fld dword [esp + 0x10]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x54]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x58]
fld dword [ecx + 0x54]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fld st(0)
fmul st(4)
fadd st(6), st(0)
fxch st(6)
fstp dword [esp + 4]
fld dword [ecx + 0x58]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fmul st(1)
fld dword [esp + 0xc]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x5c]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x60]
fld dword [ecx + 0x5c]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 8]
fld dword [esp + 8]
fld st(0)
fmul st(4)
fadd st(3), st(0)
fxch st(3)
fstp dword [esp + 4]
fld dword [ecx + 0x60]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 0xc]
fld dword [esp + 0xc]
fmul st(1)
fld dword [esp + 0x10]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x64]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x68]
fld dword [ecx + 0x64]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fld st(0)
fmul st(4)
fadd st(6), st(0)
fxch st(6)
fstp dword [esp + 4]
fld dword [ecx + 0x68]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fmul st(1)
fld dword [esp + 0xc]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x6c]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x70]
fld dword [ecx + 0x6c]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 8]
fld dword [esp + 8]
fld st(0)
fmul st(4)
fadd st(3), st(0)
fxch st(3)
fstp dword [esp + 4]
fld dword [ecx + 0x70]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 0xc]
fld dword [esp + 0xc]
fmul st(1)
fld dword [esp + 0x10]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x74]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x78]
fld dword [ecx + 0x74]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fld st(0)
fmul st(4)
fadd st(6), st(0)
fxch st(6)
fstp dword [esp + 4]
fld dword [ecx + 0x78]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fmul st(1)
fld dword [esp + 0xc]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x7c]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x80]
fld dword [ecx + 0x7c]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 8]
fld dword [esp + 8]
fld st(0)
fmul st(4)
fadd st(3), st(0)
fxch st(3)
fstp dword [esp + 4]
fld dword [ecx + 0x80]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 0xc]
fld dword [esp + 0xc]
fmul st(1)
fld dword [esp + 0x10]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax + 0x84]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax + 0x88]
fld dword [ecx + 0x84]
add ecx, 0xa0
fmul st(5)
add eax, 0xa0
sub esi, 1
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fld st(0)
fmul st(4)
fadd st(6), st(0)
fxch st(6)
fstp dword [esp + 4]
fld dword [ecx - 0x18]
fmul st(5)
fsubrp st(3)
fxch st(2)
fstp dword [esp + 0x10]
fld dword [esp + 0x10]
fmul st(1)
fld dword [esp + 0xc]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax - 0x14]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax - 0x10]
fld dword [ecx - 0x14]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 8]
fld dword [esp + 8]
fld st(0)
fmul st(4)
fadd st(3), st(0)
fxch st(3)
fstp dword [esp + 4]
fld dword [ecx - 0x10]
fmul st(5)
fsubrp st(6)
fxch st(5)
fstp dword [esp + 0xc]
fld dword [esp + 0xc]
fmul st(1)
fld dword [esp + 0x10]
fadd st(1)
fstp dword [esp + 8]
fld dword [esp + 8]
fadd dword [esp + 4]
fstp dword [eax - 0xc]
fld dword [esp + 4]
fsub dword [esp + 8]
fstp dword [eax - 8]
jne 0x10010022
fstp st(4)
pop esi
fstp st(2)
fstp st(1)
fstp st(0)
fstp st(0)
fstp dword [edi]
fld dword [esp + 8]
fstp dword [edi + 4]
add esp, 0x10
ret