Fabrication and Characterization of Self-Aligned WSe2 p-Type Field-Effect Transistor

Field: Materials Science (Physical Sciences)

Semiconducting transition metal dichalcogenides (TMDCs) have been growing interests as channel materials in field effect transistors (FET) for next generation low power digital electronics. [1]. Since a complementary metal oxide-semiconductor (CMOS) inverter constructed from pairs of n-type and p-type FETs is a fundamental building blocks in modern digital electronics [2], implementation of both n-type and p-type FETs with semiconducting TMDCs is of particular importance [3]. Among various semiconducting TMDCs, tungsten diselenide (WSe 2 ) is a promising candidate for constructing a CMOS inverter because of its high mobility, symmetric electron and hole effective mass and ambipolar transport [4]. These prominent features of WSe 2 is suitable for an application to CMOS inverter. One of the significant challenges is to develop a top gate and top contact FET structure with WSe 2 for CMOS device integration on the same wafer. In addition, it is desirable to minimize the access region between channel and S/D contact because this access region served as a series resistance to channel resistance, resulting in the lower drain current in FET. This study reports a self-aligned process to fabricate top gate and top contact WSe 2 p-type FET. In this self-aligned structure, the gate electrode and source/drain contact edges are automatically positioned and hence there are no overlap or access region between the gate and source/drain. The feature of this proposed method is that the gate stacks was utilized as a mask for self-aligned formation of WO x , which is source/drain contact for efficient hole injection [5]. The focus on this study is the impact of self-aligned structure of p-type WSe 2 FET on the electrical characteristics. The effectiveness of proposed process was experimentally demonstrated by the fabrication and characterization of device. Figures 1 shows the self-aligned fabrication process of p-type WSe 2 FET. 20 nm-thick SiO 2 was formed by dry oxidation of p + -Si substrate. The mechanically exfoliated multi-layer WSe 2 was transferred by PDMS stamp. Next, 15 nm-thick Al 2 O 3 was prepared by ALD at 200 o C with H 2 O. Then, Nickel (Ni) metal was deposited by RF sputtering on Al 2 O 3 . Ni metal was patterned for gate electrode with conventional lithography process. After that, A 2 O 3 layer was removed by wet etching. Subsequently, substrate was exposed to oxygen radicals to form WO x used as source/drain contact at surface of WSe 2 . Second layer of Al 2 O 3 was deposited as an encapsulating passivation layer. After the contact hole opening, the electrical contact pad was fabricated. Finally, forming gas (N 2 : H 2 = 97 % : 3 %) annealing was performed at 200 o C for 30 min. The top gate length was 5 μm. The gate width was estimated to be 40 μm by optical microscope. The electrical characteristics were measured with a manual probe station in an atmospheric pressure without inert gas purge at room temperature using a precision semiconductor parameter analyzer (Agilent 4156 C). Figures 2 shows the I d –V g characteristics of fabricated FETs for (a) back gate operation and (b) top gate operation. Representative I d –V g characteristics of p-type FETs were observed irrespective of back gate and top gate operation. The on/off ratio of about 10 6 ~ 10 7 order were obtained for both back gate and top gate operation. Furthermore, the threshold voltage and sub-threshold slope were modulated by varying the substrate bias during gate sweep. This study opens up interesting directions for the research and development of TMDC-based devices. Acknowledgments This study was supported by a JSPS Grant-in-Aid for Scientific Research (C) (Grant No. 20K04616), a research grant for Tokyo Tech Challenging Research Award, the Samco Foundation and a research grant for Suematsu Award. References [1] Q. H. Wang, K. K. Zadeh, A. Kis, J. N. Coleman, and M. S. Strano, Nat. Nanotechnol. 7, 699 (2012). [2] Y. Taur and T. H. Ning, Fundamentals of Modern VLSI Devices (Cambridge University Press, Cambridge, 1998). [3] Z. Ahmed, A. Afzalian, T. Schram, D. Jang, D. Verreck, Q. Smets, P. Schuddinck, B. Chehab, S. Sutar, G. Arutchelvan, A. Soussou, I. Asselberghs, A. Spessot, I. P. Radu, B. Parvais, J. Ryckaert and M. H. Na, in Proceedings of the IEEE International Electron Devices Meeting, San Francisco, CA, USA, pp. 465–468, Dec. (2020). [4] L. Yu, A. Zubair, E. J. G. Santos, X. Zhang, Y. Lin, Y. Zhang, and T. Palacios, Nano Lett. 15, 4928 (2015). [5] T. Kawanago, R. Kajikawa, K. Mizutani, Sung-Lin Tsai, I. Muneta, T. Hoshii, K. Kakushima, K. Tsutsui, and H. Wakabayashi, IEEE Journal of the Electron Devices Society, DOI: 10.1109/JEDS.2022.3224206. Figure 1