A 0.012mm2 36.41kHz Temperature-insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V unregulated Supply

Field: Engineering (Physical Sciences)

lnternet-of-Things (1oT) devices, powered by common 1.5V-to-3.6V batteries, generally require low power and less-than-l% inaccuracy frequency references for wake-up. As the mainstream of on-chip frequency references, RC oscillators have shown excellent temperature coefficients (TC <10ppm$/^{\circ}$C), but they usually come at the expense of time-consuming multi-point trimming [1,3], tens-of-pJ/cycle energy efficiency [3], or large area [4]. A compact RC oscillator [2] has achieved an energy efficiency of sub-pJ/cycle, but its line sensitivity (11.01% N) and TC (96.1ppm$/^{\circ}$C) are relatively high. Besides, the references [2–4] require energy-consuming power management integrated circuits (PMIC) due to their narrow supply voltage range. Note that the previous works [1–6] all require complementary-to-absolute-temperature (CTAT) resistors, and most even require proportional-to-absolute-temperature (PTAT) resistors as well, which limits their implementation on advanced technologies. Differently, conventional ring oscillators (ROs) are energy and area efficient, but their line sensitivity (up to 50% N) and TCs (up to 3000ppm$/^{\circ}$C) are intolerable. To surmount these tradeoffs, this paper presents a 0.012mm 2 RO, achieving a line sensitivity of 0.077% N across a wide supply range of 1.3V-to-3.7V without PMIC by employing the proposed PMOSFETs-only delay cell. Additionally, the proposed TC calibration scheme, only requiring either type of resistors, has demonstrated an unrecalibrated TC of 24.9ppm$/^{\circ}$C from -30°C to 150°C. The 36. 4lkHz prototype merely draws 76. 83nA with a 1. 3V supply owing to the proposed current-reuse technique. The architecture of the proposed RO is shown in Fig. 1 (top left). The RO core is supply-insensitive (S1), but is still susceptible to temperature variation. Therefore, the CTAT current reference is designed to compensate the TC of SI-RO. As for the small voltage swing of SI-RO, the succeeding current-domain comparator is employed to generate the rail-to-rail signal (VOUTP). Moreover, the voltage clamper provides the bias voltage (VCLAMP) to protect core devices from high supply voltage. Fig. 1 (top right) illustrates the corresponding TC compensation scheme. Given that the SI-RO outputs PTAT frequency, the proposed RO has the potential to generate a zero-to-absolute-temperature (ZTAT) frequency if the reference current (IREF) exhibits CTAT characteristic.Fig.1 (bottom left) shows the principle of generating different-TC voltages. The gate-source voltage (IVGSI) of a transistor in subthreshold region decreases approximately linearly with the incremental temperature. Furthermore, the TC of the ratio between different |$\mathrm{V}_{\mathrm{G}}$s|, depending on the aspect ratio (W/L) of transistors, can be positive, negative, or even zero. Consequently, this paper proposes a TC calibration scheme that only requires either type of resistors (Fig. 1, bottom right). Regardless of the TC polarity of the resistor (R 3 ) to be calibrated, ZTAT resistance can be achieved eventually by appropriately trimming the size of transistors to change the TC of the calibration factor (K=|$\mathrm{V}_{\mathrm{G}\mathrm{S}\mathrm{i}}$|/|$\mathrm{V}_{\mathrm{G}\mathrm{S}\mathrm{X}}$|). However, the conventional calibration scheme requires both CTAT resistor (R$\uparrow$) and PTAT resistor (R 2 ) in series at a specific ratio to achieve ZTAT resistance, which cannot be applied to advanced technologies (e.g., $\leq$28nm) lacking of CTAT resistors.