One sided communication on a non cache coherent many core architecture Contemporary multi core processors are parallel systems that also provide shared memory for programs running on them. Both the increasing number of cores in so called many core systems and the still growing computational power of the cores demand for memory systems that are able to deliver high bandwidths. Caches are essential components to satisfy this requirement. Nevertheless hardware based cache coherence in many core chips faces practical limits to provide both coherence and high memory bandwidths. In addition a shift away from global coherence can be observed. As a result alternative architectures and suitable programming models need to be investigated. This thesis focuses on fast communication for non cache coherent many core architectures. Experiments are conducted on the Single Chip Cloud Computer (SCC) a non cache coherent many core processor with 48 mesh connected cores. Although originally designed for message passing the results of this thesis show that shared memory can be efficiently used for one sided…