Copper interconnect technology Copper interconnect technology is expected to be a key component in the quest to create more powerful CPUs and memory chips. This text examines the role of copper in future interconnects presents the range of problems involved and explains how the solutions are being found 1. Introduction: Acknowledgments 2. Interconnect issues: 2.1. Overview; 2.2. Materials requirements; 2.3. Materials options; 2.4. Multilevel interconnect fabrication 3. Copper deposition: 3.1. Overview; 3.2. Chemical deposition methods for copper; 3.3. Physical deposition methods for copper 4. Copper patterning: 4.1. Overview; 4.2. Subtractive copper patterning; 4.3. Additive copper patterning by chemical mechanical polishing (CMP) 5. Interlayer dielectrics: 5.1. Silicate based ILDs; 5.2. Organic polymer based ILDs; 5.3. Patterning of ILDs 6. Cu ILD barriers: 6.1. Cu undoped SiO2 barriers; 6.2. Cu doped SiO2 barriers; 6.3. Cu polymerbarriers 7. Current practice: 7.1. Overview; 7.2. Preclean; 7.3. Barrier layers; 7.4. Copper fill methods; 7.5. Future directions References Index