Parasitic Aware Optimization of CMOS RF Circuits In the arena of Parasitic Aware Design of CMOS RF Circuits efforts are aimed at the realization of true single chip radios with few if any off chip components. Ironically the on chip passive components required for RF integration pose miore serious challenges to SOC integration than the active CMOS and BJT devices. This is not surprising since modern digital IC designs are dominated as much or more by interconnectg characteristics than by active device properties. In any event the co integration of active and passive devices in RFIC design represents a serious design problem and an even more daunting manufacturing challenge. If conventional mixed signal design techniques are employed parasitics associated with passive elements (resistors capacitors inductors transformers pads etc.) and the package effectively de tune RF circuits rendering them sub optimal or virtually useless. Hence dealing with parasitics in an effective way as part of the design process is an essential emerging methodology in modern SOC design. The parasitic aware RF circuit synthesis techinques described in this book effectively address this critical problem. Background On Parasitic Aware Optimization Modeling of On Chip Passive and Active Components Parasitic Aware Optimization Optimization of CMOS RP Circuits Optimization of CMOS Low Noise Amplifiers Optimization of CMOS Mixers Optimization of CMOS Oscillators Optimization of CMOS RF Power Amplifiers Optimization of Ultra Wideband Amplifiers.