Attacking complexity in logic synthesis of asynchronous circuits Most of the microelectronic circuits fabricated today are synchronous i.e. they are driven by one or several clock signals. Synchronous circuit design faces several fundamental challenges such as high speed clock distribution integration of multiple cores operating at different clock rates reduction of power consumption and dealing with voltage temperature manufacturing and runtime variations. Asynchronous or clockless design plays a key role in alleviating these challenges however the design and test of asynchronous circuits is much more difficult in comparison to their synchronous counterparts. A driving force for a widespread use of asynchronous technology is the availability of mature EDA (Electronic Design Automation) tools which provide an entire automated design flow starting from an HDL (Hardware Description Language) specification yielding the final circuit layout. Even though there was much progress in developing such EDA tools for asynchronous circuit design during the last two decades the maturity level as well as the acceptance of them is still not comparable with tools for synchronous circuit design. In particular logic synthesis (which implies the application of Boolean minimisation techniques) for the entire systems control path can significantly improve the efficiency of the resulting asynchronous implementation e.g. in terms of chip area and performance. However logic synthesis in particular for asynchronous circuits suffers from complexity problems. Signal Transitions Graphs (STGs) are labelled Petri nets which are a widely used to specify the interface behaviour of speed independent (SI) circuits a robust subclass of asynchronous circuits. STG decomposition is a promising approach to tackle complexity problems like state space explosion in logic synthesis of SI circuits. The (structural) decomposition of STGs is guided by a partition of the output signals and generates a usually much smaller component STG for each partition member i.e. a component STG with a much smaller state space than the initial specification. However decomposition can result in component STGs that in isolation have so called irreducible CSC conflicts (i.e. these components are not SI synthesisable anymore) even if the specification has none of them. A new approach is presented to avoid such conflicts by introducing internal communication between the components. So far STG decompositions are guided by the finest output partitions i.e. one output per component. However this might not yield optimal circuit implementations. Efficient heuristics are presented to determine coarser partitions leading to improved circuits in terms of chip area. For the new algorithms correctness proofs are given and their implementations are incorporated into the decomposition tool DESIJ. The presented techniques are successfully applied to some benchmarks including real life specifications arising in the context of control resynthesis which delivered promising results.