Design and evaluation of computer arithemetic based on carry save and signed digit redundant number representations The continuing demand for technological advances while dealing with mutual constraining characteristics of digital systems as for instance lower feature size lower power consumption and lower compute latency drives a need for constant innovation. To further improve state of the art digital hardware thorough knowledge of computer arithmetic is needed. This thesis explores selected aspects of the design and evaluation of computer arithmetic based on carry save and signed digit redundant number representations to reduce the area the critical path latency and the power consumption of arithmetic circuits. Carry save arithmetic is frequently used to realize basic arithmetic operations requiring inner product calculations as multiplication multiply add multiply accumulate and digital filters. This thesis enhances multiplication and multiply accumulation based on carry save arithmetic by improving the well known Wallace and Dadda partial product reduction strategies. An alternative concept of time based reduction strategies is introduced as well and applied to multiply accumulate units resulting in reduced area critical path latency and power consumption. A competitive redundant number representation is the signed digit number representation. Not frequently implemented in state of the art hardware designs it is recurring in prototype development. Implemented signed digit arithmetic is based on signed binary adder cells. This thesis demonstrates the need for optimizing these cells and presents concepts of a systematic design space exploration of signed binary adder cells. Additionally the error resilience capabilities of signed digit arithmetic is evaluated and favorable digit encoding schemes are presented.