Power and timing modeling for performance of integrated circuits This book contains contributions to the 1995 PATMOS Workshop on Power and Timing Modeling for Performance of Integrated Circuits held at OFFIS Oldenburg Germany. For five years the PATMOS series of annual workshops is the traditional European forum to discuss modeling optimization and simulation of ICs at the physical and logical level. Outstanding scientific contributions are mixed with informal discussions and stimulating panel sessions. Topics of the 1995 workshop include: self timed design delay modeling adder and algorithms optimization low power logic design power estimation glitch and short circuit power dissipation low power multipliers parasitic coupling and interconnections low power design and reliability and CAD tools for low power. <dt.>