Change:
Describe the bug To Reproduce -env -i ghdl-llvm # or nix run ... -a Expected behavior ghdl compiles and runs the code Additional context uses LLVM as a backend to compile VHDL to a simulator executable for RTL simulation. It finally links its outputs using (via a call to gcc). The problem is, that in this linking step it also wants to link , which the linker can not find. However, in a everything works as intended. Even a and appending to NIX_LDPATH suffices. I tried various (combinations) of and friends and also , but never got this to work. I suspect that there is something in the setup hook of the nix-shell, but inspecting and comparing s didn't get me any further. Maybe someone could look into this or introduce me to the dark magic of and packaging compilers. (Looking at other compiler's .nix files also was a dead end for me.)
I marked this as stale due to inactivity. &rarr;

Discussion:
<del> { stdenv, fetchFromGitHub, gnat, zlib, llvm, lib </del> <ins> { stdenv, fetchFromGitHub, callPackage, gnat, zlib, llvm, lib </ins> , backend ? "mcode" }: assert backend == "mcode" || backend == "llvm";

LIBRARY_PATH = "${stdenv.cc.libc}/lib"; buildInputs = [ gnat zlib ] ++ lib.optional (backend == "llvm") [ llvm ]; <ins> propagatedBuildInputs = lib.optionals (backend == "llvm") [ zlib ]; </ins> preConfigure = '' # If llvm 7.0 works, 7.x releases should work too.

enableParallelBuilding = true; <ins> passthru = { # run with either of # nix-build -A ghdl-mcode.passthru.tests # nix-build -A ghdl-llvm.passthru.tests tests = { simple = callPackage ./test-simple.nix { inherit backend; }; }; }; </ins> meta = with lib; { homepage = "https://github.com/ghdl/ghdl"; description = "VHDL 2008/93/87 simulator";

<ins> simple-tb.vhd:71:5:@700ms:(report note): 32 simple-tb.vhd:71:5:@900ms:(report note): 78 simple-tb.vhd:71:5:@1100ms:(report note): 105 simple-tb.vhd:71:5:@1300ms:(report note): 120 simple-tb.vhd:71:5:@1500ms:(report note): 79 simple-tb.vhd:71:5:@1700ms:(report note): 83 simple-tb.vhd:71:5:@1900ms:(report note): 32 simple-tb.vhd:75:1:@2100ms:(report note): All tests passed. </ins>

<ins> library ieee; use IEEE.STD_LOGIC_1164.all; use ieee.numeric_std.all; library STD; use STD.textio.all; entity tb is end tb; architecture beh of tb is component simple port ( CLK, RESET : in std_ulogic; DATA_OUT : out std_ulogic_vector(7 downto 0); DONE_OUT : out std_ulogic ); end component; signal data : std_ulogic_vector(7 downto 0) := "00100000"; signal clk : std_ulogic; signal RESET : std_ulogic := '0'; signal done : std_ulogic := '0'; signal cyclecount : integer := 0; constant cycle_time_c : time := 200 ms; constant maxcycles : integer := 100; begin simple1 : simple port map ( CLK => clk, RESET => RESET, DATA_OUT => data, DONE_OUT => done ); clk_process : process begin clk <= '0'; wait for cycle_time_c/2; clk <= '1'; wait for cycle_time_c/2; end process; count_process : process(CLK) begin if (CLK'event and CLK ='1') then if (RESET = '1') then cyclecount <= 0; else cyclecount <= cyclecount + 1; end if; end if; end process; test : process begin RESET <= '1'; wait until (clk'event and clk='1'); wait until (clk'event and clk='1'); RESET <= '0'; wait until (clk'event and clk='1'); for cyclecnt in 1 to maxcycles loop exit when done = '1'; wait until (clk'event and clk='1'); report integer'image(to_integer(unsigned(data))); end loop; wait until (clk'event and clk='1'); report "All tests passed." severity NOTE; wait; end process; end beh; </ins>

<ins> library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.NUMERIC_STD.ALL; use IEEE.STD_LOGIC_MISC.or_reduce; entity simple is port ( CLK, RESET : in std_ulogic; DATA_OUT : out std_ulogic_vector(7 downto 0); DONE_OUT : out std_ulogic ); end simple; architecture beh of simple is signal data : std_ulogic_vector(7 downto 0); signal done: std_ulogic; begin proc_ctr : process(CLK) begin if (CLK = '1' and CLK'event) then if (RESET = '1') then data <= "01011111"; done <= '0'; else case data is when "00100000" =>  data <= "01001110"; when "01001110" =>  data <= "01101001"; when "01101001" =>  data <= "01111000"; when "01111000" =>  data <= "01001111"; when "01001111" =>  data <= "01010011"; when others =>  data <= "00100000"; end case; done <= not or_reduce(data xor "01010011"); end if; end if; end process; DATA_OUT <= data; DONE_OUT <= done; end beh; </ins>

<ins> { stdenv, ghdl-llvm, ghdl-mcode, backend }: let ghdl = if backend == "llvm" then ghdl-llvm else ghdl-mcode; in stdenv.mkDerivation { name = "ghdl-test-simple"; meta.timeout = 300; nativeBuildInputs = [ ghdl ]; buildCommand = '' cp ${./simple.vhd} simple.vhd cp ${./simple-tb.vhd} simple-tb.vhd mkdir -p ghdlwork ghdl -a --workdir=ghdlwork --ieee=synopsys simple.vhd simple-tb.vhd ghdl -e --workdir=ghdlwork --ieee=synopsys -o sim-simple tb '' + (if backend == "llvm" then '' ./sim-simple --assert-level=warning > output.txt '' else '' ghdl -r --workdir=ghdlwork --ieee=synopsys tb > output.txt '') + '' diff output.txt ${./expected-output.txt} && touch $out ''; } </ins>