Code change:
<ins> //@ only-x86_64 //@ compile-flags: -C opt-level=3 #![crate_type = "lib"] #![no_std] #![feature(str_internals)] extern crate alloc; /// Ensure that the ascii-prefix loop for `str::to_lowercase` and `str::to_uppercase` uses vector /// instructions. /// /// The llvm ir should be the same for all targets that support some form of simd. Only targets /// without any simd instructions would see scalarized ir. /// Unfortunately, there is no `only-simd` directive to only run this test on only such platforms, /// and using test revisions would still require the core libraries for all platforms. // CHECK-LABEL: @lower_while_ascii // CHECK: [[A:%[0-9]]] = load <16 x i8> // CHECK-NEXT: [[B:%[0-9]]] = icmp slt <16 x i8> [[A]], zeroinitializer // CHECK-NEXT: [[C:%[0-9]]] = bitcast <16 x i1> [[B]] to i16 #[no_mangle] pub fn lower_while_ascii(s: &str) -> (alloc::string::String, &str) { alloc::str::convert_while_ascii(s, u8::to_ascii_lowercase) } </ins>

Related discussion:
text: I'm looking into the performance of / on mostly ascii strings, using a small microbenchmark to . Using linux perf tooling I see that the hot part of the code is the following large loop, which despite heavy use of sse2 instructions only seems to process 32 bytes per iteration. I don't see an easy way to improve the autovectorization of this code, but it should be relatively easy to explicitly vectorize it using , and I would like to prepare such a PR if there are no objections. As far as I know, is already in use inside , for example by .
The way the loop ors the bits for the is-ascii check into a single usize doesn't seem ideal for vectorization. keeping the lanes independent should yield better autovectorization results.
Thanks for the suggestion. I already started with a simd implementation, but now checked again if the autovectorization could be improved. With the following main loop The assembly and performance is indeed better, but there is still some weird shuffling and shifting going on: The explicit simd version looks a bit better, mostly because the ascii check directly translates to a : Do you have a preference here between autovectorization and explicit simd?
If the SIMD impl results in reasonable code across architectures, including some without SIMD then that should be fine. I think it would be the first time where we use portable simd unconditionally, so it could use some additional scrutiny. If it's only meant to target x86 with SSE2 then that'd mean having multiple paths and in that case we'd still have to tweak the generic path anyway. At that point we might as well just optimize the latter further. You can probably get rid of those too by keeping multiple bools in a small array. That way the optimizer will more easily see that it can shove them into independent simd lanes. Increasing the unroll count might help too to fit better into simd registers. We do get pretty decent autovectorization in other places in the standard library by massaging things into a state that basically looks like arrays-instead-of-SIMD-types. E.g.
It seems llvm is too "smart" for this trick, on its own that generates the exact same code. The trick does work, although it seems a bit fragile.