//  [c]
error_t rza1EthInit(NetInterface *interface)
{
   error_t error;

   //Debug message
   TRACE_INFO("Initializing RZ/A1 Ethernet MAC...\r\n");

   //Save underlying network interface
   nicDriverInterface = interface;

   //Enable Ethernet peripheral clock
   CPG.STBCR7 &= ~CPG_STBCR7_MSTP74;

   //GPIO configuration
   rza1EthInitGpio(interface);

   //Perform software reset
   ETHER.ARSTR = ETHER_ARSTR_ARST;
   //Wait for the reset to complete
   sleep(10);

   //Start EDMAC transmitting and receiving units
   ETHER.EDSR0 = ETHER_EDSR0_ENT | ETHER_EDSR0_ENR;

   //To execute a software reset with this register, 1 must be
   //written to both the SWRT and SWRR bits simultaneously
   ETHER.EDMR0 = ETHER_EDMR0_SWRT | ETHER_EDMR0_SWRR;
   //Wait for the reset to complete
   while(ETHER.EDMR0 & (ETHER_EDMR0_SWRT | ETHER_EDMR0_SWRR))
   {
   }

   //Valid Ethernet PHY or switch driver?
   if(interface->phyDriver != NULL)
   {
      //Ethernet PHY initialization
      error = interface->phyDriver->init(interface);
   }
   else if(interface->switchDriver != NULL)
   {
      //Ethernet switch initialization
      error = interface->switchDriver->init(interface);
   }
   else
   {
      //The interface is not properly configured
      error = ERROR_FAILURE;
   }

   //Any error to report?
   if(error)
   {
      return error;
   }

   //Initialize DMA descriptor lists
   rza1EthInitDmaDesc(interface);

   //Select little endian mode and set descriptor length (16 bytes)
   ETHER.EDMR0 = ETHER_EDMR0_DE | ETHER_EDMR0_DL_16;

   //Error masks
   ETHER.TRSCER0 = 0;
   //Use store and forward mode
   ETHER.TFTR0 = 0;

   //Set transmit FIFO size and receive FIFO size (2048 bytes)
   ETHER.FDR0 = ETHER_FDR0_TFD_2048 | ETHER_FDR0_RFD_2048;

   //Enable continuous reception of multiple frames
   ETHER.RMCR0 = ETHER_RMCR0_RNC;
   //No padding insertion into receive data
   ETHER.RPADIR0 = 0;

   //Receive FIFO threshold (8 frames or 2048-64 bytes)
   ETHER.FCFTR0 = ETHER_FCFTR0_RFF_8 | ETHER_FCFTR0_RFD_2048;

   //Intelligent checksum operation mode
   ETHER.CSMR = 0;

   //Enable multicast address filtering
   ETHER.ECMR0 |= ETH_ECMR0_MCT;

   //Set the upper 32 bits of the MAC address
   ETHER.MAHR0 = (interface->macAddr.b[0] << 24) | (interface->macAddr.b[1] << 16) |
      (interface->macAddr.b[2] << 8) | interface->macAddr.b[3];

   //Set the lower 16 bits of the MAC address
   ETHER.MALR0 = (interface->macAddr.b[4] << 8) | interface->macAddr.b[5];

   //Disable all CAM entries
   ETHER.TSU_TEN = 0;

   //Maximum frame length that can be accepted
   ETHER.RFLR0 = RZA1_ETH_RX_BUFFER_SIZE;
   //Automatic pause frame
   ETHER.APR0 = 0;
   //Manual pause frame
   ETHER.MPR0 = 0;
   //Automatic pause frame retransmit count
   ETHER.TPAUSER0 = 0;

   //Disable all EMAC interrupts
   ETHER.ECSIPR0 = 0;

   //Enable the desired EDMAC interrupts
   ETHER.EESIPR0 =  ETHER_EESIPR0_TWBIP | ETHER_EESIPR0_FRIP;

   //Register interrupt handler
   R_INTC_Regist_Int_Func(INTC_ID_ETHERI, rza1EthIrqHandler);
   //Configure interrupt priority
   R_INTC_Set_Priority(INTC_ID_ETHERI, RZA1_ETH_IRQ_PRIORITY);

   //Enable EDMAC transmission and reception
   ETHER.ECMR0 |= ETH_ECMR0_RE | ETH_ECMR0_TE;

   //Instruct the DMA to poll the receive descriptor list
   ETHER.EDRRR0 = ETHER_EDRRR0_RR;

   //Accept any packets from the upper layer
   osSetEvent(&interface->nicTxEvent);

   //Successful initialization
   return NO_ERROR;
}