In 1989, HP thought Reduced Instruction Set Computing (RISC) architectures were stuck at one instruction per cycle. HP researchers tried to create a new type of processor architecture, later called Explicitly Parallel Instruction Computing (EPIC), that allows the processor to use many instructions in each clock cycle. EPIC uses a form of very long instruction word (VLIW) architecture, in which 1 instruction word had many instructions. With EPIC, the compiler checks which instructions can be used at the same time, so the processor can run the instructions without needing complicated methods to see which instructions to use at the same time.
The goal of this idea is to allow better inspection of the code at the time of compile to check for additional opportunities for multiple executions at once, and to simplify processor design and save electricity by removing the need for runtime scheduling instructions.
HP thought that it was not good for individual enterprise system companies like HP to make proprietary processors, so HP worked with Intel in 1994 to create the IA-64 architecture, made with EPIC's ideas. Intel wanted to make a large effort in creating IA-64 in the expectation that the resulting processor would be used by most enterprise systems. HP and Intel had a large design effort to make the first Itanium product, Merced, in 1998.
During creation, Intel, HP, and other industry analysts thought that IA-64 would be very popular in servers, workstations, and desktops, and one day replace RISC and Complex Instruction Set Computing (CISC) architectures for multi-purpose applications.
Compaq and Silicon Graphics stopped working on their Alpha and MIPS architectures to move to the Itanium architecture.
Many groups created operating systems for Itanium, including Microsoft Windows, OpenVMS, Linux, and UNIX types such as HP-UX, Solaris,
Tru64 UNIX, and Monterey/64
(the last three were never finished work with running on Itanium). By 1997, many found that the Itanium architecture and the compiler were more difficult to use than they thought.
Technology issues such as the very high transistor counts needed for the large instruction words and the large caches. There were also problems with the project, as the two parts of the team used different methods and had slightly different priorities. Because Merced was the first EPIC processor, its creation had more problems than the team had thought. In addition, the EPIC concept requires different compiler abilities that had never been created before, so more research was needed.
Intel announced the name of the processor, "Itanium", on October 4, 1999.
In only a few hours, the name "Itanic" had been used as a joke, (a reference to "Titanic", the "unsinkable" ship that sank in 1912 ("Itanium + Titanic = Itanic")).
"Itanic" has also been used by "The Register",
and others,
to say the multi-billion-dollar investment in Itanium, and the early demand with it, would mean nothing because they thought Itanium was going to fail.
By the time Itanium was released in June 2001, its performance was not superior to competing RISC and CISC processors.
Itanium competed with low-power systems (primarily 4-CPU and small systems) with servers based on x86 processors, and with high-power such as with IBM's POWER architecture and Sun Microsystems' SPARC architecture. Intel shifted Itanium to working with the high-power business and HPC computing, trying to copy x86's successful market (i.e., 1 architecture, many system vendors). The success of the 1st processor version was only with replacing PA-RISC in HP systems, Alpha in Compaq systems and MIPS in SGI systems, but IBM also made a supercomputer based on this architecture.
POWER and SPARC were strong, and the x86 architecture grew more into the enterprise space, because of easier scaling and very large install base.
Only a few thousand systems using the 1st Itanium processor, "Merced", were sold, because of poorer performance, high cost and less Itanium-made software.
Intel saw that Itanium required more native software to work well, so Intel made thousands of systems for independent software vendors to help them make Itanium software. HP and Intel brought the 2nd Itanium processor, Itanium 2, to market a year later.
The Itanium 2 processor was released in 2002, for enterprise servers and not all of high-power computing. The 1st version of Itanium 2, code-named "McKinley", was created by HP and Intel. It fixed many of the problems of the 1st Itanium processor, which were mostly caused by a bad memory subsystem. "McKinley" had 221 million transistors (25 million of them were for logic), and was 19.5 mm by 21.6 mm (421 mm) and was created with a 180 nm design process, and a CMOS process with 6 layers of aluminium.
In 2003, AMD released the Opteron, which implemented the first x86-64 architecture (called AMD64 at the time). Opteron was much more successful because it was an easy upgrade from x86. Intel implemented x86-64 in its Xeon processors in 2004.
Intel released a new Itanium 2 processor, code-named "Madison", in 2003. Madison used a 130 nm process and was the foundation of all new Itanium processors until June 2006.
In March 2005, Intel announced that it was working on a new Itanium processor, code-named "Tukwila", to be released in 2007. Tukwila would have 4 processor cores and would replace the Itanium bus with a new Common System Interface, which would also be used by a new Xeon processor.
Later in that year, Intel changed Tukwila's release date to late 2008.
In November 2005, the largest Itanium server makers worked with Intel and many software vendors to create the Itanium Solutions Alliance, to promote the architecture and speed up software porting.
The Alliance says that its members would invest $10 billion in Itanium solutions by the end of the decade.
In 2006, Intel delivered "Montecito" (marketed as the Itanium 2 9000 series), a 2-core processor that had approximately 2x performance and 20% less energy usage.
Intel released the Itanium 2 9100 series, codenamed "Montvale", in November 2007.
In May 2009, the release for Tukwila, Montvale's successor, was changed again, with release to OEMs planned for the first quarter of 2010.
The Itanium 9300 series processor, code-named "Tukwila", was released on February 8, 2010, with greater performance and memory amount.
Tukwila uses a 65 nm process, has between two and four cores, up to 24 MB CPU cache, Hyper-Threading technology and new memory controllers. It also has double-device data correction, which helps to fix memory issues. Tukwila also has Intel QuickPath Interconnect (QPI) to replace the Itanium bus architecture. It has a maximum inner-processor bandwidth of 96 GB/s and a maximum memory bandwidth of 34 GB/s. With QuickPath, the processor has built-in memory controllers, which controls the memory using QPI interfaces to communicate with other processors and I/O hubs. QuickPath is also used with Intel processors using the "Nehalem" architecture, so that Tukwila and Nehalem might be able to use the same chipsets.
Tukwila incorporates four memory controllers, each of which supports multiple DDR3 DIMMs via a separate memory controller,
similar to the Nehalem Xeon processor code-named "Beckton".
The Itanium 9500 series processor, code-named "Poulson", is the follow-on processor to Tukwila and was released on November 8, 2012.
Intel says it skips the 45 nm process technology and uses the 32 nm process technology instead; it features 8 cores, has a 12-wide issue architecture, multi-threading additions, and new instructions for parallelism, including virtualization.
The Poulson L3 cache size is 32 MB. L2 cache size is 6 MB, 512 I KB, 256 D KB per core. Poulson's size is 544 mm², less than Tukwila's size (698.75 mm²).
At ISSCC 2011, Intel presented a paper called, "A 32nm 3.1 Billion Transistor 12-Wide-Issue Itanium Processor for Mission Critical Servers."