Authors: Jiajian Luo | Jungyun Lim | Jingjing Chen | Archana Venugopal | Zongqing Ren | Jaeho Lee
Source: IEEE Transactions on Electron Devices (article, 2024-02-26)
Field: Materials Science — Materials Chemistry

Dynamic Thermal Management in SOI Transistors Using Holey Silicon-Based Thermoelectric Cooling Silicon-on-insulator (SOI) technology offers many advantages for transistors while also presenting significant challenges in thermal management. The buried oxide (BOX) layer impedes vertical heat dissipation, rendering conventional cooling solutions based on air and liquid coolers inefficient. In this study, we propose a novel theoretical design of a holey silicon-based lateral thermoelectric cooler (TEC) that provides a unique cooling solution for SOI transistors. By redistributing heat laterally, this TEC overcomes the limitation of poor vertical heat dissipation caused by the BOX layer, meanwhile taking advantage of the sustained temperature gradient in the device layer. In addition, we present a novel precooling strategy which utilizes a long-time, optimal-voltage TEC cooling pulse to cool down a short-time, high-power-density heating pulse. We evaluate the cooling performance through simulation of two devices: an SOI transistor-TEC device and a 5 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times$</tex-math> </inline-formula> 5 SOI transistor-TEC array device. Under a 10 1.s transient heat pulse with high-power density of 11 000 W/cm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^\text{2}$</tex-math> </inline-formula> (1.6 W), the SOI transistor-TEC device with a 10 3.m thick BOX layer can be cooled from 465.7 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C down to 407.4 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C (6. <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\textit{T}$</tex-math> </inline-formula> <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$=$</tex-math> </inline-formula> 58.3 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{\circ}$</tex-math> </inline-formula> C) in peak hotspot temperature when precooled with a 1000 10.s TEC pulse, consuming 0.20 W of TEC power. Furthermore, the SOI transistor-TEC array device provides spatial temperature control by incorporating multiple coolers which enable selective cooling for individual transistor units without significant loss of cooling performance. In summary, our TEC design exhibits great potential in offering dynamic thermal management for a wide range of advanced SOI devices. Silicon on insulator ; Thermal management of electronic devices and systems ; Materials science ; Thermoelectric effect ; Silicon ; Transistor ; Optoelectronics ; Thermal ; Thermoelectric cooling ; Engineering physics ; Electronic engineering ; Electrical engineering ; Engineering ; Mechanical engineering ; Physics ; Voltage ; Thermodynamics Advanced Thermoelectric Materials and Devices ; Thermal properties of materials ; Advancements in Semiconductor Devices and Circuit Design