Authors: Sam Dharmarathna | Sy Maddux
Source: IMAPSource Proceedings (article, 2025-12-05)
Field: Materials Science — Electronic, Optical and Magnetic Materials

Advanced Substrate Metallization in the Era of AI and HPC With the rapid advancement of artificial intelligence (AI) and high-performance computing (HPC), there is an increasing demand for sophisticated semiconductor technologies that can support complex computations and massive data processing. These technologies require advanced packaging solutions that deliver high performance, reliability, and miniaturization. High-density interconnect (HDI) technology plays a crucial role in meeting these requirements, particularly through modified semi-additive processing (mSAP) techniques. As AI and HPC applications push the limits of performance and miniaturization, HDI technology has evolved to meet the growing demands for integrated circuit (IC) substrates and printed circuit boards (PCBs). The move from traditional subtractive print and etch processes to mSAP has enabled the fabrication of finer features such as stacked vias, plated fine traces, and through holes. This shift supports the direct attachment of chips to organic IC substrates and increases the density of redistribution layers, which is essential for routing high-speed signals in advanced computing applications. The mSAP process enhances reliability by starting with a thin copper foil laminated onto an organic prepreg, which improves adhesion for fine lines. Copper is deposited onto this foil with precise imaging patterns, and a subsequent flash etching step removes the foil and electroless copper layer after the resist is stripped, resulting in highly accurate, rectangular fine lines. These fine lines are crucial for maximizing circuit density and achieving precise impedance control with minimal signal loss, which is vital for AI and HPC applications. However, one of the challenges in mSAP is the occurrence of V-pits during the flash etching step, which can compromise the reliability of the final product. To address this issue, some fabricators use an additional baking step to mitigate pitting, but this increases production costs and reduces throughput. Therefore, there is a need for innovative copper electroplating solutions that can provide consistent etching during the flash etching step, effective via filling, and fine line resolution.This study explores the mechanisms behind pitting and proposes new processes to reduce its formation. We investigate various factors affecting pitting, including the choice of plating electrolytes, additive concentrations, plating current densities, etching rates, and baking conditions. Analytical techniques such as X-ray diffraction and focused ion beam scanning electron microscopy (FIB/SEM) were used to analyze the grain structure of the copper deposits.The optimized copper electroplating process discussed in this study demonstrates excellent via filling capabilities, high fine line resolution, and robust through-hole plating in a single bath. The resulting deposits exhibit superior physical properties, such as tensile strength and elongation, exceeding IPC class III requirements. These advancements ensure that HDI technologies can meet the stringent demands of AI and HPC applications, offering reliable and high-performance solutions for the future of computing. Printed circuit board ; Interconnection ; Flash (photography) ; Integrated circuit ; Fabrication ; Etching (microfabrication) ; FOIL method ; Substrate (aquarium) ; Reliability (semiconductor) Copper Interconnects and Reliability ; Nanomaterials and Printing Technologies ; Electronic Packaging and Soldering Technologies