Programmable Logic Devices (PLDs) provide the capability of implementing a wide range of electronic circuits using the same physical device.  This capability is exploited by configuring the device appropriately for each desired application.  The configuring process involves the mapping of the target circuit onto the available resources of the PLD.  Programmable Gate Arrays (PGAs) and Field Programmable Gate Arrays (FPGAS) are the most widely used PLDs.  The architecture of these devices incorporates Look Up Tables (LUTS) that are configured for desired functionality.  The efficiency of mapping algorithms is critical to the effective utilization of PGAs and FPGAs.  In LUT-based FPGAs the mapping is implemented on the LUTs. 
The conventional LUT-based FPGA mapping algorithms can be divided into two classes.  The algorithms in the first class emphasize the minimization of the number of LUTs in the solution.  This class includes “Chortle” and “Chortle-crf” algorithms by Francis, based on tree decomposition and bin packing techniques.  The algorithms in the second class emphasize the minimization of the delay of the solution.  This class includes “Flowmap” by Cong and Y. Ding, which use flow based techniques in mapping with node duplication to reduce the logical depth of the mapped netlist.  See Jason Cong and Yuzheng Ding; An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs; IEEE Trans.  On Computer Aided Design of Integrated Circuits and Systems CAD, Vol.  13, pp 1-12 Jan. 1994. 
A DAG-map (Direct Analysis Graph) method for FPGA technology mapping for delay optimization has been proposed by J. Cong et.al.  See Kuang-Chien Chen, Jason Cong, Yuzheng Ding, Andrew Kahng, Peter Trajmar; DAG-Map: Graph Based FPGA Technology Mapping For Delay Optimization; IEEE Design and test of computers, pp 7-20, September 1992.  This method utilizes a graph based technology mapping algorithm “DAG-Map”, for delay optimization in lookup-table based FPGA designs.  The algorithm carries out technology mapping and delay optimization on the entire Boolean network.  As a preprocessing step in “DAG-Map”, a general algorithm transforms an arbitrary n-input network into a two-input network with a corresponding increase in the network depth; Finally, a graph matching based technique which performs area optimization without increasing the network delay is used as a post processing step for “DAG-Map”.  This method does not however utilize the cascade elements available with each LUT in the FPGA. 
Another optimal technology mapping algorithm for delay optimization in Lookup -Table based FPGA Designs has been proposed by Jason Cong et.  al.  See Jason Cong and Yuzheng Ding; An Optimal Technology Mapping Algorithm for Delay Optimization in Lookup-Table Based FPGA Designs; IEEE Trans.  On Computer Aided Design of Integrated Circuits and Systems CAD, Vol.  13, pp 1-12 January 1994.  This method proposes a polynomial time technology-mapping algorithm, called “Flow-Map”, that optimally solves the LUT-based FPGA technology-mapping problem for depth minimization for general Boolean networks.  A key step in “Flow-Map” is the computation of a minimum height K-feasible cut in a network, by network flow computation.  This algorithm does effectively minimize the number of LUTs by maximizing the volume of each cut and by several post processing operations but it does not utilize the cascade elements with the LUT to further reduce the size of the logic. 
A method for On Area/Depth Trade-off in LUT-Based FPGA Technology mapping has been disclosed in reference by Jason Cong and Yuzheng Ding.  Jason Cong and Yuzheng Ding; On Area/Depth Trade-off in LUT-Based FPGA Technology Mapping; 30th ACM/IEEE design Automation Conference (DAC), pp.  213-218, 1993.  In this method the area and depth trade off in LUT based FPGA technology mapping is proposed by performing a number of depth relaxation operations to obtain a new network with bounded increase in depth and advantageous for subsequent re-mapping for area minimization.  The resulting network is then re-mapped to obtain an area-minimized mapping solution.  By gradually increasing the depth bound for each design a set of mapping solutions with smooth area and depth trade-off is achieved.  For the area minimization step, an optimal algorithm for computing an area-minimum mapping solution without node duplication is developed.  However this method also does not talk about the area minimization by utilizing the cascade elements with each LUT. 
Another method proposed by Jason Cong and Yuzheng Ding proposes an integrated approach to synthesis and mapping that extends the combinatorial limit set up by the depth-optimal “Flow Map” algorithm.  See Jason Cong and Yuzheng Ding; Beyond the Combinatorial Limit in Depth Minimization for LUT-Based FPGA Designs; IEEE/ACM International Conference on Computer Aided Design (IC-CAD), pp.  110-114, November 1993.  The new algorithm, “FlowSYN”, uses global combinatorial optimization techniques to guide the Boolean synthesis process during depth minimization.  The combinatorial optimization is achieved by computing a series of minimum cuts of fixed heights in a network based on fast network flow computation, and the Boolean optimization is achieved by efficient OBDD-based implementation of functional decomposition.  This method also does not utilize cascade elements.