A three-phase inverter serving as a kind of an electrical power converter incorporated in, for example, a large-capacity UPS, a battery energy storage system, or the like is adapted to perform the conversion of a dc voltage supplied from a dc power supply E, such as a solar battery and a fuel cell, into an ac voltage and to supply electric power to loads UL, VL, and WL, as shown in FIG.  7.  The three-phase inverter has a structure in which paired switching elements, which are arranged in an up/down direction, as viewed in this figure, and which correspond to each of a U-phase, a V-phase and a W-phase, for examples, GTO (Gate Turn-Off thyristor) elements UP, UN, VP, VN, WP, WN are connected in a bridge configuration. 
This inverter apparatus is adapted so that the paired GTO elements corresponding to each of the phases are alternately turned on and off, that is, a group of the GTO elements UP, VP, WP, which are shown at upper positions in the figure and correspond to a positive electrode, and a group of the GTO elements UN, VN, WN, which are shown at lower positions in the figure and correspond to a negative electrode, are alternately turned on and off.  Consequently, a dc voltage supplied from the dc power supply E is converted into an ac voltage thereby to supply ac power to the loads UL, VL, and WL, as shown in FIG.  7. 
A sinusoidal waveform control signal is converted into a pulse gate signal by using a triangular waveform carrier signal.  Then, each of the GTO elements UP, UN, VP, VN, WP, and WN is turned on by being applied with a forward bias voltage through the use of the gate driver.  Alternatively, each of the GTO elements UP, UN, VP, VN, WP, and WN is turned off by being applied with a reverse bias voltage through the use of the gate signal. 
On/off control of these GTO elements UP, UN, VP, VN, WP, and WN is performed so that in a case where the GTO elements UP, VP, WP shown at the upper positions are in an on-state, among the paired GTO elements, and where the GTO elements UN, VN, WN shown at the lower positions are in an off-state, when the GTO elements UN, VN, WN shown at the lower positions are turned on, the GTO elements UP, VP, WP shown at the upper positions are turned off before the GTO elements UN, VN, WN turn on. 
A dead time, in which the GTO elements UP, VP, WP, UN, VN, WN of both of the group shown at the upper positions and that shown at the lower positions are simultaneously brought into a turned-off state, is provided to turn on the GTO elements UN, VN, WN shown at the lower positions after a predetermined interval elapses after the GTO elements UP, VP, WP shown at the upper positions turn off.  Consequently, both of the group of the GTO elements UP, VP, WP shown at the upper positions and that of the GTO elements UN, VN, WN shown at the lower positions are prevented from simultaneously being put into a turned-on state.  Thus, an occurrence of a dc shortcircuit is prevented (see, for example, JP-A-10-112984).