Flash memory devices are a popular form of nonvolatile storage.  Flash memory devices can retain information when no power is supplied to the device.  Flash memory devices include memory cells that include a gate stack, a source and a drain.  Each gate stack also includes a control gate separated from the floating gate by an insulating layer.  The insulating layer is typically a composite ONO layer including two oxide layers separated by a nitride layer.  The control gate and the floating gate are typically formed of polysilicon.  Some memory cells may be separated by field oxide regions.  Contact is made to the source and drain regions as well as to the gate stacks
In conventional flash memory devices, particularly in NAND technology, it may be desirable to provide other components using one of the polysilicon layers which form the floating gate and control gate.  For example, the first polysilicon layer may be used to form resistors or other components for the flash memory device.  Consequently, contacts are desired to be provided to the gate stacks, the source and drain regions and the components comprised of the first polysilicon layer. 
FIG.  1 depicts a conventional method for providing a conventional flash memory device, such as a NAND device, that includes components, other than the gate stacks, which use one of the polysilicon layers.  For clarity, it is assumed that the first polysilicon layer is used.  Such components will also be called poly-1 components.  The gate stacks, source and drain regions and poly-1 components are formed, via step 12.  Typically, step 12 includes forming field oxide regions, depositing a first polysilicon layer, forming the ONO layer, patterning the ONO and first polysilicon layers, depositing a second polysilicon layer with the poly-1 component already patterned, and etching the second polysilicon layer and ONO layer to form the gate stacks and the poly-1 component.  Step 12 also typically includes implanting the source and drain regions.  From the perspective of contact formation, source and drain regions are similar.  Consequently, all such regions are referred to as source/drain regions.  Often, step 12 also includes forming a silicide, usually a tungsten-silicide, on the gate stacks and providing a capping layer including SiON on the gate stack. 
An insulating layer is then formed, via step 14.  The insulating layer covers the source/drain regions, the gate stacks, the field oxide regions and the poly-1 components.  Contact holes are then etched, via step 16, to allow electrical contact to the gate stacks, the source/drain regions, and the poly-1 components.  Typically, the contact holes for the gate stacks, the source/drain regions, and the poly-1 components are etched simultaneously.  The contact holes may then be filled with a conductive material, via step 18. 
Although the conventional method 10 functions, one of ordinary skill in the art will readily realize that it is difficult to provide contact to the poly-1 components using the conventional method 10.  FIGS.  2A and 2B depict a conventional flash memory device 50 fabricated using the conventional method 10.  FIG.  2A depicts the conventional flash memory device 50 prior to formation of contact holes.  The conventional flash memory device 50 includes a substrate 52 on which a gate stack 60, source/drain regions 56 and 58, oxide layer 55 and field oxide 54 are formed.  The gate stack 60 includes a floating gate 62, an insulating layer 64, a control gate 66, a tungsten silicide layer 68 and a SiON layer 70.  Spacers 72 and 74 can be formed on opposite sides of the gate stack 60.  The floating gate 62 and control gate 66 are formed from first and second polysilicon layers, respectively.  The insulating layer 64 is typically an ONO layer 64, which includes two layers of oxide separated by a nitride layer.  Also depicted is a poly-1 component 76 which includes a polysilicon layer 76 and happens to be located on the field oxide region 54.  On the poly-1 component 76 is an ONO layer 78.  The poly-1 component 76 may be formed using the first polysilicon layer.  Similarly, the ONO layer 78 may be formed using the same ONO layer that forms the ONO layer 64.  Blanketing the gate stack 60, the source/drain regions and the poly-1 component is an insulating layer 80, which is typically formed of oxide. 
FIG.  2B depicts the conventional flash memory device 50 after the contact holes have been etched using step 16 of the method 10.  Referring back to FIG.  2B, the contact holes 82, 84, and 86 are of very different depths.  The contact hole 82 to the gate stack 60 is the shallowest.  The contact hole 84 to the source/drain region 56 is the deepest.  The contact hole 86 to the poly-1 component 76 has a medium depth.  Typically, the contact holes 82, 84 and 86 are etched concurrently.  Furthermore, because the percentage of area occupied by the contact holes 82, 84 and 86 is small, endpoint detection using conventional techniques is difficult.  Consequently, some overetch is usually performed. 
Because of the etch used to form the contact hole 82, 84 and 86, the poly-1 component 76 may be destroyed.  The tungsten silicide layer 68 prevents the gate stack 60 from being etched through.  The source/drain region 56 is the deepest to which contact is made and the etch stops at the silicon.  Thus, the etch does not substantially harm the source/drain region 56.  However, the poly-1 component 76 and the ONO layer 78 have been etched partially or wholly through.  Consequently, the poly-1 component may be destroyed.  The etch may even remove the field oxide region 54 under the poly-1 component 76.  Removal of the field oxide region 54 could expose the underlying silicon substrate 52, which is undesirable.  The conventional flash memory device 50 may, therefore, not operate as desired. 
Accordingly, what is needed is a system and method for providing contacts to the poly-1 components without destroying the poly-1 components or underlying structures.  The present invention addresses such a need.