The present invention relates to a method and controller for transferring data by direct memory access, more particularly to a method and controller employing a restricted block transfer mode. 
Direct memory access has long been used to transfer data at high speed over data buses in computing and communication equipment, bypassing the equipment's central processing unit (CPU).  In the restricted block transfer mode, the data can be transferred in blocks, but the block size is restricted to certain values.  After the transfer of each block, direct memory access pauses to allow memory access by the CPU or another device.  The restricted block transfer mode is useful when, for example, the memory structure permits rapid access to blocks of data that do not cross certain forbidden address boundaries. 
One way to avoid crossing such address boundaries is to restrict the starting and stopping addresses of data transfers to certain address values.  Such restrictions are undesirable, however, because they often force unnecessary data to be transferred. 
If the starting and stopping addresses are not restricted, then to avoid crossing forbidden address boundaries, a data transfer may have to be divided into a plurality of sections, and a different block size employed in each section.  Conventional direct memory access controllers are not adapted to do this, however; normally, the block size must be set and changed by the CPU.  CPU interrupts must accordingly be generated during the course of the transfer, which slows the transfer and causes undesirable CPU overhead.