The development of semiconductor switching technology for high power applications in motor drive circuits, appliance controls, robotics and lighting ballasts, for example, began with the silicon bipolar junction transistor.  As the technology matured, bipolar transistors became capable of handling large current densities in the range of 40-50 A/cm.sup.2, with blocking voltages of 600 V.
However, despite the attractive power ratings achieved by bipolar transistors, there exist several fundamental drawbacks to their suitability for all high power applications.  First of all, bipolar transistors are current controlled devices.  For example, a large control current into the base, typically one fifth to one tenth of the collector current, is required to maintain the device in an operating mode.  Even larger base currents, however, are required for high speed forced turn-off.  These characteristics make the base drive circuitry complex and expensive.  The bipolar transistor is also vulnerable to breakdown if a high current and high voltage are simultaneously applied to the device, as commonly required in inductive power circuit applications.  Furthermore, it is difficult to parallel connect these devices since current diversion to a single device occurs at high temperatures, making emitter ballasting schemes necessary. 
The silicon power MOSFET was developed to address this base drive problem.  In a power MOSFET, a gate electrode bias is applied for turn-on and turn-off control.  Turn-on occurs when a conductive channel is formed in the base, between the MOSFET's source and drain regions, under an appropriate gate bias.  As will be understood by one-skilled in the art, the length of the channel is dependent on the rate of diffusion of the source and base dopants.  The length of the channel is also an important design parameter in power MOSFETs because it has a strong influence on the on-resistance and the transconductance. 
The gate electrode is separated from the device's channel by an intervening insulator, typically silicon dioxide.  Because the gate is insulated from the channel, little if any gate current is required in either the on-state or off-state.  The gate current is also kept small during switching because the gate forms a capacitor with the device's active area.  Thus, only charging and discharging current ("displacement current") is required.  The high input impedance of the gate, caused by the insulator, is a primary feature of the power MOSFET.  Moreover, because of the minimal current demands on the gate, the gate drive circuitry can be easily implemented on a single chip.  As compared to silicon bipolar technology, the simple gate control provides for a large reduction in cost and a significant improvement in reliability.  An example of a known power MOSFET is the DMOS structure, illustrated at FIG.  1, and described in a textbook by coinventor Baliga, entitled Modern Power Devices (1987), p 265. 
Power MOSFETs of the type herein described have typically been formed in silicon.  However, because of the physical, thermal and electrical properties of silicon carbide, it is believed that power MOSFETs formed of silicon carbide may provide significant performance advantages over silicon power MOSFETs.  This is because silicon carbide has a wide bandgap (2.2 eV at 300K) a high melting point (3103K, 30 atms), a small dielectric constant (9.3), a high breakdown field strength (2.5.times.10.sup.6 V/cm), a high thermal conductivity (1.5 W/cm-.degree.  C.) and a high saturated electron drift velocity (2.times.10 .sup.7 cm/sec. )  compared to silicon, which is the most commonly used semiconductor material.  These characteristics allow silicon carbide microelectronic devices to operate at higher temperatures and higher power levels than conventional silicon based devices. 
In addition to the above advantages, silicon carbide power devices can operate with lower specific on-resistance than conventional silicon power devices.  Some of the advantages of using silicon carbide for forming power semiconductor devices are described in articles by K. Shenai, R. S. Scott, and coinventor B. J. Baliga, entitled Optimum Semiconductors for High-Power Electronics, IEEE Transactions on Electron Devices, Vol.  36, No.  9, pp.  1811-1823 (1989); and by coinventors M. Bhatnagar and B. J. Baliga entitled Analysis of Silicon Carbide Power Device Performance, ISPSD '91, Abstr.  8.3, pp 176-180 (1991). 
The process for manufacturing the silicon based DMOSFET device of FIG.  1 includes diffusing the P-base and N.sup.+ source regions into the substrate.  For silicon, it is possible to obtain P-N junctions well beneath the surface of the substrate using diffusion, since diffusion rates for dopants in silicon are relatively high even at relatively low temperatures on the order of 1000-1200 degrees Centigrade.  It is therefore possible to obtain P-N junctions in silicon as deep as 1-3 microns. 
The ability to obtain deep junctions in silicon is an important feature in the design of power MOSFETs and, in particular, is a factor in determining the forward blocking capability and punch-through breakdown condition.  For example, as will be understood by one skilled in the art, despite the short-circuiting of the N.sup.+ emitter to the P-base, via the source contact as shown in FIG.  1, the DMOSFET will conduct current under reverse bias as soon as the depletion layer in the P-base punches through to the N.sup.+ emitter and the N.sup.+ emitter begins injecting electrons into the P-base region.  Because of the opportunity for punch-through, the shape of the doping profiles in the P-base and N.sup.+ emitter and the respective doping concentrations are important design considerations.  A typical diffusion profile for the DMOSFET of FIG.  1 is shown in FIG.  2.  The solid lines indicate the doping distributions, whereas the dashed lines show the resulting carrier concentration profiles, which differ from the dopant profiles as a result of compensation effects.  The surface concentration N.sub. SP of the P-base diffusion and the N.sup.+ emitter depth combine to determine the peak doping N.sub. AP in the P-base as indicated by the arrow.  The depths of the P-base and N.sup.+ -emitter diffusions are respectively denoted as X.sub. P and X.sub. N+. 
In addition to the above-mentioned design considerations including peak dopant concentration and profile, the channel length "L" between the edge of the source and drain regions beneath the gate is also important because it has a strong influence on the on-resistance of the device and the device's transconductance.  Moreover, because of the need to maintain a low peak P-base concentration and a short channel length to achieve good on-state characteristics, conventional techniques for raising the punch-through threshold generally restrict the ability to obtain preferred on-state characteristics unless other steps can be taken to limit the peak concentration in the P-base region and simultaneously provide sufficient resident charge to prevent punch-through to the N.sup.+ emitter.  With respect to FIG.  2, this would include steps to limit the peak concentrations in each region while also maintaining the total area under the respective curve for each region at the same value.  To achieve this, more uniform doping profiles that extend as far into the substrate as the diffused profiles would be required. 
In contrast to silicon, the diffusion coefficients of conventional P and N-type dopants in silicon carbide are small in the temperature range of 1000-1200 degrees Centigrade.  In fact, temperatures on the order of 1500 degrees Centigrade and higher are generally required for diffusion to occur at appreciable rates.  For example, in an invited paper by R. J. Trew, J. B. Yan and P. M. Mock, entitled The Potential of Diamond and SiC Electronic Devices for Microwave and Millimeter-Wave Power Applications, Proc.  of the IEEE, Vol.  79,No.  5, pp.  598-620 (1991), temperatures on the order of 1900 degrees Centigrade were specified as being required for the diffusion of N or P-type dopants in silicon carbide.  Unfortunately, this extreme range of temperatures is not compatible with the fabrication of integrated semiconductor devices having multiple layers of different conductivity type material.  These temperatures are also considerably above the melting point of SiO.sub.2, a diffusion masking material having no commercially acceptable alternative for high temperature processing.  Given these limitations, it is generally accepted that P-N junction formation arising from epitaxial growth or ion implantation with boron (B) or aluminum (A1) (p-type) or phosphorus (P) or nitrogen (N) (n-type) is most suitable for silicon carbide. 
Unfortunately, although there has been a general acceptance of ion-implantation as a technique for forming P-N junctions in silicon carbide, problems including out-diffusion of dopant species, the precipitation of defect clusters, and the formation of electrically active line and point defects causing poor dopant ionization are encountered in the formation of lateral MESFETs and MOSFETs.  For example, in an article by J. W. Bumgarner, H. S. Kong, H. J. Kim, J. W. Palmour, J. A. Edmond, J. T. Glass, and R. F. Davis, entitled Monocrystalline .beta.-SiC Semiconductor Thin Films: Epitaxial Growth, Doping and FET Device Development, 1988 Proc.  38th Electronics Components Conf.,  pp.  342-349, solid phase epitaxial re-growth of the amorphous regions caused by the implantation of boron was achieved by annealing at 1600 degrees Centigrade for 300 seconds.  However, defect clusters of precipitates and vacancy loops formed near the center of the amorphous regions within the implanted region.  Subsequent annealing at 1800 degrees Centigrade for 300 seconds promoted virtually defect free regrowth, but SIMS analysis revealed almost complete out-diffusion of the implanted boron ions. 
The implantation of P or N-type dopant species also results in the formation of an implant profile having a peak concentration below the implant surface.  As well understood by those skilled in the art, the implant profile can generally be approximated by a Gaussian curve, or for greater accuracy, a four-moment Pearson-IV curve.  However, even after annealing, which may cause diffusion away from the peak concentration region, a non-uniform doping profile in the N or P-type region is present.  Accordingly, it is difficult to achieve a great degree of uniformity in regions formed by ion implantation. 
Thus, while ion-implantation may be used as a technique for forming regions of P and N-type conductivity in silicon carbide, it would be preferable to manufacture silicon carbide power MOSFETS that have more uniform deep-diffused junctions than obtainable using ion-implantation techniques alone.