1.  Field of the Invention
The present invention relates to a semiconductor device and a control method used by the same, and more particularly, to a semiconductor device capable of precisely controlling an on-die-termination (ODT) circuit and an off-chip-driver (OCD) circuit and a method of controlling the same. 
2.  Description of the Related Art
The effects of the flow of data, data strobes, and AC parameters related to input and output of addresses and control signals have become increasingly more critical to the design of high-frequency double data rate (DDR) semiconductor devices.  The electrical characteristics of a channel connecting two or more components, e.g., a DRAM or a CPU, can often be more important than those of the components themselves. 
A plurality of components are connected by a channel, and a signal is input and output though a pad included in each component.  A signal output from a component passes through an off-chip-driver (OCD) circuit, usually with impedance control and is output to a channel via a pad.  In addition, a signal from the channel passes through an on-die-termination (ODT) circuit and is input to the component via the pad. 
The ODT and OCD circuit within the component are implemented with adjustable impedance to improve the electrical characteristics of the channel.  The impedance is adjusted by a control code generated by a calibration loop or a code controller unit. 
The calibration loop generates a control code for adjusting the impedance of the ODT and OCD circuit in response to a control signal input from an external source.  Similarly, the code control unit generates a control code for adjusting the impedance of the ODT and OCD circuit in response to a control signal, which is generated in response to an external mode register set signal. 
FIGS.  1 and 2 are block diagrams of conventional semiconductor devices 100 and 200 capable of controlling ODT circuits 130 and 230, and OCD circuits.  Referring to FIG.  1, the semiconductor device 100 includes a calibration loop 110, the ODT circuit 130, and a pad 150.  The calibration loop 110 generates first and second control codes CTRL1 and CTRL2 to adjust the impedance of the ODT circuit 130 in response to a control signal EXZQ, which is generated in response to the impedance of an external reference resistor (not shown). 
The impedance of the ODT circuit 130 is adjusted to match the characteristics of a channel (not shown).  Accordingly, a signal is input to the semiconductor device 100 without distortion caused by noise or channel characteristics. 
As illustrated in FIG.  1, the ODT circuit 130 includes a plurality of upper transistors that operate in response to the first control code CTRL1 and a plurality of lower transistors that operate in response to the second control code CTRL2. 
The transistors included in the ODT circuit 130 are turned on or off in response to the first and second control codes CTRL1 and CTRL2.  By adjusting transistor states, one can adjust the overall impedance of the ODT circuit 130. 
Although not shown in FIG.  1, the semiconductor device 100 of FIG.  1 may further include an OCD circuit.  The impedance of the OCD circuit (not shown) may be adjusted by using the method of adjusting the impedance of the ODT circuit 130. 
Referring to FIGS.  1 and 2, the semiconductor device 200 of FIG.  2 has the same structure as the semiconductor device 100 of FIG.  1 except that the semiconductor device 200 uses a code controller 210 instead of the calibration loop 110. 
The code controller 210 generates first and second control codes CTRL1 and CTRL2, which are binary signals, in response to a control signal EMRS generated in response to an external mode register set signal.  The impedance of the ODT circuit 230 is adjusted in response to the first and second control codes CTRL1 and CTRL2. 
The semiconductor device 100, using the calibration loop 110 that operates in response to an external control signal, or the semiconductor device 200, using the code controller 210 that operates in response to the control signal EMRS generated in response to the external mode register set signal, can generate definite control codes unaffected by process, voltage, and temperature changes. 
However, the conventional semiconductor device 100 or 200 may have an offset due to various external factors, including process, voltage, and temperature (PVT) variations.  In addition, although the semiconductor device 100 or 200 is designed to have a minimum offset, the channel characteristics of the semiconductor device 100 or 200 needs to be improved.  Therefore, the impedance of the semiconductor device 100 or 200 should be adjusted precisely to improve performance. 
As the semiconductor device 100 or 200 operates at higher and higher frequencies, the driver intensity and impedance of the OCD circuit need to be controlled more precisely.  However, the semiconductor device 100 or 200 cannot alter the fixed external resistance even when the impedance of the OCD circuit needs to be adjusted to improve channel characteristics.  Thus, it is difficult to precisely control the impedance of the OCD circuit. 
If the number of bits of the external mode register set signal used in the code controller 210 is increased, the impedance of the OCD circuit may be more precisely controlled.  However, an increase in the number of bits of the external mode register set signal complicates the circuit structure of the semiconductor device 200.