Many portable products, such as cell phones, laptop computers, personal digital assistants (PDAs) or the like, incorporate one or more processors executing programs that support communication and multimedia applications.  The processors for such products conventionally have a hierarchical memory configuration with multi-levels of caches including an instruction cache, a data cache, and system memory.  The processors also need to operate with high performance and efficiency to support the plurality of computationally intensive functions for such products.  The processors are typically pipelined and support execution of conditional branch instructions. 
The execution of a conditional branch instruction on a pipelined processor may stall the pipeline pending the determination of the condition.  In order to avoid stalling the processor, some form of branch prediction is typically employed early in the pipeline allowing the processor to speculatively fetch and execute instructions based on a predicted branch behavior.  If a conditional branch is mispredicted, the associated speculatively fetched instructions are flushed from the pipeline and new instructions are fetched from the determined branch address.  Such misprediction reduces processor performance and increases power usage. 
Conventional approaches to branch prediction are limited due to the implementation cost and complexity of branch prediction circuits, all of which consume power.