(1) Field of the Invention
The present invention relates to a method used to fabricate a capacitor structure, for a dynamic random access memory, (DRAM), device, and more specifically a method of fabricating a storage node electrode, for a crown shaped, DRAM capacitor structure, optimizing surface area, and minimizing capacitance depletion. 
(2) Description of the Prior Art
The use of hemispherical grain, (HSG), silicon layer, as the surface layer of a storage node electrode, has allowed increases in DRAM cell capacitance to be realized.  The concave and convex features of the HSG silicon layer, result in surface area increases, when compared to counterparts fabricated with smooth surfaces.  The attainment of a HSG silicon layer usually features the formation of HSG silicon seeds, on a silicon storage node shape, followed by an anneal cycle, used to grow the HSG silicon layer, via consumption of the HSG silicon seeds and a top portion of the underlying silicon storage node shape.  In order to enhance the formation of the HSG silicon layer, an undoped, or lightly doped, silicon storage node shape is preferred.  However the use of undoped, or lightly doped, silicon storage node shapes, result in undoped, or lightly doped HSG silicon layers, which can result in a performance degrading, capacitance depletion phenomena, thus negated the capacitance benefits arrived at via the use of the increased surface area of the HSG silicon layer. 
Methods used to solve the capacitance depletion phenomena, resulting from the formation of HSG silicon layers, using undoped, or lightly doped, silicon storage node shapes, have been either a phosphorous ion implantation, into the HSG silicon layer, or a phosphine anneal procedure, applied to the HSG silicon layer.  A shortcoming of the phosphorous ion implantation procedure, is the anisotropic nature of this procedure, limiting the level of dopant in the convex and concave features of the HSG silicon layer.  The use of phosphine annealing, results in a phosphorous rich layer, at the surface of the HSG silicon layer, and can result in the formation of a P.sub.2 O.sub.5 layer at the surface of the HSG silicon layer, when exposed to air, with the formation of the P.sub.2 O.sub.5 layer depleting the phosphorous concentration in the HSG layer. 
This invention will offer a procedure for doping of the HSG silicon layer, via selective deposition of a doped polysilicon layer, only on the HSG silicon layer, which is located as the top layer of a storage node shape.  The selectively deposited, doped polysilicon layer, can be deposited, in situ, in the same UHV system, or in situ, in the same chamber of a cluster tool, used for the selective formation of the HSG silicon layer, on an underlying amorphous silicon, storage node shape.  Prior art, such as Akram et al, in U.S. Pat.  No.  5,753,558, or Dennison et al, in U.S. Pat.  No.  5,340,765, describe processes used to create HSG silicon layers, but none of the prior arts describe the use of a selectively deposited, doped polysilicon layer, on an underlying HSG silicon layer, used to reduce the capacitance depletion phenomena, arising from lightly doped, HSG silicon layers.