1.  Field of the Invention
The present invention relates to a multilayer chip capacitor, and more particularly, to a multilayer chip capacitor suitably used as a decoupling capacitor of a power distribution network of a digital switching circuit such as a micro processor unit (MPU) and capable of maintaining a power network distribution network impedance at a low level in a broad frequency range as a single capacitor, a motherboard apparatus having the same and a power distribution network. 
2.  Description of the Related Art
A power distribution network (PDN) of a micro processor unit (MPU) is designed with increasing difficulty due to higher speed and more integration of the MPU.  Notably, a decrease in a power voltage and an increase in an MPU consumption current resulting from more integration of the MPU has been gradually lowering a target impedance Ztarget, as represented by following Equation 1:Ztarget=Vp×AR/I=Vr/I  Equation 1,
where Vp is a power voltage, AR is an allowed ripple, I is an MPU consumption current, an Vr is an allowed ripple voltage. 
A general ripple voltage Vr is a value equal to 5˜10% of the power voltage.  The target impedance Ztarget should be satisfied not only in a direct current (DC) but also in all frequencies where a transient current is present.  A personal computer (PC) or a laptop computer undergoes a transient current even in a very high frequency range due to higher speed of a central processing unit (CPU), i.e., MPU chip and thus should satisfy a target impedance even in a broad frequency range.  To satisfy the target impedance in each frequency range, the PDN employs a voltage regulator module (VRM), a bulk capacitor, a general two-terminal MLCC and a low equivalent series inductance (ESL) MLCC.  This PDN is referred to as a multi-stage PDN (see FIG.  23B). 
The VRM, bulk capacitor and general two-terminal multilayer chip capacitor (MLCC) supply a current in a frequency range of several kHz, several kHz to hundreds of kHz, hundreds of kHz to several MHz, respectively and serve to lower impedance of the PDN.  Unlike the bulk capacitor or general two-terminal MLCC directly installed on a motherboard, the low ESL MLCC is typically installed on a CPU package to supply a current in a frequency range of at least several MHz and reduce impedance.  Finally, a die capacitor within the CPU supplies a current and lowers impedance of the PDN in a frequency higher than an effective frequency of the low ESL MLCC.  The plurality of bulk capacitors, general two-terminal MLCC and low ESL MLCC are connected in parallel to one another. 
FIG.  1 is a schematic graph illustrating magnitude of impedance Z with respect to frequency of a general multi-stage PDN.  In each stage, the VRM, bulk capacitor, general two-terminal MLCC, low ESL MLCC and die capacitor have respective impedances ZREG, ZBLK, ZMF, ZPKG, and ZDIE determining the impedance of an entire PDN.  Accordingly, as shown, impedance of an individual capacitor greatly affects an impedance profile of the entire PDN.  Also, an impedance of a previous stage capacitor is associated with an impedance of a next stage capacitor to determine the impedance of the entire PDN.  In designing the PDN, an impedance at the each stage cannot be determined independently but the impedance of the entire PDN should be considered.  A general two terminal MLCC which has a relatively higher ESL is installed on a motherboard or CPU package for mid-frequency decoupling.  Also, a low ESL MLCC is installed in the CPU package for high-frequency decoupling.  In a case where the PDN is designed to satisfy impedance characteristics in a wider frequency range, a greater number of decoupling capacitors may be utilized to cover wide frequency ranges (see FIG.  23B). 
FIG.  2 schematically illustrates a conventional motherboard apparatus having decoupling capacitors connected thereto by MPU power circuits.  Referring to FIG.  2, a CPU, i.e., MPU chip 51 is surface-mounted on a package board 53 to form CPU packages 51 and 53.  Theses CPU packages 51 and 53 are surface-mounted onto a motherboard 55.  Circuit conductors such as power (PWR) planes, ground (GND) planes, vias are provided inside and on an outer surface of the motherboard 55 and the package board 53 to configure a power circuit.  Also, bumps or pins 15 are utilized to electrically connect the components 53 and 55.  Decoupling capacitors 10 and 20 of different types according to the frequency range are connected to this power circuit to form a multi-stage PDN.  The low ESL MLCC 10 for high-frequency decoupling, for example, a low inductance ceramic capacitor (LICC) or an interdigital capacitor (IDC) may be disposed on a bottom of the CPU package 53.  The general MLCC 20 for mid-frequency decoupling may be directly disposed on a top or bottom of the motherboard 55 in the vicinity of the CPU packages 51 and 53, or installed on the bottom of the CPU package 53. 
As described above, to form the multi-stage PDN, the capacitors 10 and 20 of different structures according to each frequency range should be employed.  Accordingly, mounting surfaces or mounting positions of the capacitor need to be different according to the each frequency range.  Moreover, a greater number of the chip capacitors 10 and 20 are required to lower total impedance of the PDN to a target impedance or less.