Size reduction of field-effect transistors (FETs), including reduction of the gate length and gate oxide thickness, has enabled the continued improvement in speed, performance, density, and cost per unit function of integrated circuits over the past few decades.  In recent years, advances in technology have yielded a transistor design that utilizes raised source/drain regions having one or more raised channel regions (referred to as fins) interconnecting the source and drain regions.  A gate is formed by depositing a conductive layer over and/or adjacent to the fins.  This type of transistor is commonly referred to as a FinFET.  It has been found that FinFET designs provide better scalability as design requirements shrink and better short-channel control. 
FIG.  1 illustrates a perspective view of a dual-fin FinFET 100 of the prior art.  The FinFET 100 includes a source 110 and a drain 112 interconnected by fins 114.  A gate electrode 116 comprises a contact area and a line that extends over the fins 114.  In this embodiment, current flows from the source 110 to the drain 112 when a voltage is applied to a gate electrode 116.  Problems, however, may occur during fabrication that may adversely affect the performance of the FinFET. 
FIGS.  2a-2f, which are cross-section views taken along the A-A line of FIG.  1, illustrate one such problem that results from the topography of the fin and the source/drain regions.  Referring first to FIG.  2a, a gate electrode 116 is deposited over the etched fins 114.  As illustrated in FIG.  2a, the topography of the underlying fins 114 and source/drain regions (not shown) is transferred on to the gate electrode 116.  This may result in severe drop-off in the surface of the gate electrode film over the fins 114 and source/drain regions. 
In FIG.  2b, an anti-reflective coating (ARC) (or other masking material) 210, which acts as a hard mask, is spin coated onto the surface.  FIG.  2c illustrates the situation after a photo-resist has been applied and patterned, and an etching step has been performed to remove unwanted portions of the ARC 210.  The etching step typically uses an end-point signal to indicate when the gate electrode 116 has been exposed.  Often, however, residual ARC remains after the ARC open step in areas in which the ARC is thicker, such as regions 220 of FIG.  2c.  This results in incomplete hard mask open in areas with severe topography. 
FIG.  2d illustrates the FinFET after an over-etch process has been performed to attempt removal of the remaining ARC 210.  As illustrated in FIG.  2d, however, some of the ARC 210 remains after the over-etch process.  Performing the over-etch process for a longer duration is not typically preferred due to damage that may occur to the underlying gate electrode 116. 
FIG.  2e illustrates the resulting structure after an etch is performed to remove the excess gate electrode material.  As illustrated, the excess ARC 210 causes residual gate electrode material, e.g., parasitic spacers 222, running along the outer periphery of the active area.  These parasitic spacers 222 may adversely affect the performance of the FinFET. 
FIG.  2f is a plan view of the dual-fin FinFET 100 illustrated in FIG.  1 after performing the process described above.  Note that the parasitic spacers 222 are formed around the source/drain regions and the fins 114.  These parasitic spacers (or residual poly stringers) 222 can adversely affect the performance of the FinFET, and in some cases, the parasitic spacers 222 can cause electrical shorts between the gate and the source/drain regions, rendering the FinFET inoperable. 
This problem may be prevented or reduced when using 248 nm lithography processes because of the large resist budget.  This allows an excessive over etch during the ARC open process, thus ensuring that all excess ARC is cleared in all areas.  However, some processes require a smaller resist budget mask in the gate electrode definition.  For example, processes for fabricating FinFET devices having sub 50 nm gates utilize 193 nm lithography technology have very small resist budget mask in the gate electrode definition.  In these cases, an over-etch process may not be practical. 
One attempt to solve this problem is a thick-layer approach, which involves forming a thick gate electrode, which is typically thicker than the height of the fins.  An etch-back process is performed to reduce the thickness of the gate electrode, resulting in a layer that is more planarized than the surface of the beginning gate electrode.  As a result of the more planarized surface, an ARC layer may be deposited and patterned such that the excess ARC layer is completely removed, preventing the parasitic spacers described above. 
One disadvantage of the thick-layer approach is that the very thick poly-layer itself causes a higher degree of film thickness non-uniformity in the deposited film.  This initial non-uniformity can further be worsened by the plasma etch-back process that would typically be a fixed-time etch process where no endpoint signal is employed. 
Therefore, there is a need for a method to form a FinFET without having a parasitic spacer formed around the fins and the source/drain regions.