Due to high integration and high speed of metal oxide semiconductor field effect transistors (MOSFET), various processes have been studied to form transistors that do not generate errors and have excellent performance.  Particularly, many processes are developed to increase mobility of electrons or holes in order to produce high-performance transistors. 
A process of applying physical stress to a channel area to change an energy band structure of the channel area may be performed to increase the mobility of the electrons or the holes.  For example, NMOS transistors have improved performance in the case of when tensile stress is applied to a channel, and PMOS transistors have improved performance in the case of when compressive stress is applied to a channel.  Accordingly, a dual stress film structure where a tensile stress film is formed on the NMOS transistor and a compressive stress film is formed on the PMOS transistor to improve performances of both the NMOS transistor and the PMOS transistor has been studied. 
However, in the case of when the dual stress film is applied, an area where the tensile stress film and the compressive stress film partially overlap may be formed at the interface of the NMOS transistor and the PMOS transistor according to characteristics of devices or photolithography margins.  The overlapping area of the stress film is thicker than the area where the single stress film is layered.  Therefore, in the case where contact holes are formed through the single stress film and the overlapping area using an etching process, the contact holes are first formed through the single stress film, and a lower stricture of the contact holes which are formed beforehand may be attacked before the contact holes are formed through the overlapping area.  Accordingly, contact characteristics and reliability of the semiconductor device may be reduced.