Prior art computer systems, such as computer system 10 of FIG.  1, employ various levels of software.  At a high level are application programs and operating systems, available over-the-shelf to consumers.  At a lower level are the system (BIOS) and device drivers that are responsible for manipulating basic interactions among hardware components within the computer system. 
The different levels of software typically reside on a permanent form of data storage device.  For instance, the BIOS is typically burned into one or more ROM devices that are used along with DRAM to implement system memory 130.  The application programs and operating systems typically reside on hard drive 151.  These permanent forms of data storage are slow to access.  When it is necessary for the program to be executed, the program or a portion thereof is loaded into system memory 130 so as to decrease execution times. 
The microprocessor 110 is illustrated in FIG.  1 as a multi-chip module (CM) that comprises not only the main processor 111 but also the second level (L2) cache 112, an advanced programmable interrupt controller (APIC) 113, and a bus interface unit 114.  One example of an MCM is the Pentium. RTM.  Pro processor, manufactured by Intel Corporation of Santa Clara, Calif.
The memory controller and bridge chip 120 is responsible for communications between the microprocessor 110, the system memory 130, and the system bus 140.  The system memory 130 typically comprises dynamic random access memory (DRAM).  The system memory may additionally comprise one or more ROM devices that contain boot-up code. 
System bus 140 is a high-speed bus that is coupled to peripheral devices 160, which may include a graphics accelerator, fax modem board, sound card, and other add-in boards.  The system bus 140 is also coupled to the hard drive controller 150.  The hard drive controller interfaces between the system bus 140 and the hard drive 151.  As mentioned previously, both the system memory 130 and the hard drive 151 may include software that is executed by the microprocessor 110. 
Prior art microprocessors employ privilege levels that are assigned to each level of software.  The segmented addressing scheme common to Intel architecture processors (e.g. the Pentium. RTM.  Pro processor), facilitates the privilege level scheme.  These processors have four levels of privilege.  Privilege level 0 is the highest privilege level, and therefore code executing at this privilege level has access to the most features available.  Privilege level 3 is the lowest privilege level, and is therefore most restrictive as to which features are available to code executing at this privilege level.  Privilege level 0 is typically reserved for the operating system "kernel," that contains the most critical code modules of the operating system.  Privilege level 3 is often referred to as the "user level," which is typically the level of execution of the user application programs, such as word processors, spread sheets, and desktop publishers. 
A program executing at one privilege level may switch execution to a program executing at another privilege level.  This is typically accomplished through a call gate, task gate, or interrupt gate.  FIG.  2 illustrates a block diagram of a prior art call from a procedure at a user privilege level to a procedure within an operating system kernel. 
For the example shown in FIG.  2, the call from user code 210 to kernel code 240 occurs in two steps.  First, the user code 210 at privilege level 3 executes a far call instruction to a software routine that is at privilege level 0.  In prior art processors, this far call occurs through a gate 220.  The gate is a tightly-controlled interface that protects the kernel code at privilege level 0 from being interfered with by a user at a lower privilege level. 
The address associated with the call instruction in user code 210 points to a call gate descriptor 220.  The call gate descriptor provides information about the privileged code 230 being called.  For instance, the call gate descriptor provides access rights, information about the new code segment, the new privilege level, and information about the new stack segment. 
In transferring execution from a privilege level 3 procedure 210 to a privilege level 0 procedure 230, the CALL instruction performs many state-saving operations.  Some of the architectural state of the computer (the values of several predetermined registers) is pushed on to the stack before control is transferred to the called procedure 230.  Then, when a return instruction (RET) is asserted within the privileged code 230, the contents of the stack are restored to the appropriate registers. 
If it is determined that the calling procedure 210 has the appropriate access rights to the called procedure 230, then execution transfers to the privileged code 230.  Within the privileged code 230, another call is performed in order to switch to the kernel code 240. 
Similarly to the first call instruction in user code 210, the call instruction in privileged code 230 performs many state-saving operations.  Once again, some of the architectural state of the computer is saved before execution is transferred from the privileged code 230 to the kernel code 240.  A detailed description of the prior art procedure calls described above can be found within the Pentium Pro Family Developer's Manual, vols.  1-3, available from Intel Corporation of Santa Clara, Calif.
The state saving that is associated with the CALL instruction, and similarly with other prior art procedure call instructions, can be disadvantageous.  Often the privileged code 230 comprises a library routine that is solely responsible for making a procedure call to the kernel.  Therefore, there is no need to save much of the architectural state that is normally saved during a system call from the user code 210 to the privileged code 230.  Saving the architectural state during both call instructions is time consuming, thus decreasing the performance of the computer system.  For instance, prior art procedure calls have taken anywhere from approximately 300-1000 clock cycles, depending on the particular application. 
Moreover, often times operating system code is set up to be a flat operating system, such as UNIX.sup.*  or Microsoft WindowsNT.sup.*.  The flat operating system often uses the same attributes in setting up code and data segments.  Thus, there is no need to use a segment descriptor to customize code and data segments of the privileged operating system procedure.  FNT .sup.*  other brands and names are the property of their respective owners
It is therefore desirable to provide for a method of performing a system call wherein a reduced amount of the entire architectural state of the computer is saved.  It is further desirable to provide an instruction that is capable of performing a call to a privileged procedure in a reduced number of clock cycles.  It is yet further desirable to provide for a method of performing a system call to a more privileged procedure without using a descriptor table.  It is also desirable to provide a method for resuming user level code after the called privileged procedure completes.