This application relies for priority upon Korean Patent Application No.  2001-6813, filed on Feb. 12, 2001, the contents of which are herein incorporated by reference in their entirety. 
1.  Field of the Invention
The present invention relates generally to a ferroelectric memory device and a method of forming ferroelectric memory devices.  More specifically, the present invention is directed to a ferroelectric memory device having a ferroelectric capacitor connected to a buried contact structure, as wells as a method of forming that device. 
2.  Description of Related Art
In current data processing systems, a Random Access Memory (RAM) is used to provide high-speed access to data, which is stored in the memory.  Because the semiconductor industry is in continuous need of memory devices having even higher operation speeds, studies have been conducted on the use of a Ferroelectric Random Access Memory (hereinafter referred to as xe2x80x9cFRAMxe2x80x9d).  A ferroelectric layer formed between capacitor electrodes provides a FRAM with non-volatile characteristics.  In other words, the FRAM has two stable polarization states, represented by a hysterisis loop. 
The FRAM has several advantages over other RAM devices.  It has non-volatile characteristics as a flash memory.  It also uses a relatively low operation voltage (approximately 5V), and has excellent operation speed (dozens of nanoseconds).  In order to be usable in modern semiconductor products, however, FRAM devices must be highly integrated. 
Like a dynamic random access memory (DRAM), the FRAM includes a transistor and a capacitor.  The capacitor is a ferroelectric capacitor having a ferroelectric layer.  The ferroelectric capacitor must be electrically connected to the transistor.  Several approaches have been used to provide the electric connection between the capacitor and the transistor.  One approach, disclosed in U.S. Pat.  No.  5,119,154, uses a metal to provide a local interconnection.  Unfortunately, this local interconnection approach is not suitable for high-density FRAMs because the local interconnection is fairly large and the size of the unit memory cells in high-density devices must be minimized. 
Another approach uses a contact plug made of a conductive material to connect a source region of the transistor to the ferroelectric capacitor.  The contact plug connection approach, disclosed in U.S. Pat.  Nos.  5,854,104 and 5,591,663, has been widely used in the production of high-density FRAMs.  FIG.  1 is a schematic cross-sectional view of a conventional ferroelectric memory device constructed using the conventional contact plug connection approach. 
Referring to FIG.  1, a memory cell of a conventional FRAM includes a transistor 104 located on a semiconductor substrate 10.  The transistor 104 has a drain region 106a, a source region 106b, and a gate electrode (not shown).  A first interlayer insulating layer 108 is formed and planarized on the transistor 104 and the substrate 100.  A bit line 112 is then formed on the first interlayer insulating layer 108.  The bit line 112 is electrically connected to the drain region 106a through a predetermined part of the first interlayer insulating layer 108. 
A second interlayer insulating layer 114 is formed on the first interlayer insulating layer 108 and the bit line 112.  A contact hole 118 is formed through a predetermined region of the second and first interlayer insulating layers 114, 108.  A contact plug 119 is formed in the contact hole 118.  A ferroelectric capacitor 126 is formed on the second interlayer insulating layer 114 in electrical contact with the contact plug 119.  A third interlayer insulating layer 128 is then formed on the second interlayer insulating layer 114 and the ferroelectric capacitor 126.  The ferroelectric capacitor 126 is electrically connected to the source region 106b via the contact plug 119 formed through the second and first interlayer insulating layers 114, 108. 
To form the contact plug 119, the first and second interlayer insulating layers 108, 114 must be etched to form the contact hole 118.  Unfortunately, however, the first and second interlayer insulating layers 108, 114 are fairly thick, having thicknesses of about 4000 xc3x85-6000 xc3x85 and 3000 xc3x85-5000 xc3x85, respectively.  Furthermore, as the integration level of the semiconductor devices increases, the diameter of the contact holes decreases while an aspect ratio thereof increases.  As a result, the contact hole 118 must be narrow and deep. 
It is difficult to etch the narrow and deep contact hole 118.  Problems such as a closed contact hole or an over-etched source region can occur.  It is also difficult to fill the narrow and deep contact hole 118 with a conductive material, such as tungsten (W), having improved electric conductivity.  Materials with better deposition characteristics, such as polysilicon, are therefore used to fill the contact hole 118.  Polysilicon, however, is more resistive than tungsten (W) and therefore provides an inferior contact plug. 
Still referring to FIG.  1, after the contact hole 118 is filled with polysilicon, it is then planarized down to a top surface of the interlayer insulating layer 114 to form a contact plug.  Thereafter, a lower electrode 120, a ferroelectric layer 122, and an upper electrode 124 are formed and patterned over the contact plug 119 to form a ferroelectric capacitor 126 that is electrically connected to the contact plug 119. 
A contact area between a polysilicon contact plug 119 and a lower electrode 120 is determined based upon a diameter of the contact hole 118.  Since the diameter of a contact hole decreases as the integration of semiconductor device increases, however, it is difficult to secure a stable electrical contact between a lower electrode and a contact plug in high-density devices.  Securing a stable contact in highly-integrated devices is a significant task. 
In a conventional process of forming a ferroelectric layer 122 of the capacitor 126, a ferroelectric material is deposited and annealed in a high-temperature oxygen ambient.  Through this process, the crystalline state of the ferroelectric material is thereby changed to a perovskite ferroelectric crystalline state.  The high temperature used for this process is around 550xc2x0 C. or higher.  Annealing in an oxygen ambient is important in many steps of the semiconductor integration process.  Unfortunately, this annealing process also causes the formation of a thin insulating layer (e.g., a silicon dioxide (SiO2) layer) at an interface between the polysilicon contact plug and the lower electrode.  This undesired byproduct can make it difficult to secure good contact between the contact plug and the lower electrode and result in a contact failure. 
The conventional polysilicon contact plug approach for providing the connection between the ferroelectric capacitor and the transistor in the FRAM memory device is unable to provide the contact stability necessary to enable the high integration levels desired by the industry.  The industry would be benefited by a ferroelectric memory device that improves the stability of the contact and therefore the integration level of the FRAM.  A corresponding method is also desirable. 
According to preferred aspects of the present invention, a lower electrode of a ferroelectric capacitor is electrically connected to a source region of a transistor through a buried contact structure that can be formed concurrently with a bit line.  The buried contact structure therefore makes it possible to simplify the process steps. 
In addition, an oxidation barrier layer is formed on the buried contact structure to prevent oxygen from contacting the buried contact structure during subsequent annealing in a high-temperature oxygen ambient.  Also, where the buried contact structure is made of tungsten (W), for example, the formation of silicon dioxide (SiO2) thereon is prevented. 
Also, since the diameter of a top of the contact structure is greater than a diameter of a contact hole, the ratio of the contact area to capacitor size is increased over that of the conventional contact plug.  Furthermore, compared with the conventional polysilicon contact plug process, the contact hole of this embodiment has a lower aspect ratio. 
According to one embodiment of the present invention, a method of forming a ferroelectric memory device includes forming a transistor on a semiconductor substrate.  A first interlayer insulating layer is formed on the transistor and the substrate.  A buried contact structure and bit line are then formed on the first interlayer insulating layer.  In this case, the buried contact structure and the bit line are electrically connected to a source and a drain of the transistor, respectively.  A blocking layer to prevent oxygen diffusion is formed on the resulting structure.  The buried contact structure and the bit line are thereby encapsulated by the blocking layer.  A second interlayer insulating layer is formed on the blocking layer.  A ferroelectric capacitor, electrically connected to the buried contact structure, is formed on the second interlayer insulating layer. 
The buried contact structure and the bit line are preferably formed by patterning the first interlayer insulating layer to expose the source and the drain regions form first contact holes.  A conductive layer is then formed in the first contact holes and on the first interlayer insulating layer.  The conductive layer is patterned leaving a portion of the conductive layer in the first contact holes and on a region of the first interlayer insulating layer located on both sides of the contact holes. 
Forming the ferroelectric capacitor preferably includes forming a second contact hole to expose the top surface of the buried contact structure.  A lower capacitor electrode is formed on the second contact hole and the second interlayer insulating layer.  A capacitor dielectric layer is then formed on the lower electrode.  An upper capacitor electrode is formed on the dielectric layer.  The upper electrode, dielectric layer, and lower capacitor electrode are then patterned. 
A diameter of the second contact hole is preferably greater than that of the first contact hole.  The contact structure of the capacitor remaining on the second interlayer insulating layer is also preferably maximized within a design rule.  This results in an increase in a contact area between the lower electrode and the buried contact structure. 
The lower capacitor electrode can be formed by sequentially stacking a first metal, an oxide of the first metal, and platinum on top of each other.  The electrode can alternatively be formed from any one of those three materials alone or any combination thereof.  The upper capacitor electrode is preferably made by stacking a second metal on a second metal oxide.  Or it can be made from either one of those materials alone.  The ferroelectric layer is preferably made of any one or more of the following materials: lead zircon titanate (PZT), lead lanthanum zirconate titanate (PLZT), strontium barium tantalum (SBT), strontium barium tantalum nitride (SBTN), strontium barium tantalum titanate (SBTT), BaTiO3, SrTiO3, Bi4TiO12, and PbTiO3. 
In a preferred embodiment, the lower electrode is made by sequentially stacking iridium (Ir) (having a thickness of about 1500 xc3x85), iridium dioxide (IrO2) (having a thickness of about 500 xc3x85), and platinum (Pt) (having a thickness of about 1500 xc3x85).  The upper electrode is preferably made by sequentially stacking IrO2 (having a thickness of about 300 xc3x85) and Ir (having a thickness of about 1200 xc3x85).  The ferroelectric layer is preferably made of PZT (having a thickness of about 2000 xc3x85). 
Also according to a preferred embodiment, a reaction barrier layer is formed on the ferroelectric capacitor and the second interlayer insulating layer.  A third interlayer insulating layer is formed on the reaction barrier layer.  A first interconnection line is formed on the third interlayer insulating layer.  An inter-level dielectric film is formed on the first interconnection line.  A second interconnection line is formed on the inter-level dielectric film to be electrically connected to the upper capacitor electrode. 
The conductive material for forming the buried contact structure and the bit line is preferably made by stacking a tungsten (W) layer on a titanium/titanium nitride (Ti/TiN) adhesive layer/barrier layer.  A blocking layer is preferably made of SiON, SiN, or aluminum oxide, having a thickness ranging from approximately 100 xc3x85-500 xc3x85, to prevent oxygen diffusion. 
According to another aspect of the invention, a method of forming a ferroelectric capacitor FRAM memory cell includes forming a transistor on a semiconductor substrate.  The transistor includes a source region, a drain region, and a gate electrode.  A first interlayer insulating layer is formed on the transistor and the substrate.  The first interlayer insulating layer is patterned to form first contact holes that expose the drain region and the source region.  A conductive material is then used to form a conductive layer on the interlayer insulating layer and to fill the first contact holes.  The conductive layer is patterned to form a buried contact structure and a bit line that are electrically connected to the source region and the drain region, respectively. 
A blocking layer is formed on the buried contact structure, the bit line, and the first interlayer insulating layer to prevent oxygen diffusion.  The buried contact structure and the bit line are thereby encapsulated.  A second interlayer insulating layer is formed on the blocking layer.  The second interlayer insulating layer and the blocking layer are patterned to expose a top region of the buried contact structure, forming a second contact hole.  A ferroelectric capacitor is formed on the second interlayer insulating layer and is electrically connected to the buried contact structure through the second contact hole.  A diameter of the second contact hole is preferably larger than that of the first contact hole.  A contact area between a lower electrode of the capacitor and the buried contact structure is also preferably increased to improve a contact therebetween. 
The conductive material preferably includes a sequentially stacked adhesive layer/barrier layer of titanium/titanium nitride (Ti/TiN) and a conductive layer of tungsten (W).  An oxygen diffusion blocking layer is preferably made of SiON, SiN, or aluminum oxide.  The blocking layer preferably has a thickness ranging between about 100 xc3x85-500 xc3x85. 
The ferroelectric capacitor is preferably constructed by forming a lower capacitor electrode on the second contact hole and on the second interlayer insulating layer.  A ferroelectric layer is formed on the lower capacitor electrode.  An upper electrode is then formed on the ferroelectric layer.  The upper electrode, the ferroelectric layer, and the lower electrode are then patterned.  In addition, a reaction barrier layer can be formed on the ferroelectric capacitor and the second interlayer insulating layer.  A third interlayer insulating layer is formed on the reaction barrier layer.  A first interconnection line is formed on the third interlayer insulating layer.  An inter-level dielectric film is formed on the first interconnection line.  A second interconnection line is formed on the inter-level dielectric film and is electrically connected to the upper capacitor electrode. 
The lower electrode can be made by sequentially stacking Ir (having a thickness of about 1500 xc3x85), IrO2 (having a thickness of about 500 xc3x85), and platinum (having a thickness of about 1500 xc3x85).  The ferroelectric layer can be made of PZT (having a thickness of about 2000 xc3x85).  The upper electrode can be made by sequentially stacking IrO2 (having a thickness of about 300 xc3x85) and Ir (having a thickness of about 1200 xc3x85). 
According to another aspect of the invention, a transistor of a ferroelectric memory device is formed on a semiconductor substrate.  First and second interlayer insulating layers are then sequentially formed on the substrate.  A buried contact structure and bit line are interposed between the interlayer insulating layers and are respectively electrically connected to source and drain regions of the transistor through first contact holes formed in the first interlayer insulating layer.  A blocking layer is formed on the buried contact structure, the bit line, and the first interlayer insulating layer to prevent oxygen diffusion.  A lower capacitor electrode, formed on the second interlayer insulating layer, is electrically connected to the buried contact structure via a second contact hole formed through the second interlayer insulating layer and the blocking layer.  A ferroelectric capacitor has a lower electrode, a ferroelectric layer, and an upper electrode.  A diameter of the second contact hole is preferably larger than that of the first contact hole to increase a contact area between the lower electrode and the buried contact structure.