The present invention relates generally to semiconductor devices and more particularly to methods for forming localized halo structures in a semiconductor substrate in the fabrication of semiconductor devices. 
Several trends exist presently in the semiconductor device fabrication industry and the electronics industry.  Devices are continually getting smaller, faster and requiring less power.  A reason for these trends is that more personal devices are being fabricated which are relatively small and portable, thereby relying on a battery as its primary supply source.  For example, cellular phones, personal computing devices, and personal sound systems are devices which are in great demand in the consumer market.  In addition to being smaller and more portable, personal devices are requiring more computational power and speed.  In light of all these trends, there is a need in the industry to provide smaller and faster MOS transistors used to provide the core functionality of the integrated circuits used in these semiconductor devices. 
The phenomenal success of the MOS transistor has been partially due to the capability of the MOS transistor to take advantage of the lateral scaling improvements in the technologies.  Lateral scaling results in simultaneous improvements in both the performance and the packing density of the devices.  Although generalized scaling has served well for the last few decades, many of the technology advances that allow the devices to continue improving the performance and the packing density are approaching fundamental physical limitations.  Future device improvements will require the devices to be either optimized for voltage reduction, high performance, or reliability. 
Gate oxide thickness, junction scaling, and well engineering in MOS devices has enabled channel length scaling by improving short channel characteristics.  By changing the doping profile in the channel region, the distribution of the electric field and potential contours can be changed.  The goal is to optimize the channel profile to minimize the off-state leakage while maximizing the linear and saturation drive currents.  Channel doping optimization can improve the circuit gate delay, for example, by about 10% for a given technology.  Super Steep Retrograde Wells (SSRW) and halo implants (or pocket implants) have been used as a means to scale the channel length and increase the transistor drive current without causing an increase in the off-state leakage current. 
Retrograde well engineering changes the 1-D characteristics of the well profile by creating a retrograde profile (the subsurface concentration is higher than the surface concentration) toward the Si/SiO2 surface of a MOS device.  The halo architecture creates a localized 2-D dopant distribution near the S/D regions and extends under the channel.  Halos are generally known for their ability to stop unwanted source/drain leakage conduction, or punchthrough current, and as such, are sometimes referred to as a xe2x80x9cpunchthrough stopperxe2x80x9d. 
The retrograde well profile has been used to improve device performance and is typically created by using a slow diffusing dopant species such as arsenic or antimony for PMOS devices and indium for NMOS devices.  Retrograde wells may only slightly improve saturated drive currents relative to uniform wells, but with today""s deep sub-micron technologies, significantly improve linear drive currents and lead to improved circuit performance. 
Additional benefits and improvements attributable to a theoretically ideal halo with optimal retrograde dopant profiles will be discussed in association with FIG.  1.  FIG.  1 illustrates a 2-D simulation 1 of a true localized and optimal halo profile together with a potential profile for a MOS transistor.  The MOS transistor comprises a gate 2 having a channel length 2a, a gate-oxide 3 having a thickness tox 3a, and a semiconductor substrate 4 with source/drain regions having a depth 4a on either side of a channel region. 
Several graded profiles are illustrated within a channel portion of the semiconductor substrate 4, exhibited by a generally vertically retrograde profile 5a, a generally laterally graded profile toward the center of the channel 5b, and a generally diagonally graded profile toward the source/drain regions 5c.  Implanted dopant concentrations symbolized by solid lines 6-13, range from a high concentration p-type dopant 6, thru a zero dopant concentration 9, to a high concentration n-type dopant 13 to produce the retrograde profiles 5a, 5b, and 5c.  The centers of highest p-type dopant concentration 6, each form the center of the optimal halo. 
In the MOS transistor of FIG.  1, a dopant concentration profile below the surface channel is preferably a vertically retrograde profile 5a toward the substrate surface to provide for high carrier mobility close to the surface under the gate.  Since dopant impurities scatter mobility carriers and degrade linear drive current, ideally the dopant concentration near the substrate 4 surface is low.  At the same time, the vertically retrograde profile 5a provides the highest p-type dopant concentration 6 areas below the surface which advantageously tend to block subsurface currents and further redirect the source/drain current toward the surface. 
Profile 5b is laterally graded toward the center of the channel (and across the channel) from the regions of the highest p-type concentration 6 for maintaining and controlling the Vt roll-off.  Profile 5c is diagonally graded toward the source/drain regions to minimize tunneling current and body-to-source/drain junction capacitance (Cjbw). 
Further, the retrograde profile associated with the lower channel portion would ideally extend under the source/drain regions to minimize the body-to-source/drain junction capacitance (Cjbw), to minimize tunneling current, and to minimize the source-drain resistance Rsd.  The Rsd would be minimized because less compensation of the dose to the highly doped source/drain areas would be required.  A low Rsd allows less potential (voltage) drop across the highly doped source/drain region, thus more potential will drop across the channel 2a.  It is the amount of potential drop across the channel that determines the amount of drive current. 
Together, profiles graded in the above manner would provide halos centered around the high p-type concentration 6 areas, and would tend to direct source/drain current toward the substrate surface while blocking subsurface currents, control Vt roll-off, and minimize Cjbw, tunneling current and Rsd. 
In addition, as device densities and operational speeds continue to increase, reduction of the delay times in the MOS devices used in integrated circuits is desired.  These delays are related to the on-state resistance as well as the junction capacitances of these MOS devices.  In order to reduce these delays and increase MOS device speeds, improved halo profiles as indicated are desired.  Further, increasing device densities also result in a reduced source to drain distance, which requires that halo dopant concentrations increase and move closer to the surface of the substrate.  These changes may result in a disruption to the operation of a MOS transistor.  In these and similar circumstances, a vertically retrograde profile may help to avoid or mitigate some of the problems encountered in the scaling of MOS devices. 
Several prior art methods have been used to create halo-type structures.  One such method is the xe2x80x9csolid source diffusionxe2x80x9d approach, which creates a halo-type structure from a highly doped spacer. 
FIGS.  2A-2D illustrate a prior art method of forming a halo-type structure in a MOS transistor 20 according to the xe2x80x9csolid source diffusionxe2x80x9d method.  Initially in FIG.  2A, the MOS transistor 20 comprises a gate structure 21 formed over a semiconductor substrate 22.  Gate structure 21 comprises a gate-oxide material layer 24 formed over the semiconductor substrate 22, a polysilicon material layer 26 formed over the gate-oxide 24, and an offset spacer 28 comprising a diffusion source material formed surrounding the gate-oxide material layer 24 and the polysilicon material layer 26.  Typically, during the deposition formation of the offset spacer 28, a relatively high concentration dopant may be implanted in-situ with the offset spacer material. 
In FIG.  2B, during a high temperature direct thermal process DT, dopant diffuses 29 from the spacer 28 into areas of the semiconductor substrate 22 underlying the spacer 28 to form a crude halo-type structure 30.  In FIG.  2C, a sidewall spacer 32 is formed over or replaces the offset spacer 28 of the gate structure 21 to provide a larger overall spacer thickness 32xe2x80x2, which will be used to guide a deposition of a source/drain region.  In FIG.  2D, source/drain regions 34 are then formed by implanting into the semiconductor substrate 22 to a predetermined depth 34xe2x80x2 of the MOS transistor 20. 
Although the xe2x80x9csolid source diffusionxe2x80x9d method described provides a halo-type structure, which may block source/drain leakage currents, the high dopant concentration near the surface of the substrate where the dopant originated, also causes a reduction in carrier mobility and a higher Rsd value.  This method is therefore typically unable to produce the desirable retrograde profile toward the surface and toward the source/drain regions.  Further, the sharp definition between the halo and the source/drain regions also may cause tunnel diode current problems.  From a thermal budget standpoint, the relatively high temperature during the direct thermal process step may also be disadvantageous.  The xe2x80x9csolid source diffusionxe2x80x9d method is therefore generally unsuitable for the high device density and high-speed semiconductor applications contemplated. 
The xe2x80x9creplacement gatexe2x80x9d approach is another method to generate a halo-type structure.  The xe2x80x9creplacement gatexe2x80x9d approach (not shown) creates a halo-type structure by first forming a gate structure with a surrounding spacer of oxide material, then masking and removing the gate.  A high-angle implant is then performed thru an exposed gate area of the substrate to implant the area underlying the spacer.  A gate material is subsequently deposited and the gate is redefined with a mask layer and an etch process, and proceeding with the standard deep S/D implant process. 
The xe2x80x9creplacement gatexe2x80x9d approach, however, may also produce a number of negative side-effects.  The doping of all the long channel devices will typically be affected by the implant, which may produce a Vt which is too high or has too much Vt roll-off.  This approach is unable to produce a laterally graded profile across the channel, for further Vt roll-off control.  Finally, the xe2x80x9creplacement gatexe2x80x9d approach is unlikely to achieve a vertically retrograde profile if a channel implant amorphous layer exists, because a very high dose (dopant concentration) is needed for the halo. 
A large-tilt-angle implant can be used to fabricate halo-type structures, usually with the use of a side spacer to protect the gate structure from unwanted dopant contamination.  Prior art FIG.  3, however, illustrates the non-uniform results of a typical quad high-angle implant in a conventional MOS transistor 40, which may be similar in the initial structure to MOS device 20 of FIG.  2a.  
In FIG.  3, the MOS transistor 40 comprises a gate structure 41 formed over a semiconductor substrate 42.  Gate structure 41 comprises a gate-oxide material layer 44 formed over the semiconductor substrate 42, a polysilicon material layer 46 formed over the gate-oxide 44, and an offset spacer 48 comprising an oxide material formed surrounding the gate-oxide material layer 44 and the polysilicon material layer 46. 
A quad high-angle (QHA) implant 54 is performed on the MOS transistor 40, wherein four separate high angle implants are done on the device wafer, each implant performed on the wafer held in a position, then rotationally indexed by 90 degrees.  Although the QHA implant 54 beneficially permits implantation of dopant underlying the gate structure, the gate structure 41, STI 56, and the TAP (photo resist material) 58 structures also shield some areas of the semiconductor substrate 42 from being implanted at one or more of the four implant angles.  Thus, not all areas receive the same uniform dopant concentration. 
For example, FIG.  3 also illustrates four areas of non-uniform dopant concentration 60a-60d at the general depth of interest for the formation of the halo region.  Dopant concentration area 60a underlying the edge of the gate structure 41, for example, receives only one of the four QHA implants 54, for a xc2xc dose.  By contrast, dopant concentration areas 60b and 60c, are in open areas midway between the gate structure 41 and the STI 56/TAP 58 structures, which receive generally all four QHA implants 54, for a full 4/4 dose.  Finally, dopant concentration area 60d, which is only shielded by the STI 56/TAP 58 structures for one of the four QHA implants 54, will likely receive a xc2xe dose. 
Thus, several difficulties are also encounter in the conventional QHA implant 54 formation of a halo of FIG.  3.  Areas underlying the edge of the gate structure 41 are implanted to a relatively low dose level with a non-uniform distribution, while the bulk of the implant is received in other unwanted areas (e.g., in the source/drain regions).  Dopant received in these unwanted areas increases junction capacitance and may cause body leakage, resulting in reduced switching speeds and higher Rsd.  The Rsd is increased for the following reasons: Because the halo implant first enters at the substrate surface, the dopant concentration is also highest at the surface.  In a subsequent step, the source/drain region then receives a dose having the opposite dopant polarity, thus the HDD dose requires compensation, which increases the Rsd. 
Halo implants have been used as an additional means to scale channel length and increase transistor drive current without causing an increase in the off-state leakage current of high-speed, high-density MOS devices.  Several conventional approaches to create a halo-type structure have been discussed such as the xe2x80x9csolid source diffusionxe2x80x9d approach, the more complex xe2x80x9creplacement gatexe2x80x9d approach, and the conventional high-angle implant method.  However, several problems encountered with each of these conventional approaches exist.  Therefore, it is desirable to provide an improved method of forming a localized halo structure to take advantage of the potential performance benefits in a MOS transistor, and in the manufacture and fabrication of such semiconductor devices. 
The following presents a simplified summary in order to provide a basic understanding of one or more aspects of the invention.  This summary is not an extensive overview of the invention, and is neither intended to identify key or critical elements of the invention, nor to delineate the scope thereof.  Rather, the primary purpose of the summary is to present some concepts of the invention in a simplified form as a prelude to the more detailed description that is presented later. 
The present invention relates to methods for forming a localized halo having a retrograde profile in a semiconductor substrate in the fabrication of semiconductor devices.  The invention provides for the formation of the halo structure in an area localized to, and generally underlying the edge of a gate structure.  The dopant concentration profiles produced in association with the halo structure, according to the inventive method, yields beneficially ideal retrograde profiles directed toward the surface and the center of the channel and toward the source/drain regions. 
In an attempt to approximate and implement the formation of retrograde dopant concentration profiles associated with a halo region in a semiconductor substrate of (e.g., a MOS transistor), several aspects of the present invention are provided.  One aspect of the invention provides a method which comprises providing a gate structure overlying a semiconductor substrate, implanting a dopant material at an angle around the gate structure to form a halo structure in a source/drain region of the semiconductor substrate and underlying a portion of the gate structure.  A trench is then formed in the source/drain region of the semiconductor substrate, thereby removing at least a portion of the halo structure in the source/drain region.  A silicon material is then formed in the trench using, for example, epitaxial deposition. 
The trench, in this aspect of the invention, is used to remove unwanted portions of halo dopant from the source/drain regions which do not underlie the gate structure.  Removing the unwanted dopant and replacing it with intrinsic silicon, for example, lowers the body-to-source/drain junction capacitance (Cjbw), lowers the tunneling current, and lowers the source/drain on-state resistance Rsd due to less compensation that is later required in the source/drain regions. 
In one aspect of the invention, the trench is only partially refilled with an undoped silicon material layer (e.g., Si, or SiGe) in a low temperature selective epitaxial deposition (LT-SEpitaxy, or simply LT-SE), then the remainder of the trench is filled with a doped silicon material layer (e.g., Si/SiGe and Boron, or Si/SiGe and As) in a second LT-SE deposition. 
In this way, the depth and concentration of the selectively doped silicon material layer may be controlled, while the underlying intrinsic silicon layer limits source/drain conduction to the substrate surface above the halo.  In addition, this also produces an abrupt HDD profile.  Alternatively, in contrast with the abrupt dopant change indicated above, a controllably graded profile may be accomplished by slowly ramping-up the dopant concentration during the second LT-SE.  Further, by varying the thickness of either layer and controlling the dopant concentration based on, for example, an epitaxial growth rate, a variety of preprogrammed dopant profiles may be obtained. 
In a further aspect of the invention, the semiconductor device proceeds to be processed conventionally comprising thermally processing the device, forming a spacer on lateral sidewalls of the gate structure, and performing a source/drain implant into the silicon material layer and the selectively doped silicon material layer to form a source and drain region having a depth that is less than the trench.  In another aspect of the invention, the thermal annealing may be a rapid thermal anneal (RTA) used to slightly grade the junction and lower the junction capacitance between the doped and undoped silicon layers. 
In another aspect of the invention, the trench is generally filled with an undoped silicon material layer (e.g., Si, or SiGe) using, for example, LT-SE.  An HDD implant is then performed into the intrinsic silicon material layer.  In this way, the depth and dopant concentration of the implant may be controlled with the time and concentration of the implant, while the underlying intrinsic silicon layer limits source/drain conduction to the substrate surface above the halo.  In this method aspect, the dopant implant into the silicon material layer inherently produces a gradation in the dopant concentration without a sharp junction, thereby yielding a lower junction capacitance, if desired. 
Again, in a further aspect of the invention, the semiconductor device may be processed conventionally comprising thermally annealing the device, forming a spacer on lateral sidewalls of the gate structure, and performing a source/drain implant into the silicon material layer and the dopant implanted silicon material layer to form a source and drain region having a depth that is less than the trench. 
The improved formation method and controllable dopant profiles achievable using the invention may be employed to provide accurate and repeatable formation of localized halo structures to take advantage of some of the potential performance benefits associated therewith. 
To the accomplishment of the foregoing and related ends, the following description and annexed drawings set forth in detail certain illustrative aspects and implementations of the invention.  These are indicative of but a few of the various ways in which the principles of the invention may be employed.  Other aspects, advantages and novel features of the invention will become apparent from the following detailed description of the invention when considered in conjunction with the drawings.