Repository: coala/coala

Issue:
Add language definition for Verilog
https://en.wikipedia.org/wiki/Verilog

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Discussion:

Resolving patch:
diff --git a/coalib/bearlib/languages/__init__.py b/coalib/bearlib/languages/__init__.py
--- a/coalib/bearlib/languages/__init__.py
+++ b/coalib/bearlib/languages/__init__.py
@@ -42,6 +42,7 @@
 from .definitions.TinyBasic import TinyBasic
 from .definitions.TypeScript import TypeScript
 from .definitions.Vala import Vala
+from .definitions.Verilog import Verilog
 from .definitions.VisualBasic import VisualBasic
 from .definitions.XML import XML
 from .definitions.ZShell import ZShell
diff --git a/coalib/bearlib/languages/definitions/Verilog.py b/coalib/bearlib/languages/definitions/Verilog.py
new file mode 100644
--- /dev/null
+++ b/coalib/bearlib/languages/definitions/Verilog.py
@@ -0,0 +1,31 @@
+from coalib.bearlib.languages.Language import Language
+
+
+@Language
+class Verilog:
+    aliases = 'verilog',
+    extensions = '.v',
+    comment_delimiters = '//',
+    multiline_comment_delimiters = {'/*': '*/'}
+    string_delimiters = {'"': '"'}
+    encapsulators = {'(': ')', '[': ']', '{': '}'}
+    string_delimiter_escape = {'"': '\\"', "'": "\\'"}
+    line_continuation = '\\'
+    keywords = [
+        'always', 'and', 'assign', 'attribute', 'begin', 'buf', 'bufif0',
+        'bufif1', 'case', 'casex', 'casez', 'cmos', 'deassign', 'default',
+        'defparam', 'disable', 'edge', 'else', 'end', 'endattribute',
+        'endcase', 'endfunction', 'endmodule', 'endprimitive', 'endspecify',
+        'endtable', 'endtask', 'event', 'for', 'force', 'forever', 'fork',
+        'function', 'highz0', 'highz1', 'if', 'ifnone', 'initial', 'inout',
+        'input', 'integer', 'join', 'medium', 'module', 'large', 'macromodule',
+        'nand', 'negedge', 'nmos', 'nor', 'not', 'notif0', 'notif1', 'or',
+        'output', 'parameter', 'pmos', 'posedge', 'primitive', 'pull0',
+        'pull1', 'pulldown', 'pullup', 'rcmos', 'real', 'realtime', 'reg',
+        'release', 'repeat', 'rnmos', 'rpmos', 'rtran', 'rtranif0', 'rtranif1',
+        'scalared', 'signed', 'small', 'specify', 'specparam', 'strength',
+        'strong0', 'strong1', 'supply0', 'supply1', 'table', 'task', 'time',
+        'tran', 'tranif0', 'tranif1', 'tri', 'tri0', 'tri1', 'triand', 'trior',
+        'trireg', 'unsigned', 'vectored', 'wait', 'wand', 'weak0', 'weak1',
+        'while', 'wire', 'wor', 'xnor', 'xor',
+        ]


Test patch:
diff --git a/tests/TestUtilities.py b/tests/TestUtilities.py
--- a/tests/TestUtilities.py
+++ b/tests/TestUtilities.py
@@ -69,6 +69,7 @@
     'TinyBasic 1.0, 2.0',
     'TypeScript',
     'Vala',
+    'Verilog',
     'VisualBasic',
     'm4',
     'ZShell',