Repository: Qiskit/qiskit

Issue:
matplotlib visualizer should not use transpiler(format='json')
We are going to remove the option `format='json'` from the transpiler (see #1129). For that, we need to move the visualizers into the function `get_instractions` introduced in PR #1187.

The file `qiskit/tools/visualization//_matplotlib.py` calls `transpiler.transpile_dag(dag_circuit, basis_gates=self._basis, format='json')`. This needs to be removed in favor of `_utils.get_instructions`.


Discussion:

Resolving patch:
diff --git a/qiskit/tools/visualization/_matplotlib.py b/qiskit/tools/visualization/_matplotlib.py
--- a/qiskit/tools/visualization/_matplotlib.py
+++ b/qiskit/tools/visualization/_matplotlib.py
@@ -25,10 +25,9 @@
 except ImportError:
     HAS_MATPLOTLIB = False
 
-from qiskit import dagcircuit
-from qiskit import transpiler
 from qiskit.tools.visualization import _error
 from qiskit.tools.visualization import _qcstyle
+from qiskit.tools.visualization import _utils
 
 
 logger = logging.getLogger(__name__)
@@ -132,30 +131,19 @@ def __init__(self,
                             labelleft=False, labelright=False)
 
     def parse_circuit(self, circuit):
-        dag_circuit = dagcircuit.DAGCircuit.fromQuantumCircuit(
-            circuit, expand_gates=False)
-        basis = ("id,u0,u1,u2,u3,x,y,z,h,s,sdg,t,tdg,rx,ry,rz,"
-                 "cx,cy,cz,ch,crz,cu1,cu3,swap,ccx,cswap")
-        self._ast = transpiler.transpile_dag(dag_circuit,
-                                             basis_gates=basis,
-                                             format='json')
-        self._registers()
-        self._ops = self._ast['instructions']
-
-    def _registers(self):
+        qregs, cregs, ops = _utils._get_instructions(
+            circuit, reversebits=self.reverse_bits)
+        self._registers(cregs, qregs)
+        self._ops = ops
+
+    def _registers(self, creg, qreg):
         # NOTE: formats of clbit and qubit are different!
-        header = self._ast['header']
         self._creg = []
-        for e in header['clbit_labels']:
-            for i in range(e[1]):
-                self._creg.append(Register(name=e[0], index=i))
-        if len(self._creg) != header['number_of_clbits']:
-            raise _error.VisualizationError('internal error')
+        for e in creg:
+            self._creg.append(Register(name=e[0], index=e[1]))
         self._qreg = []
-        for e in header['qubit_labels']:
+        for e in qreg:
             self._qreg.append(Register(name=e[0], index=e[1]))
-        if len(self._qreg) != header['number_of_qubits']:
-            raise _error.VisualizationError('internal error')
 
     @property
     def ast(self):
@@ -415,22 +403,6 @@ def _draw_regs(self):
                     }
                 self._cond['n_lines'] += 1
                 idx += 1
-        # reverse bit order
-        if self.reverse_bits:
-            self._reverse_bits(self._qreg_dict)
-            self._reverse_bits(self._creg_dict)
-
-    def _reverse_bits(self, target_dict):
-        coord = {}
-        # grouping
-        for dict_ in target_dict.values():
-            if dict_['group'] not in coord:
-                coord[dict_['group']] = [dict_['y']]
-            else:
-                coord[dict_['group']].insert(0, dict_['y'])
-        # reverse bit order
-        for key in target_dict.keys():
-            target_dict[key]['y'] = coord[target_dict[key]['group']].pop(0)
 
     def _draw_regs_sub(self, n_fold, feedline_l=False, feedline_r=False):
         # quantum register
@@ -520,13 +492,25 @@ def _draw_ops(self, verbose=False):
                 _iswide = False
                 gw = 1
             # get qreg index
-            if 'qubits' in op.keys():
-                q_idxs = op['qubits']
+            if 'qargs' in op.keys():
+                q_idxs = []
+                for qarg in op['qargs']:
+                    for index, reg in self._qreg_dict.items():
+                        if (reg['group'] == qarg[0] and
+                                reg['index'] == qarg[1]):
+                            q_idxs.append(index)
+                            break
             else:
                 q_idxs = []
             # get creg index
-            if 'clbits' in op.keys():
-                c_idxs = op['clbits']
+            if 'cargs' in op.keys():
+                c_idxs = []
+                for carg in op['cargs']:
+                    for index, reg in self._creg_dict.items():
+                        if (reg['group'] == carg[0] and
+                                reg['index'] == carg[1]):
+                            c_idxs.append(index)
+                            break
             else:
                 c_idxs = []
             # find empty space to place gate


Test patch: