Repository: Qiskit/qiskit

Issue:
`circuit.draw(idle_wires=False)` should ignore barrier
There is an option to the circuit drawers for not plotting qubits that are idle - this is useful for visualizing small circuits that happen to be embedded on large devices. However a barrier on a qubit is seen as a sign of non-idleness. I think barriers should just be ignored as they are not operations. And barriers on all device qubits gets inserted by the transpiler, so it makes this option useless until the drawer can ignore it.


Discussion:
Is it ok if I try this issue? 
Yes thank you :)

> On May 18, 2020, at 12:02 AM, metacubestormerxii12 <notifications@github.com> wrote:
> 
> Is it ok if I try this issue?
> 
> —
> You are receiving this because you were mentioned.
> Reply to this email directly, view it on GitHub, or unsubscribe.

By the way, could you show an example of what you mean by this? I think I have replicated this circumstance but I'm not 100% sure
Ok I think I understand now actually. 

Resolving patch:
diff --git a/qiskit/dagcircuit/dagcircuit.py b/qiskit/dagcircuit/dagcircuit.py
--- a/qiskit/dagcircuit/dagcircuit.py
+++ b/qiskit/dagcircuit/dagcircuit.py
@@ -609,15 +609,21 @@ def compose(self, other, edge_map=None, qubits=None, clbits=None, front=False, i
         else:
             return None
 
-    def idle_wires(self):
+    def idle_wires(self, ignore=None):
         """Return idle wires.
 
+        Args:
+            ignore (list(str)): List of node names to ignore. Default: []
+
         Yields:
             Bit: Bit in idle wire.
         """
+        if ignore is None:
+            ignore = []
         for wire in self._wires:
-            nodes = self.nodes_on_wire(wire, only_ops=False)
-            if len(list(nodes)) == 2:
+            nodes = [node for node in self.nodes_on_wire(wire, only_ops=False)
+                     if node.name not in ignore]
+            if len(nodes) == 2:
                 yield wire
 
     def size(self):
diff --git a/qiskit/visualization/text.py b/qiskit/visualization/text.py
--- a/qiskit/visualization/text.py
+++ b/qiskit/visualization/text.py
@@ -955,8 +955,8 @@ def add_connected_gate(instruction, gates, layer, current_cons):
                 return layer, current_cons, connection_label
 
             for qubit in instruction.qargs:
-                layer.set_qubit(qubit, Barrier())
-
+                if qubit in self.qregs:
+                    layer.set_qubit(qubit, Barrier())
         elif isinstance(instruction.op, SwapGate):
             # swap
             gates = [Ex(conditional=conditional) for _ in range(len(instruction.qargs))]
diff --git a/qiskit/visualization/utils.py b/qiskit/visualization/utils.py
--- a/qiskit/visualization/utils.py
+++ b/qiskit/visualization/utils.py
@@ -140,7 +140,7 @@ def _get_layered_instructions(circuit, reverse_bits=False,
         cregs.reverse()
 
     if not idle_wires:
-        for wire in dag.idle_wires():
+        for wire in dag.idle_wires(ignore=['barrier']):
             if wire in qregs:
                 qregs.remove(wire)
             if wire in cregs:


Test patch:
diff --git a/test/python/dagcircuit/test_dagcircuit.py b/test/python/dagcircuit/test_dagcircuit.py
--- a/test/python/dagcircuit/test_dagcircuit.py
+++ b/test/python/dagcircuit/test_dagcircuit.py
@@ -1062,6 +1062,13 @@ def test_dag_depth_empty(self):
         dag = circuit_to_dag(qc)
         self.assertEqual(dag.depth(), 0)
 
+    def test_dag_idle_wires(self):
+        """Test dag idle_wires."""
+        wires = list(self.dag.idle_wires())
+        self.assertEqual(len(wires), 0)
+        wires = list(self.dag.idle_wires(['u2', 'cx']))
+        self.assertEqual(len(wires), 1)
+
     def test_dag_depth1(self):
         """Test DAG depth #1
         """
diff --git a/test/python/visualization/test_circuit_text_drawer.py b/test/python/visualization/test_circuit_text_drawer.py
--- a/test/python/visualization/test_circuit_text_drawer.py
+++ b/test/python/visualization/test_circuit_text_drawer.py
@@ -1825,6 +1825,18 @@ def test_text_empty_circuit(self):
         circuit = QuantumCircuit()
         self.assertEqual(str(_text_circuit_drawer(circuit, idle_wires=False)), expected)
 
+    def test_text_barrier(self):
+        """idle_wires should ignore barrier
+        See https://github.com/Qiskit/qiskit-terra/issues/4391"""
+        expected = '\n'.join(["         ┌───┐ ░ ",
+                              "qr_1: |0>┤ H ├─░─",
+                              "         └───┘ ░ "])
+        qr = QuantumRegister(3, 'qr')
+        circuit = QuantumCircuit(qr)
+        circuit.h(qr[1])
+        circuit.barrier(qr[1], qr[2])
+        self.assertEqual(str(_text_circuit_drawer(circuit, idle_wires=False)), expected)
+
 
 class TestTextNonRational(QiskitTestCase):
     """ non-rational numbers are correctly represented """