Theorem: BVExpr.bitblast.blastAdd.go_eq_eval_getLsb
Proof state before:
case inr.hcin
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin : aig.Ref
s : aig.RefStream curr
lhs rhs : aig.RefStream w
assign : α → Bool
lhsExpr rhsExpr : BitVec w
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := lhs.getRef idx hidx }, assign⟧ = lhsExpr.getLsb idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := rhs.getRef idx hidx }, assign⟧ = rhsExpr.getLsb idx
hcin : ⟦{ aig := aig, ref := cin }, assign⟧ = BitVec.carry curr lhsExpr rhsExpr false
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry α w
hlt✝ : curr < w
hgo :
  go (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).aig (curr + 1) ⋯
      (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).cout
      ((s.cast ⋯).pushRef
        (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).out)
      (lhs.cast ⋯) (rhs.cast ⋯) =
    res
hlt : curr < idx
⊢ (xor ⟦{ aig := aig, ref := { gate := (lhs.getRef curr hlt✝).gate, hgate := ?inr.hcin } }, assign⟧
          ⟦{ aig := (mkFullAdderOut aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).aig,
              ref := { gate := (rhs.getRef curr hlt✝).gate, hgate := ⋯ } },
            assign⟧ &&
        ⟦{ aig := (mkFullAdderOut aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).aig,
            ref := { gate := cin.gate, hgate := ⋯ } },
          assign⟧ ||
      ⟦{ aig := aig, ref := { gate := (lhs.getRef curr hlt✝).gate, hgate := ?inr.hcin } }, assign⟧ &&
        ⟦{ aig := (mkFullAdderOut aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).aig,
            ref := { gate := (rhs.getRef curr hlt✝).gate, hgate := ⋯ } },
          assign⟧) =
    (lhsExpr.getLsb curr).atLeastTwo (rhsExpr.getLsb curr) (BitVec.carry curr lhsExpr rhsExpr false)

case inr.hcin
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin : aig.Ref
s : aig.RefStream curr
lhs rhs : aig.RefStream w
assign : α → Bool
lhsExpr rhsExpr : BitVec w
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := lhs.getRef idx hidx }, assign⟧ = lhsExpr.getLsb idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := rhs.getRef idx hidx }, assign⟧ = rhsExpr.getLsb idx
hcin : ⟦{ aig := aig, ref := cin }, assign⟧ = BitVec.carry curr lhsExpr rhsExpr false
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry α w
hlt✝ : curr < w
hgo :
  go (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).aig (curr + 1) ⋯
      (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).cout
      ((s.cast ⋯).pushRef
        (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).out)
      (lhs.cast ⋯) (rhs.cast ⋯) =
    res
hlt : curr < idx
⊢ (lhs.getRef curr hlt✝).gate < aig.decls.size
Tactic:
rw [AIG.LawfulOperator.denote_mem_prefix (f := mkFullAdderOut)]
Proof state after:
case inr.hcin
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin : aig.Ref
s : aig.RefStream curr
lhs rhs : aig.RefStream w
assign : α → Bool
lhsExpr rhsExpr : BitVec w
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := lhs.getRef idx hidx }, assign⟧ = lhsExpr.getLsb idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := rhs.getRef idx hidx }, assign⟧ = rhsExpr.getLsb idx
hcin : ⟦{ aig := aig, ref := cin }, assign⟧ = BitVec.carry curr lhsExpr rhsExpr false
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry α w
hlt✝ : curr < w
hgo :
  go (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).aig (curr + 1) ⋯
      (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).cout
      ((s.cast ⋯).pushRef
        (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).out)
      (lhs.cast ⋯) (rhs.cast ⋯) =
    res
hlt : curr < idx
⊢ (xor ⟦{ aig := aig, ref := { gate := (lhs.getRef curr hlt✝).gate, hgate := ?inr.hcin } }, assign⟧
          ⟦{ aig := aig, ref := { gate := (rhs.getRef curr hlt✝).gate, hgate := ?inr.hcin } }, assign⟧ &&
        ⟦{ aig := (mkFullAdderOut aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).aig,
            ref := { gate := cin.gate, hgate := ⋯ } },
          assign⟧ ||
      ⟦{ aig := aig, ref := { gate := (lhs.getRef curr hlt✝).gate, hgate := ?inr.hcin } }, assign⟧ &&
        ⟦{ aig := aig, ref := { gate := (rhs.getRef curr hlt✝).gate, hgate := ?inr.hcin } }, assign⟧) =
    (lhsExpr.getLsb curr).atLeastTwo (rhsExpr.getLsb curr) (BitVec.carry curr lhsExpr rhsExpr false)

case inr.hcin
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin : aig.Ref
s : aig.RefStream curr
lhs rhs : aig.RefStream w
assign : α → Bool
lhsExpr rhsExpr : BitVec w
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := lhs.getRef idx hidx }, assign⟧ = lhsExpr.getLsb idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := rhs.getRef idx hidx }, assign⟧ = rhsExpr.getLsb idx
hcin : ⟦{ aig := aig, ref := cin }, assign⟧ = BitVec.carry curr lhsExpr rhsExpr false
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry α w
hlt✝ : curr < w
hgo :
  go (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).aig (curr + 1) ⋯
      (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).cout
      ((s.cast ⋯).pushRef
        (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).out)
      (lhs.cast ⋯) (rhs.cast ⋯) =
    res
hlt : curr < idx
⊢ (rhs.getRef curr hlt✝).gate < aig.decls.size

case inr.hcin
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin : aig.Ref
s : aig.RefStream curr
lhs rhs : aig.RefStream w
assign : α → Bool
lhsExpr rhsExpr : BitVec w
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := lhs.getRef idx hidx }, assign⟧ = lhsExpr.getLsb idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := rhs.getRef idx hidx }, assign⟧ = rhsExpr.getLsb idx
hcin : ⟦{ aig := aig, ref := cin }, assign⟧ = BitVec.carry curr lhsExpr rhsExpr false
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry α w
hlt✝ : curr < w
hgo :
  go (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).aig (curr + 1) ⋯
      (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).cout
      ((s.cast ⋯).pushRef
        (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).out)
      (lhs.cast ⋯) (rhs.cast ⋯) =
    res
hlt : curr < idx
⊢ (lhs.getRef curr hlt✝).gate < aig.decls.size

case inr.hcin
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin : aig.Ref
s : aig.RefStream curr
lhs rhs : aig.RefStream w
assign : α → Bool
lhsExpr rhsExpr : BitVec w
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := lhs.getRef idx hidx }, assign⟧ = lhsExpr.getLsb idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := rhs.getRef idx hidx }, assign⟧ = rhsExpr.getLsb idx
hcin : ⟦{ aig := aig, ref := cin }, assign⟧ = BitVec.carry curr lhsExpr rhsExpr false
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry α w
hlt✝ : curr < w
hgo :
  go (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).aig (curr + 1) ⋯
      (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).cout
      ((s.cast ⋯).pushRef
        (mkFullAdder aig { lhs := lhs.getRef curr hlt✝, rhs := rhs.getRef curr hlt✝, cin := cin }).out)
      (lhs.cast ⋯) (rhs.cast ⋯) =
    res
hlt : curr < idx
⊢ (lhs.getRef curr hlt✝).gate < aig.decls.size