Theorem: BVExpr.bitblast.blastAdd.go_eq_eval_getLsb
Proof state before:
case inl
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin : aig.Ref
s : aig.RefStream curr
lhs rhs : aig.RefStream w
assign : α → Bool
lhsExpr rhsExpr : BitVec w
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := lhs.getRef idx hidx }, assign⟧ = lhsExpr.getLsb idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := rhs.getRef idx hidx }, assign⟧ = rhsExpr.getLsb idx
hcin : ⟦{ aig := aig, ref := cin }, assign⟧ = BitVec.carry curr lhsExpr rhsExpr false
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry α w
hlt : curr < w
hgo :
  go (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).aig (curr + 1) ⋯
      (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).cout
      ((s.cast ⋯).pushRef (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).out)
      (lhs.cast ⋯) (rhs.cast ⋯) =
    res
heq : curr = idx
⊢ ⟦{
        aig :=
          (go (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).aig (curr + 1) ⋯
              (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).cout
              ((s.cast ⋯).pushRef
                (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).out)
              (lhs.cast ⋯) (rhs.cast ⋯)).aig,
        ref := (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).out.cast ⋯ },
      assign⟧ =
    ⟦{ aig := aig, ref := lhs.getRef idx hidx1 }, assign⟧.xor
      (⟦{ aig := aig, ref := rhs.getRef idx hidx1 }, assign⟧.xor (BitVec.carry idx lhsExpr rhsExpr false))
Tactic:
simp only [← heq]
Proof state after:
case inl
α : Type
inst✝² : BEq α
inst✝¹ : Hashable α
inst✝ : DecidableEq α
w : Nat
aig : AIG α
curr : Nat
hcurr : curr ≤ w
cin : aig.Ref
s : aig.RefStream curr
lhs rhs : aig.RefStream w
assign : α → Bool
lhsExpr rhsExpr : BitVec w
hleft : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := lhs.getRef idx hidx }, assign⟧ = lhsExpr.getLsb idx
hright : ∀ (idx : Nat) (hidx : idx < w), ⟦{ aig := aig, ref := rhs.getRef idx hidx }, assign⟧ = rhsExpr.getLsb idx
hcin : ⟦{ aig := aig, ref := cin }, assign⟧ = BitVec.carry curr lhsExpr rhsExpr false
idx : Nat
hidx1 : idx < w
hidx2 : curr ≤ idx
res : RefStreamEntry α w
hlt : curr < w
hgo :
  go (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).aig (curr + 1) ⋯
      (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).cout
      ((s.cast ⋯).pushRef (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).out)
      (lhs.cast ⋯) (rhs.cast ⋯) =
    res
heq : curr = idx
⊢ ⟦{
        aig :=
          (go (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).aig (curr + 1) ⋯
              (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).cout
              ((s.cast ⋯).pushRef
                (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).out)
              (lhs.cast ⋯) (rhs.cast ⋯)).aig,
        ref := (mkFullAdder aig { lhs := lhs.getRef curr hlt, rhs := rhs.getRef curr hlt, cin := cin }).out.cast ⋯ },
      assign⟧ =
    ⟦{ aig := aig, ref := lhs.getRef curr ⋯ }, assign⟧.xor
      (⟦{ aig := aig, ref := rhs.getRef curr ⋯ }, assign⟧.xor (BitVec.carry curr lhsExpr rhsExpr false))