--- initial
+++ final
@@ -1,72 +1,72 @@
 void __init MMU_init_hw(void) {
   unsigned int hmask, mb, mb2;
   unsigned int n_hpteg, lg_n_hpteg;
   extern unsigned int hash_page_patch_A[];
   extern unsigned int hash_page_patch_B[], hash_page_patch_C[];
   extern unsigned int hash_page[];
   extern unsigned int flush_hash_patch_A[], flush_hash_patch_B[];
   if (!mmu_has_feature(MMU_FTR_HPTE_TABLE)) {
     /*
      * Put a blr (procedure return) instruction at the
      * start of hash_page, since we can still get DSI
      * exceptions on a 603.
      */
     hash_page[0] = 0x4e800020;
     flush_icache_range((unsigned long)&hash_page[0], (unsigned long)&hash_page[1]);
     return;
   }
   if (ppc_md.progress) ppc_md.progress("hash:enter", 0x105);
 #define LG_HPTEG_SIZE 6 /* 64 bytes per HPTEG */
 #define SDR1_LOW_BITS ((n_hpteg - 1) >> 10)
 #define MIN_N_HPTEG 1024 /* min 64kB hash table */
   /*
    * Allow 1 HPTE (1/8 HPTEG) for each page of memory.
    * This is less than the recommended amount, but then
    * Linux ain't AIX.
    */
   n_hpteg = total_memory / (PAGE_SIZE * 8);
   if (n_hpteg < MIN_N_HPTEG) n_hpteg = MIN_N_HPTEG;
   lg_n_hpteg = __ilog2(n_hpteg);
   if (n_hpteg & (n_hpteg - 1)) {
     ++lg_n_hpteg; /* round up if not power of 2 */
     n_hpteg = 1 << lg_n_hpteg;
   }
   Hash_size = n_hpteg << LG_HPTEG_SIZE;
   /*
    * Find some memory for the hash table.
    */
   if (ppc_md.progress) ppc_md.progress("hash:find piece", 0x322);
-  Hash = __va(memblock_alloc(Hash_size, Hash_size));
+  Hash = __va(memblock_phys_alloc(Hash_size, Hash_size));
   memset(Hash, 0, Hash_size);
   _SDR1 = __pa(Hash) | SDR1_LOW_BITS;
   Hash_end = (struct hash_pte *)((unsigned long)Hash + Hash_size);
   printk("Total memory = %lldMB; using %ldkB for hash table (at %p)\n", (unsigned long long)(total_memory >> 20), Hash_size >> 10, Hash);
   /*
    * Patch up the instructions in hashtable.S:create_hpte
    */
   if (ppc_md.progress) ppc_md.progress("hash:patch", 0x345);
   Hash_mask = n_hpteg - 1;
   hmask = Hash_mask >> (16 - LG_HPTEG_SIZE);
   mb2 = mb = 32 - LG_HPTEG_SIZE - lg_n_hpteg;
   if (lg_n_hpteg > 16) mb2 = 16 - LG_HPTEG_SIZE;
   hash_page_patch_A[0] = (hash_page_patch_A[0] & ~0xffff) | ((unsigned int)(Hash) >> 16);
   hash_page_patch_A[1] = (hash_page_patch_A[1] & ~0x7c0) | (mb << 6);
   hash_page_patch_A[2] = (hash_page_patch_A[2] & ~0x7c0) | (mb2 << 6);
   hash_page_patch_B[0] = (hash_page_patch_B[0] & ~0xffff) | hmask;
   hash_page_patch_C[0] = (hash_page_patch_C[0] & ~0xffff) | hmask;
   /*
    * Ensure that the locations we've patched have been written
    * out from the data cache and invalidated in the instruction
    * cache, on those machines with split caches.
    */
   flush_icache_range((unsigned long)&hash_page_patch_A[0], (unsigned long)&hash_page_patch_C[1]);
   /*
    * Patch up the instructions in hashtable.S:flush_hash_page
    */
   flush_hash_patch_A[0] = (flush_hash_patch_A[0] & ~0xffff) | ((unsigned int)(Hash) >> 16);
   flush_hash_patch_A[1] = (flush_hash_patch_A[1] & ~0x7c0) | (mb << 6);
   flush_hash_patch_A[2] = (flush_hash_patch_A[2] & ~0x7c0) | (mb2 << 6);
   flush_hash_patch_B[0] = (flush_hash_patch_B[0] & ~0xffff) | hmask;
   flush_icache_range((unsigned long)&flush_hash_patch_A[0], (unsigned long)&flush_hash_patch_B[1]);
   if (ppc_md.progress) ppc_md.progress("hash:done", 0x205);
 }<sep>@@
expression e1, e2, e3;
@@
(
- memblock_alloc(e1, e2)
+ memblock_phys_alloc(e1, e2)
|
- memblock_alloc_nid(e1, e2, e3)
+ memblock_phys_alloc_nid(e1, e2, e3)
|
- memblock_alloc_try_nid(e1, e2, e3)
+ memblock_phys_alloc_try_nid(e1, e2, e3)
)