imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,21 +1,21 @@
 int smu7_disable_power_containment(struct pp_hwmgr *hwmgr) {
   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   int result = 0;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment) && data->power_containment_features) {
+  if (PP_CAP(PHM_PlatformCaps_PowerContainment) && data->power_containment_features) {
     int smc_result;
     if (data->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) {
       smc_result = smum_send_msg_to_smc(hwmgr->smumgr, (uint16_t)(PPSMC_MSG_TDCLimitDisable));
       PP_ASSERT_WITH_CODE((smc_result == 0), "Failed to disable TDCLimit in SMC.", result = smc_result);
     }
     if (data->power_containment_features & POWERCONTAINMENT_FEATURE_DTE) {
       smc_result = smum_send_msg_to_smc(hwmgr->smumgr, (uint16_t)(PPSMC_MSG_DisableDTE));
       PP_ASSERT_WITH_CODE((smc_result == 0), "Failed to disable DTE in SMC.", result = smc_result);
     }
     if (data->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) {
       smc_result = smum_send_msg_to_smc(hwmgr->smumgr, (uint16_t)(PPSMC_MSG_PkgPwrLimitDisable));
       PP_ASSERT_WITH_CODE((smc_result == 0), "Failed to disable PkgPwrTracking in SMC.", result = smc_result);
     }
     data->power_containment_features = 0;
   }
   return result;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,10 +1,10 @@
 int smu7_disable_smc_cac(struct pp_hwmgr *hwmgr) {
   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   int result = 0;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CAC) && data->cac_enabled) {
+  if (PP_CAP(PHM_PlatformCaps_CAC) && data->cac_enabled) {
     int smc_result = smum_send_msg_to_smc(hwmgr->smumgr, (uint16_t)(PPSMC_MSG_DisableCac));
     PP_ASSERT_WITH_CODE((smc_result == 0), "Failed to disable CAC in SMC.", result = -1);
     data->cac_enabled = false;
   }
   return result;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,41 +1,41 @@
 static int smu7_enable_didt(struct pp_hwmgr *hwmgr, const bool enable) {
   uint32_t en = enable ? 1 : 0;
   uint32_t block_en = 0;
   int32_t result = 0;
   uint32_t didt_block;
   uint32_t data;
   if (hwmgr->chip_id == CHIP_POLARIS11)
     didt_block = Polaris11_DIDTBlock_Info;
   else
     didt_block = DIDTBlock_Info;
-  block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) ? en : 0;
+  block_en = PP_CAP(PHM_PlatformCaps_SQRamping) ? en : 0;
   data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0);
   data &= ~DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK;
   data |= ((block_en << DIDT_SQ_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_SQ_CTRL0__DIDT_CTRL_EN_MASK);
   cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_CTRL0, data);
   didt_block &= ~SQ_Enable_MASK;
   didt_block |= block_en << SQ_Enable_SHIFT;
-  block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) ? en : 0;
+  block_en = PP_CAP(PHM_PlatformCaps_DBRamping) ? en : 0;
   data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0);
   data &= ~DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK;
   data |= ((block_en << DIDT_DB_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_DB_CTRL0__DIDT_CTRL_EN_MASK);
   cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_CTRL0, data);
   didt_block &= ~DB_Enable_MASK;
   didt_block |= block_en << DB_Enable_SHIFT;
-  block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) ? en : 0;
+  block_en = PP_CAP(PHM_PlatformCaps_TDRamping) ? en : 0;
   data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0);
   data &= ~DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK;
   data |= ((block_en << DIDT_TD_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TD_CTRL0__DIDT_CTRL_EN_MASK);
   cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_CTRL0, data);
   didt_block &= ~TD_Enable_MASK;
   didt_block |= block_en << TD_Enable_SHIFT;
-  block_en = phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping) ? en : 0;
+  block_en = PP_CAP(PHM_PlatformCaps_TCPRamping) ? en : 0;
   data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0);
   data &= ~DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK;
   data |= ((block_en << DIDT_TCP_CTRL0__DIDT_CTRL_EN__SHIFT) & DIDT_TCP_CTRL0__DIDT_CTRL_EN_MASK);
   cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_CTRL0, data);
   didt_block &= ~TCP_Enable_MASK;
   didt_block |= block_en << TCP_Enable_SHIFT;
   if (enable) result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_Didt_Block_Function, didt_block);
   return result;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,29 +1,29 @@
 int smu7_enable_power_containment(struct pp_hwmgr *hwmgr) {
   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
   int smc_result;
   int result = 0;
   struct phm_cac_tdp_table *cac_table;
   data->power_containment_features = 0;
   if (hwmgr->pp_table_version == PP_TABLE_V1)
     cac_table = table_info->cac_dtp_table;
   else
     cac_table = hwmgr->dyn_state.cac_dtp_table;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
+  if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
     if (data->enable_tdc_limit_feature) {
       smc_result = smum_send_msg_to_smc(hwmgr->smumgr, (uint16_t)(PPSMC_MSG_TDCLimitEnable));
       PP_ASSERT_WITH_CODE((0 == smc_result), "Failed to enable TDCLimit in SMC.", result = -1;);
       if (0 == smc_result) data->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit;
     }
     if (data->enable_pkg_pwr_tracking_feature) {
       smc_result = smum_send_msg_to_smc(hwmgr->smumgr, (uint16_t)(PPSMC_MSG_PkgPwrLimitEnable));
       PP_ASSERT_WITH_CODE((0 == smc_result), "Failed to enable PkgPwrTracking in SMC.", result = -1;);
       if (0 == smc_result) {
         uint32_t default_limit = (uint32_t)(cac_table->usMaximumPowerDeliveryLimit * 256);
         data->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit;
         if (smu7_set_power_limit(hwmgr, default_limit)) pr_err("Failed to set Default Power Limit in SMC!");
       }
     }
   }
   return result;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,11 +1,11 @@
 int smu7_enable_smc_cac(struct pp_hwmgr *hwmgr) {
   struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
   int result = 0;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_CAC)) {
+  if (PP_CAP(PHM_PlatformCaps_CAC)) {
     int smc_result;
     smc_result = smum_send_msg_to_smc(hwmgr->smumgr, (uint16_t)(PPSMC_MSG_EnableCac));
     PP_ASSERT_WITH_CODE((0 == smc_result), "Failed to enable CAC in SMC.", result = -1);
     data->cac_enabled = (0 == smc_result) ? true : false;
   }
   return result;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,20 +1,20 @@
 int smu7_power_control_set_level(struct pp_hwmgr *hwmgr) {
   struct phm_ppt_v1_information *table_info = (struct phm_ppt_v1_information *)(hwmgr->pptable);
   struct phm_cac_tdp_table *cac_table;
   int adjust_percent, target_tdp;
   int result = 0;
   if (hwmgr->pp_table_version == PP_TABLE_V1)
     cac_table = table_info->cac_dtp_table;
   else
     cac_table = hwmgr->dyn_state.cac_dtp_table;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
+  if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
     /* adjustment percentage has already been validated */
     adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ? hwmgr->platform_descriptor.TDPAdjustment : (-1 * hwmgr->platform_descriptor.TDPAdjustment);
     /* SMC requested that target_tdp to be 7 bit fraction in DPM table
      * but message to be 8 bit fraction for messages
      */
     target_tdp = ((100 + adjust_percent) * (int)(cac_table->usTDP * 256)) / 100;
     result = smu7_set_overdriver_target_tdp(hwmgr, (uint32_t)target_tdp);
   }
   return result;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,32 +1,32 @@
 static int cz_apply_state_adjust_rules(struct pp_hwmgr *hwmgr, struct pp_power_state *prequest_ps, const struct pp_power_state *pcurrent_ps) {
   struct cz_power_state *cz_ps = cast_PhwCzPowerState(&prequest_ps->hardware);
   const struct cz_power_state *cz_current_ps = cast_const_PhwCzPowerState(&pcurrent_ps->hardware);
   struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
   struct PP_Clocks clocks = {0, 0, 0, 0};
   bool force_high;
   uint32_t num_of_active_displays = 0;
   struct cgs_display_info info = {0};
   cz_ps->evclk = hwmgr->vce_arbiter.evclk;
   cz_ps->ecclk = hwmgr->vce_arbiter.ecclk;
   cz_ps->need_dfs_bypass = true;
   cz_hwmgr->video_start = (hwmgr->uvd_arbiter.vclk != 0 || hwmgr->uvd_arbiter.dclk != 0 || hwmgr->vce_arbiter.evclk != 0 || hwmgr->vce_arbiter.ecclk != 0);
   cz_hwmgr->battery_state = (PP_StateUILabel_Battery == prequest_ps->classification.ui_label);
   clocks.memoryClock = hwmgr->display_config.min_mem_set_clock != 0 ? hwmgr->display_config.min_mem_set_clock : cz_hwmgr->sys_info.nbp_memory_clock[1];
   cgs_get_active_displays_info(hwmgr->device, &info);
   num_of_active_displays = info.display_count;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
+  if (PP_CAP(PHM_PlatformCaps_StablePState)) clocks.memoryClock = hwmgr->dyn_state.max_clock_voltage_on_ac.mclk;
   if (clocks.memoryClock < hwmgr->gfx_arbiter.mclk) clocks.memoryClock = hwmgr->gfx_arbiter.mclk;
   force_high = (clocks.memoryClock > cz_hwmgr->sys_info.nbp_memory_clock[CZ_NUM_NBPMEMORYCLOCK - 1]) || (num_of_active_displays >= 3);
   cz_ps->action = cz_current_ps->action;
   if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_PEAK)
     cz_nbdpm_pstate_enable_disable(hwmgr, false, false);
   else if (hwmgr->request_dpm_level == AMD_DPM_FORCED_LEVEL_PROFILE_STANDARD)
     cz_nbdpm_pstate_enable_disable(hwmgr, false, true);
   else if (!force_high && (cz_ps->action == FORCE_HIGH))
     cz_ps->action = CANCEL_FORCE_HIGH;
   else if (force_high && (cz_ps->action != FORCE_HIGH))
     cz_ps->action = FORCE_HIGH;
   else
     cz_ps->action = DO_NOTHING;
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,15 +1,15 @@
 static int cz_dpm_get_pp_table_entry_callback(struct pp_hwmgr *hwmgr, struct pp_hw_power_state *hw_ps, unsigned int index, const void *clock_info) {
   struct cz_power_state *cz_ps = cast_PhwCzPowerState(hw_ps);
   const ATOM_PPLIB_CZ_CLOCK_INFO *cz_clock_info = clock_info;
   struct phm_clock_voltage_dependency_table *table = hwmgr->dyn_state.vddc_dependency_on_sclk;
   uint8_t clock_info_index = cz_clock_info->index;
   if (clock_info_index > (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1)) clock_info_index = (uint8_t)(hwmgr->platform_descriptor.hardwareActivityPerformanceLevels - 1);
   cz_ps->levels[index].engineClock = table->entries[clock_info_index].clk;
   cz_ps->levels[index].vddcIndex = (uint8_t)table->entries[clock_info_index].v;
   cz_ps->level = index + 1;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
+  if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
     cz_ps->levels[index].dsDividerIndex = 5;
     cz_ps->levels[index].ssDividerIndex = 5;
   }
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,4 +1,4 @@
 int cz_dpm_powerup_vce(struct pp_hwmgr *hwmgr) {
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_VCEPowerGating)) return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_VCEPowerON);
+  if (PP_CAP(PHM_PlatformCaps_VCEPowerGating)) return smum_send_msg_to_smc(hwmgr, PPSMC_MSG_VCEPowerON);
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,9 +1,9 @@
 static int cz_set_deep_sleep_sclk_threshold(struct pp_hwmgr *hwmgr) {
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
+  if (PP_CAP(PHM_PlatformCaps_SclkDeepSleep)) {
     uint32_t clks = hwmgr->display_config.min_core_set_clock_in_sr;
     if (clks == 0) clks = CZ_MIN_DEEP_SLEEP_SCLK;
     PP_DBG_LOG("Setting Deep Sleep Clock: %d\n", clks);
     smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetMinDeepSleepSclk, clks);
   }
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,39 +1,39 @@
 static int cz_update_sclk_limit(struct pp_hwmgr *hwmgr) {
   struct cz_hwmgr *cz_hwmgr = (struct cz_hwmgr *)(hwmgr->backend);
   struct phm_clock_voltage_dependency_table *table = hwmgr->dyn_state.vddc_dependency_on_sclk;
   unsigned long clock = 0;
   unsigned long level;
   unsigned long stable_pstate_sclk;
   unsigned long percentage;
   cz_hwmgr->sclk_dpm.soft_min_clk = table->entries[0].clk;
   level = cz_get_max_sclk_level(hwmgr) - 1;
   if (level < table->count)
     cz_hwmgr->sclk_dpm.soft_max_clk = table->entries[level].clk;
   else
     cz_hwmgr->sclk_dpm.soft_max_clk = table->entries[table->count - 1].clk;
   clock = hwmgr->display_config.min_core_set_clock;
   if (clock == 0) pr_debug("min_core_set_clock not set\n");
   if (cz_hwmgr->sclk_dpm.hard_min_clk != clock) {
     cz_hwmgr->sclk_dpm.hard_min_clk = clock;
     smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkHardMin, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.hard_min_clk, PPSMC_MSG_SetSclkHardMin));
   }
   clock = cz_hwmgr->sclk_dpm.soft_min_clk;
   /* update minimum clocks for Stable P-State feature */
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState)) {
+  if (PP_CAP(PHM_PlatformCaps_StablePState)) {
     percentage = 75;
     /*Sclk - calculate sclk value based on percentage and find FLOOR sclk from VddcDependencyOnSCLK table  */
     stable_pstate_sclk = (hwmgr->dyn_state.max_clock_voltage_on_ac.mclk * percentage) / 100;
     if (clock < stable_pstate_sclk) clock = stable_pstate_sclk;
   } else {
     if (clock < hwmgr->gfx_arbiter.sclk) clock = hwmgr->gfx_arbiter.sclk;
   }
   if (cz_hwmgr->sclk_dpm.soft_min_clk != clock) {
     cz_hwmgr->sclk_dpm.soft_min_clk = clock;
     smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMin, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.soft_min_clk, PPSMC_MSG_SetSclkSoftMin));
   }
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_StablePState) && cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
+  if (PP_CAP(PHM_PlatformCaps_StablePState) && cz_hwmgr->sclk_dpm.soft_max_clk != clock) {
     cz_hwmgr->sclk_dpm.soft_max_clk = clock;
     smum_send_msg_to_smc_with_parameter(hwmgr, PPSMC_MSG_SetSclkSoftMax, cz_get_sclk_level(hwmgr, cz_hwmgr->sclk_dpm.soft_max_clk, PPSMC_MSG_SetSclkSoftMax));
   }
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,15 +1,15 @@
 static s8 phy_GetChannelIndexOfTxPowerLimit(u8 Band, u8 Channel) {
   s8 channelIndex = -1;
   u8 channel5G[CHANNEL_MAX_NUMBER_5G] = {36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 149, 151, 153, 155, 157, 159, 161, 163, 165, 167, 168, 169, 171, 173, 175, 177};
   u8 i = 0;
   if (Band == BAND_ON_2_4G)
     channelIndex = Channel - 1;
   else if (Band == BAND_ON_5G) {
-    for (i = 0; i < sizeof(channel5G) / sizeof(u8); ++i) {
+    for (i = 0; i < ARRAY_SIZE(channel5G); ++i) {
       if (channel5G[i] == Channel) channelIndex = i;
     }
   } else
     DBG_871X("Invalid Band %d in %s", Band, __func__);
   if (channelIndex == -1) DBG_871X("Invalid Channel %d of Band %d in %s", Channel, Band, __func__);
   return channelIndex;
 }<sep>@@
type T;
T[] E;
@@
- ((sizeof(E) /sizeof(T)))
+ ARRAY_SIZE(E)
--- initial
+++ final
@@ -1,18 +1,18 @@
 static bool phy_GetChnlIndex(u8 Channel, u8 *ChannelIdx) {
   u8 channel5G[CHANNEL_MAX_NUMBER_5G] = {36, 38, 40, 42, 44, 46, 48, 50, 52, 54, 56, 58, 60, 62, 64, 100, 102, 104, 106, 108, 110, 112, 114, 116, 118, 120, 122, 124, 126, 128, 130, 132, 134, 136, 138, 140, 142, 144, 149, 151, 153, 155, 157, 159, 161, 163, 165, 167, 168, 169, 171, 173, 175, 177};
   u8 i = 0;
   bool bIn24G = true;
   if (Channel <= 14) {
     bIn24G = true;
     *ChannelIdx = Channel - 1;
   } else {
     bIn24G = false;
-    for (i = 0; i < sizeof(channel5G) / sizeof(u8); ++i) {
+    for (i = 0; i < ARRAY_SIZE(channel5G); ++i) {
       if (channel5G[i] == Channel) {
         *ChannelIdx = i;
         return bIn24G;
       }
     }
   }
   return bIn24G;
 }<sep>@@
type T;
T[] E;
@@
- ((sizeof(E) /sizeof(T)))
+ ARRAY_SIZE(E)
--- initial
+++ final
@@ -1,40 +1,40 @@
 static int gfx_v8_0_init_save_restore_list(struct amdgpu_device *adev) {
   int i, temp, data;
   int unique_indices[] = {0, 0, 0, 0, 0, 0, 0, 0};
   int indices_count = 0;
   int indirect_start_offsets[] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
   int offset_count = 0;
   int list_size;
   unsigned int *register_list_format = kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
   if (!register_list_format) return -ENOMEM;
   memcpy(register_list_format, adev->gfx.rlc.register_list_format, adev->gfx.rlc.reg_list_format_size_bytes);
-  gfx_v8_0_parse_ind_reg_list(register_list_format, RLC_FormatDirectRegListLength, adev->gfx.rlc.reg_list_format_size_bytes >> 2, unique_indices, &indices_count, sizeof(unique_indices) / sizeof(int), indirect_start_offsets, &offset_count, sizeof(indirect_start_offsets) / sizeof(int));
+  gfx_v8_0_parse_ind_reg_list(register_list_format, RLC_FormatDirectRegListLength, adev->gfx.rlc.reg_list_format_size_bytes >> 2, unique_indices, &indices_count, ARRAY_SIZE(unique_indices), indirect_start_offsets, &offset_count, ARRAY_SIZE(indirect_start_offsets));
   /* save and restore list */
   WREG32_FIELD(RLC_SRM_CNTL, AUTO_INCR_ADDR, 1);
   WREG32(mmRLC_SRM_ARAM_ADDR, 0);
   for (i = 0; i<adev->gfx.rlc.reg_list_size_bytes> > 2; i++)
     WREG32(mmRLC_SRM_ARAM_DATA, adev->gfx.rlc.register_restore[i]);
   /* indirect list */
   WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_list_format_start);
   for (i = 0; i<adev->gfx.rlc.reg_list_format_size_bytes> > 2; i++)
     WREG32(mmRLC_GPM_SCRATCH_DATA, register_list_format[i]);
   list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
   list_size = list_size >> 1;
   WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.reg_restore_list_size);
   WREG32(mmRLC_GPM_SCRATCH_DATA, list_size);
   /* starting offsets starts */
   WREG32(mmRLC_GPM_SCRATCH_ADDR, adev->gfx.rlc.starting_offsets_start);
-  for (i = 0; i < sizeof(indirect_start_offsets) / sizeof(int); i++)
+  for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
     WREG32(mmRLC_GPM_SCRATCH_DATA, indirect_start_offsets[i]);
   /* unique indices */
   temp = mmRLC_SRM_INDEX_CNTL_ADDR_0;
   data = mmRLC_SRM_INDEX_CNTL_DATA_0;
-  for (i = 0; i < sizeof(unique_indices) / sizeof(int); i++) {
+  for (i = 0; i < ARRAY_SIZE(unique_indices); i++) {
     if (unique_indices[i] != 0) {
       WREG32(temp + i, unique_indices[i] & 0x3FFFF);
       WREG32(data + i, unique_indices[i] >> 20);
     }
   }
   kfree(register_list_format);
   return 0;
 }<sep>@@
type T;
T[] E;
@@
- ((sizeof(E) /sizeof(T)))
+ ARRAY_SIZE(E)
--- initial
+++ final
@@ -1,9 +1,9 @@
 static void reg_r(struct gspca_dev *gspca_dev, __u16 index, __u16 len) {
   struct usb_device *dev = gspca_dev->dev;
   if (len > USB_BUF_SZ) {
-    PERR("reg_r: buffer overflow\n");
+    gspca_err(gspca_dev, "reg_r: buffer overflow\n");
     return;
   }
   usb_control_msg(dev, usb_rcvctrlpipe(dev, 0), 0, USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 0, index, gspca_dev->usb_buf, len, 500);
   PDEBUG(D_USBI, "reg read [%02x] -> %02x ..", index, gspca_dev->usb_buf[0]);
 }<sep>@@
if String.length c < 3 || not(String.sub c (String.length c - 3) 2 = "\\n")
then c1 := make_expr ((String.sub c 0 (String.length c - 1)) ^ "\\n\"")
else c1 := make_expr c

@@
symbol gspca_dev;
constant char[] r.c;
expression s.c1;
@@
-               PERR(c
+               gspca_err(gspca_dev,c1
		,...)
--- initial
+++ final
@@ -1,10 +1,10 @@
 static void reg_w(struct gspca_dev *gspca_dev, __u16 index, const __u8 *buffer, __u16 len) {
   struct usb_device *dev = gspca_dev->dev;
   if (len > USB_BUF_SZ) {
-    PERR("reg_w: buffer overflow\n");
+    gspca_err(gspca_dev, "reg_w: buffer overflow\n");
     return;
   }
   PDEBUG(D_USBO, "reg write [%02x] = %02x..", index, *buffer);
   memcpy(gspca_dev->usb_buf, buffer, len);
   usb_control_msg(dev, usb_sndctrlpipe(dev, 0), 0, USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE, 0, index, gspca_dev->usb_buf, len, 500);
 }<sep>@@
if String.length c < 3 || not(String.sub c (String.length c - 3) 2 = "\\n")
then c1 := make_expr ((String.sub c 0 (String.length c - 1)) ^ "\\n\"")
else c1 := make_expr c

@@
symbol gspca_dev;
constant char[] r.c;
expression s.c1;
@@
-               PERR(c
+               gspca_err(gspca_dev,c1
		,...)
--- initial
+++ final
@@ -1,16 +1,16 @@
 static void dtcs033_setexposure(struct gspca_dev *gspca_dev, s32 expo, s32 gain) {
   /* gain [dB] encoding */
   u16 sGain = (u16)gain;
   u16 gainVal = 224 + (sGain - 14) * (768 - 224) / (33 - 14);
   u16 wIndex = 0x0100 | (0x00FF & gainVal);
   u16 wValue = (0xFF00 & gainVal) >> 8;
   /* exposure time [msec] encoding */
   u16 sXTime = (u16)expo;
   u16 xtimeVal = (524 * (150 - (sXTime - 1))) / 150;
   const u8 bRequestType = USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE;
   const u8 bRequest = 0x18;
   reg_rw(gspca_dev, bRequestType, bRequest, wValue, wIndex, 0);
-  if (gspca_dev->usb_err < 0) PERR("usb error in setexposure(gain) sequence.\n");
+  if (gspca_dev->usb_err < 0) gspca_err(gspca_dev, "usb error in setexposure(gain) sequence.\n");
   reg_rw(gspca_dev, bRequestType, bRequest, (xtimeVal << 4), 0x6300, 0);
-  if (gspca_dev->usb_err < 0) PERR("usb error in setexposure(time) sequence.\n");
+  if (gspca_dev->usb_err < 0) gspca_err(gspca_dev, "usb error in setexposure(time) sequence.\n");
 }<sep>@@
if String.length c < 3 || not(String.sub c (String.length c - 3) 2 = "\\n")
then c1 := make_expr ((String.sub c 0 (String.length c - 1)) ^ "\\n\"")
else c1 := make_expr c

@@
symbol gspca_dev;
constant char[] r.c;
expression s.c1;
@@
-               PERR(c
+               gspca_err(gspca_dev,c1
		,...)
--- initial
+++ final
@@ -1,9 +1,9 @@
 static int et_video(struct gspca_dev *gspca_dev, int on) {
   int ret;
   reg_w_val(gspca_dev, ET_GPIO_OUT,
             on ? 0x10 /* startvideo - set Bit5 */
                : 0);  /* stopvideo */
   ret = Et_WaitStatus(gspca_dev);
-  if (ret != 0) PERR("timeout video on/off");
+  if (ret != 0) gspca_err(gspca_dev, "timeout video on/off\n");
   return ret;
 }<sep>@@
if String.length c < 3 || not(String.sub c (String.length c - 3) 2 = "\\n")
then c1 := make_expr ((String.sub c 0 (String.length c - 1)) ^ "\\n\"")
else c1 := make_expr c

@@
symbol gspca_dev;
constant char[] r.c;
expression s.c1;
@@
-               PERR(c
+               gspca_err(gspca_dev,c1
		,...)