imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,43 +1,43 @@
 static int dce_v10_0_sw_init(void *handle) {
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
     r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
     if (r) return r;
   }
   for (i = 8; i < 20; i += 2) {
     r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
     if (r) return r;
   }
   /* HPD hotplug */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
   if (r) return r;
   adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
   adev->ddev->mode_config.async_page_flip = true;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   adev->ddev->mode_config.preferred_depth = 24;
   adev->ddev->mode_config.prefer_shadow = 1;
   adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
   r = amdgpu_display_modeset_create_props(adev);
   if (r) return r;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   /* allocate crtcs */
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
     r = dce_v10_0_crtc_init(adev, i);
     if (r) return r;
   }
   if (amdgpu_atombios_get_connector_info_from_object_table(adev))
     amdgpu_display_print_display_setup(adev->ddev);
   else
     return -EINVAL;
   /* setup afmt */
   r = dce_v10_0_afmt_init(adev);
   if (r) return r;
   r = dce_v10_0_audio_init(adev);
   if (r) return r;
   drm_kms_helper_poll_init(adev->ddev);
   adev->mode_info.mode_config_initialized = true;
   return 0;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 42
+ VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A
...+>,e3)
--- initial
+++ final
@@ -1,43 +1,43 @@
 static int dce_v11_0_sw_init(void *handle) {
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
     r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
     if (r) return r;
   }
   for (i = 8; i < 20; i += 2) {
     r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
     if (r) return r;
   }
   /* HPD hotplug */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A, &adev->hpd_irq);
   if (r) return r;
   adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
   adev->ddev->mode_config.async_page_flip = true;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   adev->ddev->mode_config.preferred_depth = 24;
   adev->ddev->mode_config.prefer_shadow = 1;
   adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
   r = amdgpu_display_modeset_create_props(adev);
   if (r) return r;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   /* allocate crtcs */
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
     r = dce_v11_0_crtc_init(adev, i);
     if (r) return r;
   }
   if (amdgpu_atombios_get_connector_info_from_object_table(adev))
     amdgpu_display_print_display_setup(adev->ddev);
   else
     return -EINVAL;
   /* setup afmt */
   r = dce_v11_0_afmt_init(adev);
   if (r) return r;
   r = dce_v11_0_audio_init(adev);
   if (r) return r;
   drm_kms_helper_poll_init(adev->ddev);
   adev->mode_info.mode_config_initialized = true;
   return 0;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 42
+ VISLANDS30_IV_SRCID_HOTPLUG_DETECT_A
...+>,e3)
--- initial
+++ final
@@ -1,27 +1,27 @@
 static int dce_virtual_sw_init(void *handle) {
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 229, &adev->crtc_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER, &adev->crtc_irq);
   if (r) return r;
   adev->ddev->max_vblank_count = 0;
   adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   adev->ddev->mode_config.preferred_depth = 24;
   adev->ddev->mode_config.prefer_shadow = 1;
   adev->ddev->mode_config.fb_base = adev->gmc.aper_base;
   r = amdgpu_display_modeset_create_props(adev);
   if (r) return r;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   /* allocate crtcs, encoders, connectors */
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
     r = dce_virtual_crtc_init(adev, i);
     if (r) return r;
     r = dce_virtual_connector_encoder_init(adev, i);
     if (r) return r;
   }
   drm_kms_helper_poll_init(adev->ddev);
   adev->mode_info.mode_config_initialized = true;
   return 0;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 229
+ VISLANDS30_IV_SRCID_SMU_DISP_TIMER2_TRIGGER
...+>,e3)
--- initial
+++ final
@@ -1,75 +1,75 @@
 static int gmc_v7_0_sw_init(void *handle) {
   int r;
   int dma_bits;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   if (adev->flags & AMD_IS_APU) {
     adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
   } else {
     u32 tmp = RREG32(mmMC_SEQ_MISC0);
     tmp &= MC_SEQ_MISC0__MT__MASK;
     adev->gmc.vram_type = gmc_v7_0_convert_vram_type(tmp);
   }
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
   if (r) return r;
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
   if (r) return r;
   /* Adjust VM size here.
    * Currently set to 4GB ((1 << 20) 4k pages).
    * Max GPUVM size for cayman and SI is 40 bits.
    */
   amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
   /* Set the internal MC address mask
    * This is the max address of the GPU's
    * internal address space.
    */
   adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
   /* set DMA mask + need_dma32 flags.
    * PCIE - can handle 40-bits.
    * IGP - can handle 40-bits
    * PCI - dma32 for legacy pci gart, 40 bits on newer asics
    */
   adev->need_dma32 = false;
   dma_bits = adev->need_dma32 ? 32 : 40;
   r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
   if (r) {
     adev->need_dma32 = true;
     dma_bits = 32;
     pr_warn("amdgpu: No suitable DMA available\n");
   }
   r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
   if (r) {
     pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
     pr_warn("amdgpu: No coherent DMA available\n");
   }
   adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
   r = gmc_v7_0_init_microcode(adev);
   if (r) {
     DRM_ERROR("Failed to load mc firmware!\n");
     return r;
   }
   r = gmc_v7_0_mc_init(adev);
   if (r) return r;
   adev->gmc.stolen_size = gmc_v7_0_get_vbios_fb_size(adev);
   /* Memory manager */
   r = amdgpu_bo_init(adev);
   if (r) return r;
   r = gmc_v7_0_gart_init(adev);
   if (r) return r;
   /*
    * number of VMs
    * VMID 0 is reserved for System
    * amdgpu graphics/compute will use VMIDs 1-7
    * amdkfd will use VMIDs 8-15
    */
   adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
   amdgpu_vm_manager_init(adev);
   /* base offset of vram pages */
   if (adev->flags & AMD_IS_APU) {
     u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
     tmp <<= 22;
     adev->vm_manager.vram_base_offset = tmp;
   } else {
     adev->vm_manager.vram_base_offset = 0;
   }
   return 0;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 146
+ VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT
...+>,e3)
@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 147
+ VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT 
...+>,e3)
--- initial
+++ final
@@ -1,79 +1,79 @@
 static int gmc_v8_0_sw_init(void *handle) {
   int r;
   int dma_bits;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   if (adev->flags & AMD_IS_APU) {
     adev->gmc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
   } else {
     u32 tmp;
     if ((adev->asic_type == CHIP_FIJI) || (adev->asic_type == CHIP_VEGAM))
       tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
     else
       tmp = RREG32(mmMC_SEQ_MISC0);
     tmp &= MC_SEQ_MISC0__MT__MASK;
     adev->gmc.vram_type = gmc_v8_0_convert_vram_type(tmp);
   }
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->gmc.vm_fault);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT, &adev->gmc.vm_fault);
   if (r) return r;
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->gmc.vm_fault);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT, &adev->gmc.vm_fault);
   if (r) return r;
   /* Adjust VM size here.
    * Currently set to 4GB ((1 << 20) 4k pages).
    * Max GPUVM size for cayman and SI is 40 bits.
    */
   amdgpu_vm_adjust_size(adev, 64, 9, 1, 40);
   /* Set the internal MC address mask
    * This is the max address of the GPU's
    * internal address space.
    */
   adev->gmc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
   /* set DMA mask + need_dma32 flags.
    * PCIE - can handle 40-bits.
    * IGP - can handle 40-bits
    * PCI - dma32 for legacy pci gart, 40 bits on newer asics
    */
   adev->need_dma32 = false;
   dma_bits = adev->need_dma32 ? 32 : 40;
   r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
   if (r) {
     adev->need_dma32 = true;
     dma_bits = 32;
     pr_warn("amdgpu: No suitable DMA available\n");
   }
   r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
   if (r) {
     pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
     pr_warn("amdgpu: No coherent DMA available\n");
   }
   adev->need_swiotlb = drm_get_max_iomem() > ((u64)1 << dma_bits);
   r = gmc_v8_0_init_microcode(adev);
   if (r) {
     DRM_ERROR("Failed to load mc firmware!\n");
     return r;
   }
   r = gmc_v8_0_mc_init(adev);
   if (r) return r;
   adev->gmc.stolen_size = gmc_v8_0_get_vbios_fb_size(adev);
   /* Memory manager */
   r = amdgpu_bo_init(adev);
   if (r) return r;
   r = gmc_v8_0_gart_init(adev);
   if (r) return r;
   /*
    * number of VMs
    * VMID 0 is reserved for System
    * amdgpu graphics/compute will use VMIDs 1-7
    * amdkfd will use VMIDs 8-15
    */
   adev->vm_manager.id_mgr[0].num_ids = AMDGPU_NUM_OF_VMIDS;
   amdgpu_vm_manager_init(adev);
   /* base offset of vram pages */
   if (adev->flags & AMD_IS_APU) {
     u64 tmp = RREG32(mmMC_VM_FB_OFFSET);
     tmp <<= 22;
     adev->vm_manager.vram_base_offset = tmp;
   } else {
     adev->vm_manager.vram_base_offset = 0;
   }
   return 0;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 146
+ VISLANDS30_IV_SRCID_GFX_PAGE_INV_FAULT
...+>,e3)
@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 147
+ VISLANDS30_IV_SRCID_GFX_MEM_PROT_FAULT 
...+>,e3)
--- initial
+++ final
@@ -1,28 +1,28 @@
 static int sdma_v2_4_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   /* SDMA trap event */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, &adev->sdma.trap_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, &adev->sdma.trap_irq);
   if (r) return r;
   /* SDMA Privileged inst */
   r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, &adev->sdma.illegal_inst_irq);
   if (r) return r;
   /* SDMA Privileged inst */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, &adev->sdma.illegal_inst_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, &adev->sdma.illegal_inst_irq);
   if (r) return r;
   r = sdma_v2_4_init_microcode(adev);
   if (r) {
     DRM_ERROR("Failed to load sdma firmware!\n");
     return r;
   }
   for (i = 0; i < adev->sdma.num_instances; i++) {
     ring = &adev->sdma.instance[i].ring;
     ring->ring_obj = NULL;
     ring->use_doorbell = false;
     sprintf(ring->name, "sdma%d", i);
     r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, (i == 0) ? AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1);
     if (r) return r;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 224
+ VISLANDS30_IV_SRCID_SDMA_TRAP	 
...+>,e3)
@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 247
+ VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE
...+>,e3)
--- initial
+++ final
@@ -1,33 +1,33 @@
 static int sdma_v3_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   /* SDMA trap event */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, &adev->sdma.trap_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_TRAP, &adev->sdma.trap_irq);
   if (r) return r;
   /* SDMA Privileged inst */
   r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, &adev->sdma.illegal_inst_irq);
   if (r) return r;
   /* SDMA Privileged inst */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, &adev->sdma.illegal_inst_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE, &adev->sdma.illegal_inst_irq);
   if (r) return r;
   r = sdma_v3_0_init_microcode(adev);
   if (r) {
     DRM_ERROR("Failed to load sdma firmware!\n");
     return r;
   }
   for (i = 0; i < adev->sdma.num_instances; i++) {
     ring = &adev->sdma.instance[i].ring;
     ring->ring_obj = NULL;
     if (!amdgpu_sriov_vf(adev)) {
       ring->use_doorbell = true;
       ring->doorbell_index = (i == 0) ? AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
     } else {
       ring->use_pollmem = true;
     }
     sprintf(ring->name, "sdma%d", i);
     r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, (i == 0) ? AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1);
     if (r) return r;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 224
+ VISLANDS30_IV_SRCID_SDMA_TRAP	 
...+>,e3)
@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 247
+ VISLANDS30_IV_SRCID_SDMA_SRBM_WRITE
...+>,e3)
--- initial
+++ final
@@ -1,10 +1,10 @@
 static int smu7_register_irq_handlers(struct pp_hwmgr *hwmgr) {
   struct amdgpu_irq_src *source = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
   if (!source) return -ENOMEM;
   source->funcs = &smu7_irq_funcs;
-  amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), AMDGPU_IH_CLIENTID_LEGACY, 230, source);
-  amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), AMDGPU_IH_CLIENTID_LEGACY, 231, source);
+  amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH, source);
+  amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW, source);
   /* Register CTF(GPIO_19) interrupt */
-  amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), AMDGPU_IH_CLIENTID_LEGACY, 83, source);
+  amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_GPIO_19, source);
   return 0;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 83
+ VISLANDS30_IV_SRCID_GPIO_19
...+>,e3)

@@
expression e1,e2,e3;
@@

amdgpu_irq_add_id(e1,e2,<+...
- 230
+ VISLANDS30_IV_SRCID_CG_TSS_THERMAL_LOW_TO_HIGH 
...+>,e3)
@@
expression e1,e2,e3;
@@

amdgpu_irq_add_id(e1,e2,<+...
- 231
+ VISLANDS30_IV_SRCID_CG_TSS_THERMAL_HIGH_TO_LOW 
...+>,e3)
--- initial
+++ final
@@ -1,16 +1,16 @@
 static int uvd_v5_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   int r;
   /* UVD TRAP */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
   if (r) return r;
   r = amdgpu_uvd_sw_init(adev);
   if (r) return r;
   r = amdgpu_uvd_resume(adev);
   if (r) return r;
   ring = &adev->uvd.inst->ring;
   sprintf(ring->name, "uvd");
   r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 124
+ VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE 
...+>,e3)
--- initial
+++ final
@@ -1,48 +1,48 @@
 static int uvd_v6_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   int i, r;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   /* UVD TRAP */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq);
   if (r) return r;
   /* UVD ENC TRAP */
   if (uvd_v6_0_enc_support(adev)) {
     for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-      r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.inst->irq);
+      r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq);
       if (r) return r;
     }
   }
   r = amdgpu_uvd_sw_init(adev);
   if (r) return r;
   if (!uvd_v6_0_enc_support(adev)) {
     for (i = 0; i < adev->uvd.num_enc_rings; ++i)
       adev->uvd.inst->ring_enc[i].funcs = NULL;
     adev->uvd.inst->irq.num_types = 1;
     adev->uvd.num_enc_rings = 0;
     DRM_INFO("UVD ENC is disabled\n");
   } else {
     struct drm_sched_rq *rq;
     ring = &adev->uvd.inst->ring_enc[0];
     rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
     r = drm_sched_entity_init(&ring->sched, &adev->uvd.inst->entity_enc, rq, NULL);
     if (r) {
       DRM_ERROR("Failed setting up UVD ENC run queue.\n");
       return r;
     }
   }
   r = amdgpu_uvd_resume(adev);
   if (r) return r;
   ring = &adev->uvd.inst->ring;
   sprintf(ring->name, "uvd");
   r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
   if (r) return r;
   if (uvd_v6_0_enc_support(adev)) {
     for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
       ring = &adev->uvd.inst->ring_enc[i];
       sprintf(ring->name, "uvd_enc%d", i);
       r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0);
       if (r) return r;
     }
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 119
+ VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP 
...+>,e3)
@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 124
+ VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE 
...+>,e3)
--- initial
+++ final
@@ -1,21 +1,21 @@
 static int vce_v3_0_sw_init(void *handle) {
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   struct amdgpu_ring *ring;
   int r, i;
   /* VCE */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 167, &adev->vce.irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_VCE_TRAP, &adev->vce.irq);
   if (r) return r;
   r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE + (VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE) * 2);
   if (r) return r;
   /* 52.8.3 required for 3 ring support */
   if (adev->vce.fw_version < FW_52_8_3) adev->vce.num_rings = 2;
   r = amdgpu_vce_resume(adev);
   if (r) return r;
   for (i = 0; i < adev->vce.num_rings; i++) {
     ring = &adev->vce.ring[i];
     sprintf(ring->name, "vce%d", i);
     r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0);
     if (r) return r;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 167
+ VISLANDS30_IV_SRCID_VCE_TRAP
...+>,e3)
--- initial
+++ final
@@ -1,28 +1,28 @@
 static int sdma_v4_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   /* SDMA trap event */
-  r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, 224, &adev->sdma.trap_irq);
+  r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA0, VISLANDS30_IV_SRCID_SDMA_TRAP, &adev->sdma.trap_irq);
   if (r) return r;
   /* SDMA trap event */
-  r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, 224, &adev->sdma.trap_irq);
+  r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_SDMA1, VISLANDS30_IV_SRCID_SDMA_TRAP, &adev->sdma.trap_irq);
   if (r) return r;
   r = sdma_v4_0_init_microcode(adev);
   if (r) {
     DRM_ERROR("Failed to load sdma firmware!\n");
     return r;
   }
   for (i = 0; i < adev->sdma.num_instances; i++) {
     ring = &adev->sdma.instance[i].ring;
     ring->ring_obj = NULL;
     ring->use_doorbell = true;
     DRM_INFO("use_doorbell being set to: [%s]\n", ring->use_doorbell ? "true" : "false");
     ring->doorbell_index = (i == 0) ? (AMDGPU_DOORBELL64_sDMA_ENGINE0 << 1)  // get DWORD offset
                                     : (AMDGPU_DOORBELL64_sDMA_ENGINE1 << 1); // get DWORD offset
     sprintf(ring->name, "sdma%d", i);
     r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, (i == 0) ? AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1);
     if (r) return r;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 224
+ VISLANDS30_IV_SRCID_SDMA_TRAP	 
...+>,e3)
--- initial
+++ final
@@ -1,10 +1,10 @@
 int smu9_register_irq_handlers(struct pp_hwmgr *hwmgr) {
   struct amdgpu_irq_src *source = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
   if (!source) return -ENOMEM;
   source->funcs = &smu9_irq_funcs;
   amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), SOC15_IH_CLIENTID_THM, 0, source);
   amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), SOC15_IH_CLIENTID_THM, 1, source);
   /* Register CTF(GPIO_19) interrupt */
-  amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), SOC15_IH_CLIENTID_ROM_SMUIO, 83, source);
+  amdgpu_irq_add_id((struct amdgpu_device *)(hwmgr->adev), SOC15_IH_CLIENTID_ROM_SMUIO, VISLANDS30_IV_SRCID_GPIO_19, source);
   return 0;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 83
+ VISLANDS30_IV_SRCID_GPIO_19
...+>,e3)