--- initial
+++ final
@@ -1,81 +1,81 @@
 static int fsl_ifc_chip_init(struct fsl_ifc_mtd *priv) {
   struct fsl_ifc_ctrl *ctrl = priv->ctrl;
   struct fsl_ifc_global __iomem *ifc_global = ctrl->gregs;
   struct fsl_ifc_runtime __iomem *ifc_runtime = ctrl->rregs;
   struct nand_chip *chip = &priv->chip;
   struct mtd_info *mtd = nand_to_mtd(&priv->chip);
   u32 csor;
   int ret;
   /* Fill in fsl_ifc_mtd structure */
   mtd->dev.parent = priv->dev;
   nand_set_flash_node(chip, priv->dev->of_node);
   /* fill in nand_chip structure */
   /* set up function call table */
   if ((ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr)) & CSPR_PORT_SIZE_16)
     chip->legacy.read_byte = fsl_ifc_read_byte16;
   else
     chip->legacy.read_byte = fsl_ifc_read_byte;
   chip->legacy.write_buf = fsl_ifc_write_buf;
   chip->legacy.read_buf = fsl_ifc_read_buf;
   chip->select_chip = fsl_ifc_select_chip;
-  chip->cmdfunc = fsl_ifc_cmdfunc;
+  chip->legacy.cmdfunc = fsl_ifc_cmdfunc;
   chip->waitfunc = fsl_ifc_wait;
   chip->set_features = nand_get_set_features_notsupp;
   chip->get_features = nand_get_set_features_notsupp;
   chip->bbt_td = &bbt_main_descr;
   chip->bbt_md = &bbt_mirror_descr;
   ifc_out32(0x0, &ifc_runtime->ifc_nand.ncfgr);
   /* set up nand options */
   chip->bbt_options = NAND_BBT_USE_FLASH;
   chip->options = NAND_NO_SUBPAGE_WRITE;
   if (ifc_in32(&ifc_global->cspr_cs[priv->bank].cspr) & CSPR_PORT_SIZE_16) {
     chip->legacy.read_byte = fsl_ifc_read_byte16;
     chip->options |= NAND_BUSWIDTH_16;
   } else {
     chip->legacy.read_byte = fsl_ifc_read_byte;
   }
   chip->controller = &ifc_nand_ctrl->controller;
   nand_set_controller_data(chip, priv);
   chip->ecc.read_page = fsl_ifc_read_page;
   chip->ecc.write_page = fsl_ifc_write_page;
   csor = ifc_in32(&ifc_global->csor_cs[priv->bank].csor);
   switch (csor & CSOR_NAND_PGS_MASK) {
   case CSOR_NAND_PGS_512:
     if (!(chip->options & NAND_BUSWIDTH_16)) {
       /* Avoid conflict with bad block marker */
       bbt_main_descr.offs = 0;
       bbt_mirror_descr.offs = 0;
     }
     priv->bufnum_mask = 15;
     break;
   case CSOR_NAND_PGS_2K: priv->bufnum_mask = 3; break;
   case CSOR_NAND_PGS_4K: priv->bufnum_mask = 1; break;
   case CSOR_NAND_PGS_8K: priv->bufnum_mask = 0; break;
   default: dev_err(priv->dev, "bad csor %#x: bad page size\n", csor); return -ENODEV;
   }
   /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
   if (csor & CSOR_NAND_ECC_DEC_EN) {
     chip->ecc.mode = NAND_ECC_HW;
     mtd_set_ooblayout(mtd, &fsl_ifc_ooblayout_ops);
     /* Hardware generates ECC per 512 Bytes */
     chip->ecc.size = 512;
     if ((csor & CSOR_NAND_ECC_MODE_MASK) == CSOR_NAND_ECC_MODE_4) {
       chip->ecc.bytes = 8;
       chip->ecc.strength = 4;
     } else {
       chip->ecc.bytes = 16;
       chip->ecc.strength = 8;
     }
   } else {
     chip->ecc.mode = NAND_ECC_SOFT;
     chip->ecc.algo = NAND_ECC_HAMMING;
   }
   ret = fsl_ifc_sram_init(priv);
   if (ret) return ret;
   /*
    * As IFC version 2.0.0 has 16KB of internal SRAM as compared to older
    * versions which had 8KB. Hence bufnum mask needs to be updated.
    */
   if (ctrl->version >= FSL_IFC_VERSION_2_0_0) priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
   return 0;
 }<sep>@@
expression chip; 
@@
- chip->cmdfunc
+ chip->legacy.cmdfunc