--- initial
+++ final
@@ -1,97 +1,97 @@
 static void nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode *mode) {
   struct drm_device *dev = crtc->dev;
   struct nouveau_drm *drm = nouveau_drm(dev);
   struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc);
   struct nv04_crtc_reg *regp = &nv04_display(dev)->mode_reg.crtc_reg[nv_crtc->index];
   struct nv04_crtc_reg *savep = &nv04_display(dev)->saved_reg.crtc_reg[nv_crtc->index];
   const struct drm_framebuffer *fb = crtc->primary->fb;
   struct drm_encoder *encoder;
   bool lvds_output = false, tmds_output = false, tv_output = false, off_chip_digital = false;
   list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
     struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
     bool digital = false;
     if (encoder->crtc != crtc) continue;
     if (nv_encoder->dcb->type == DCB_OUTPUT_LVDS) digital = lvds_output = true;
     if (nv_encoder->dcb->type == DCB_OUTPUT_TV) tv_output = true;
     if (nv_encoder->dcb->type == DCB_OUTPUT_TMDS) digital = tmds_output = true;
     if (nv_encoder->dcb->location != DCB_LOC_ON_CHIP && digital) off_chip_digital = true;
   }
   /* Registers not directly related to the (s)vga mode */
   /* What is the meaning of this register? */
   /* A few popular values are 0x18, 0x1c, 0x38, 0x3c */
   regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1 << 5);
   regp->crtc_eng_ctrl = 0;
   /* Except for rare conditions I2C is enabled on the primary crtc */
   if (nv_crtc->index == 0) regp->crtc_eng_ctrl |= NV_CRTC_FSEL_I2C;
 #if 0
 	/* Set overlay to desired crtc. */
 	if (dev->overlayAdaptor) {
 		NVPortPrivPtr pPriv = GET_OVERLAY_PRIVATE(dev);
 		if (pPriv->overlayCRTC == nv_crtc->index)
 			regp->crtc_eng_ctrl |= NV_CRTC_FSEL_OVERLAY;
 	}
 #endif
   /* ADDRESS_SPACE_PNVM is the same as setting HCUR_ASI */
   regp->cursor_cfg = NV_PCRTC_CURSOR_CONFIG_CUR_LINES_64 | NV_PCRTC_CURSOR_CONFIG_CUR_PIXELS_64 | NV_PCRTC_CURSOR_CONFIG_ADDRESS_SPACE_PNVM;
   if (drm->device.info.chipset >= 0x11) regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_CUR_BPP_32;
   if (mode->flags & DRM_MODE_FLAG_DBLSCAN) regp->cursor_cfg |= NV_PCRTC_CURSOR_CONFIG_DOUBLE_SCAN_ENABLE;
   /* Unblock some timings */
   regp->CRTC[NV_CIO_CRE_53] = 0;
   regp->CRTC[NV_CIO_CRE_54] = 0;
   /* 0x00 is disabled, 0x11 is lvds, 0x22 crt and 0x88 tmds */
   if (lvds_output)
     regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11;
   else if (tmds_output)
     regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88;
   else
     regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22;
   /* These values seem to vary */
   /* This register seems to be used by the bios to make certain decisions on some G70 cards? */
   regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX];
   nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation);
   /* probably a scratch reg, but kept for cargo-cult purposes:
    * bit0: crtc0?, head A
    * bit6: lvds, head A
    * bit7: (only in X), head A
    */
   if (nv_crtc->index == 0) regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80;
   /* The blob seems to take the current value from crtc 0, add 4 to that
    * and reuse the old value for crtc 1 */
   regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TVOUT_LATENCY];
   if (!nv_crtc->index) regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4;
   /* the blob sometimes sets |= 0x10 (which is the same as setting |=
    * 1 << 30 on 0x60.830), for no apparent reason */
   regp->CRTC[NV_CIO_CRE_59] = off_chip_digital;
   if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1;
   regp->crtc_830 = mode->crtc_vdisplay - 3;
   regp->crtc_834 = mode->crtc_vdisplay - 1;
   if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) /* This is what the blob does */
     regp->crtc_850 = NVReadCRTC(dev, 0, NV_PCRTC_850);
   if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) regp->gpio_ext = NVReadCRTC(dev, 0, NV_PCRTC_GPIO_EXT);
   if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS)
     regp->crtc_cfg = NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC;
   else
     regp->crtc_cfg = NV04_PCRTC_CONFIG_START_ADDRESS_HSYNC;
   /* Some misc regs */
   if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
     regp->CRTC[NV_CIO_CRE_85] = 0xFF;
     regp->CRTC[NV_CIO_CRE_86] = 0x1;
   }
-  regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->depth + 1) / 8;
+  regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8;
   /* Enable slaved mode (called MODE_TV in nv4ref.h) */
   if (lvds_output || tmds_output || tv_output) regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7);
   /* Generic PRAMDAC regs */
   if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) /* Only bit that bios and blob set. */
     regp->nv10_cursync = (1 << 25);
   regp->ramdac_gen_ctrl = NV_PRAMDAC_GENERAL_CONTROL_BPC_8BITS | NV_PRAMDAC_GENERAL_CONTROL_VGA_STATE_SEL | NV_PRAMDAC_GENERAL_CONTROL_PIXMIX_ON;
-  if (fb->depth == 16) regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
+  if (fb->format->depth == 16) regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_ALT_MODE_SEL;
   if (drm->device.info.chipset >= 0x11) regp->ramdac_gen_ctrl |= NV_PRAMDAC_GENERAL_CONTROL_PIPE_LONG;
   regp->ramdac_630 = 0; /* turn off green mode (tv test pattern?) */
   regp->tv_setup = 0;
   nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness);
   /* Some values the blob sets */
   regp->ramdac_8c0 = 0x100;
   regp->ramdac_a20 = 0x0;
   regp->ramdac_a24 = 0xfffff;
   regp->ramdac_a34 = 0x1;
 }<sep>@@
struct drm_framebuffer *fb;
@@
- fb->depth
+ fb->format->depth

@@
struct drm_framebuffer *fb;
@@
- (fb->format->depth)
+ fb->format->depth