imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,35 +1,36 @@
 int vmw_compat_shader_add(struct vmw_private *dev_priv, struct vmw_cmdbuf_res_manager *man, u32 user_key, const void *bytecode, SVGA3dShaderType shader_type, size_t size, struct list_head *list) {
+  struct ttm_operation_ctx ctx = {false, true};
   struct vmw_dma_buffer *buf;
   struct ttm_bo_kmap_obj map;
   bool is_iomem;
   int ret;
   struct vmw_resource *res;
   if (!vmw_shader_id_ok(user_key, shader_type)) return -EINVAL;
   /* Allocate and pin a DMA buffer */
   buf = kzalloc(sizeof(*buf), GFP_KERNEL);
   if (unlikely(!buf)) return -ENOMEM;
   ret = vmw_dmabuf_init(dev_priv, buf, size, &vmw_sys_ne_placement, true, vmw_dmabuf_bo_free);
   if (unlikely(ret != 0)) goto out;
   ret = ttm_bo_reserve(&buf->base, false, true, NULL);
   if (unlikely(ret != 0)) goto no_reserve;
   /* Map and copy shader bytecode. */
   ret = ttm_bo_kmap(&buf->base, 0, PAGE_ALIGN(size) >> PAGE_SHIFT, &map);
   if (unlikely(ret != 0)) {
     ttm_bo_unreserve(&buf->base);
     goto no_reserve;
   }
   memcpy(ttm_kmap_obj_virtual(&map, &is_iomem), bytecode, size);
   WARN_ON(is_iomem);
   ttm_bo_kunmap(&map);
-  ret = ttm_bo_validate(&buf->base, &vmw_sys_placement, false, true);
+  ret = ttm_bo_validate(&buf->base, &vmw_sys_placement, &ctx);
   WARN_ON(ret != 0);
   ttm_bo_unreserve(&buf->base);
   res = vmw_shader_alloc(dev_priv, buf, size, 0, shader_type);
   if (unlikely(ret != 0)) goto no_reserve;
   ret = vmw_cmdbuf_res_add(man, vmw_cmdbuf_res_shader, vmw_shader_key(user_key, shader_type), res, list);
   vmw_resource_unreference(&res);
 no_reserve:
   vmw_dmabuf_unreference(&buf);
 out:
   return ret;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,16 +1,17 @@
 int vbox_bo_pin(struct vbox_bo *bo, u32 pl_flag, u64 *gpu_addr) {
+  struct ttm_operation_ctx ctx = {false, false};
   int i, ret;
   if (bo->pin_count) {
     bo->pin_count++;
     if (gpu_addr) *gpu_addr = vbox_bo_gpu_offset(bo);
     return 0;
   }
   vbox_ttm_placement(bo, pl_flag);
   for (i = 0; i < bo->placement.num_placement; i++)
     bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
-  ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+  ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
   if (ret) return ret;
   bo->pin_count = 1;
   if (gpu_addr) *gpu_addr = vbox_bo_gpu_offset(bo);
   return 0;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,19 +1,20 @@
 int vbox_bo_push_sysram(struct vbox_bo *bo) {
+  struct ttm_operation_ctx ctx = {false, false};
   int i, ret;
   if (!bo->pin_count) {
     DRM_ERROR("unpin bad %p\n", bo);
     return 0;
   }
   bo->pin_count--;
   if (bo->pin_count) return 0;
   if (bo->kmap.virtual) ttm_bo_kunmap(&bo->kmap);
   vbox_ttm_placement(bo, TTM_PL_FLAG_SYSTEM);
   for (i = 0; i < bo->placement.num_placement; i++)
     bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
-  ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+  ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
   if (ret) {
     DRM_ERROR("pushing to VRAM failed\n");
     return ret;
   }
   return 0;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,14 +1,15 @@
 int vbox_bo_unpin(struct vbox_bo *bo) {
+  struct ttm_operation_ctx ctx = {false, false};
   int i, ret;
   if (!bo->pin_count) {
     DRM_ERROR("unpin bad %p\n", bo);
     return 0;
   }
   bo->pin_count--;
   if (bo->pin_count) return 0;
   for (i = 0; i < bo->placement.num_placement; i++)
     bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
-  ret = ttm_bo_validate(&bo->bo, &bo->placement, false, false);
+  ret = ttm_bo_validate(&bo->bo, &bo->placement, &ctx);
   if (ret) return ret;
   return 0;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,30 +1,30 @@
 static struct drm_i915_gem_object *vgpu_create_gem(struct drm_device *dev, struct intel_vgpu_fb_info *info) {
   struct drm_i915_private *dev_priv = to_i915(dev);
   struct drm_i915_gem_object *obj;
   obj = i915_gem_object_alloc(dev_priv);
   if (obj == NULL) return NULL;
   drm_gem_private_object_init(dev, &obj->base, info->size << PAGE_SHIFT);
   i915_gem_object_init(obj, &intel_vgpu_gem_ops);
-  obj->base.read_domains = I915_GEM_DOMAIN_GTT;
-  obj->base.write_domain = 0;
+  obj->read_domains = I915_GEM_DOMAIN_GTT;
+  obj->write_domain = 0;
   if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
     unsigned int tiling_mode = 0;
     unsigned int stride = 0;
     switch (info->drm_format_mod << 10) {
     case PLANE_CTL_TILED_LINEAR: tiling_mode = I915_TILING_NONE; break;
     case PLANE_CTL_TILED_X:
       tiling_mode = I915_TILING_X;
       stride = info->stride;
       break;
     case PLANE_CTL_TILED_Y:
       tiling_mode = I915_TILING_Y;
       stride = info->stride;
       break;
     default: gvt_dbg_core("not supported tiling mode\n");
     }
     obj->tiling_and_stride = tiling_mode | stride;
   } else {
     obj->tiling_and_stride = info->drm_format_mod ? I915_TILING_X : 0;
   }
   return obj;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,18 +1,18 @@
 struct drm_i915_gem_object *huge_gem_object(struct drm_i915_private *i915, phys_addr_t phys_size, dma_addr_t dma_size) {
   struct drm_i915_gem_object *obj;
   unsigned int cache_level;
   GEM_BUG_ON(!phys_size || phys_size > dma_size);
   GEM_BUG_ON(!IS_ALIGNED(phys_size, PAGE_SIZE));
   GEM_BUG_ON(!IS_ALIGNED(dma_size, I915_GTT_PAGE_SIZE));
   if (overflows_type(dma_size, obj->base.size)) return ERR_PTR(-E2BIG);
   obj = i915_gem_object_alloc(i915);
   if (!obj) return ERR_PTR(-ENOMEM);
   drm_gem_private_object_init(&i915->drm, &obj->base, dma_size);
   i915_gem_object_init(obj, &huge_ops);
-  obj->base.read_domains = I915_GEM_DOMAIN_CPU;
-  obj->base.write_domain = I915_GEM_DOMAIN_CPU;
+  obj->read_domains = I915_GEM_DOMAIN_CPU;
+  obj->write_domain = I915_GEM_DOMAIN_CPU;
   cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE;
   i915_gem_object_set_cache_coherency(obj, cache_level);
   obj->scratch = phys_size;
   return obj;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,18 +1,18 @@
 static struct drm_i915_gem_object *fake_huge_pages_object(struct drm_i915_private *i915, u64 size, bool single) {
   struct drm_i915_gem_object *obj;
   GEM_BUG_ON(!size);
   GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
   if (size >> PAGE_SHIFT > UINT_MAX) return ERR_PTR(-E2BIG);
   if (overflows_type(size, obj->base.size)) return ERR_PTR(-E2BIG);
   obj = i915_gem_object_alloc(i915);
   if (!obj) return ERR_PTR(-ENOMEM);
   drm_gem_private_object_init(&i915->drm, &obj->base, size);
   if (single)
     i915_gem_object_init(obj, &fake_ops_single);
   else
     i915_gem_object_init(obj, &fake_ops);
-  obj->base.write_domain = I915_GEM_DOMAIN_CPU;
-  obj->base.read_domains = I915_GEM_DOMAIN_CPU;
+  obj->write_domain = I915_GEM_DOMAIN_CPU;
+  obj->read_domains = I915_GEM_DOMAIN_CPU;
   obj->cache_level = I915_CACHE_NONE;
   return obj;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,16 +1,16 @@
 static struct drm_i915_gem_object *huge_pages_object(struct drm_i915_private *i915, u64 size, unsigned int page_mask) {
   struct drm_i915_gem_object *obj;
   GEM_BUG_ON(!size);
   GEM_BUG_ON(!IS_ALIGNED(size, BIT(__ffs(page_mask))));
   if (size >> PAGE_SHIFT > INT_MAX) return ERR_PTR(-E2BIG);
   if (overflows_type(size, obj->base.size)) return ERR_PTR(-E2BIG);
   obj = i915_gem_object_alloc(i915);
   if (!obj) return ERR_PTR(-ENOMEM);
   drm_gem_private_object_init(&i915->drm, &obj->base, size);
   i915_gem_object_init(obj, &huge_page_ops);
-  obj->base.write_domain = I915_GEM_DOMAIN_CPU;
-  obj->base.read_domains = I915_GEM_DOMAIN_CPU;
+  obj->write_domain = I915_GEM_DOMAIN_CPU;
+  obj->read_domains = I915_GEM_DOMAIN_CPU;
   obj->cache_level = I915_CACHE_NONE;
   obj->mm.page_mask = page_mask;
   return obj;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,34 +1,34 @@
 static void describe_obj(struct seq_file *m, struct drm_i915_gem_object *obj) {
   struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
   struct intel_engine_cs *engine;
   struct i915_vma *vma;
   unsigned int frontbuffer_bits;
   int pin_count = 0;
   lockdep_assert_held(&obj->base.dev->struct_mutex);
-  seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", &obj->base, get_active_flag(obj), get_pin_flag(obj), get_tiling_flag(obj), get_global_flag(obj), get_pin_mapped_flag(obj), obj->base.size / 1024, obj->base.read_domains, obj->base.write_domain, i915_cache_level_str(dev_priv, obj->cache_level), obj->mm.dirty ? " dirty" : "", obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
+  seq_printf(m, "%pK: %c%c%c%c%c %8zdKiB %02x %02x %s%s%s", &obj->base, get_active_flag(obj), get_pin_flag(obj), get_tiling_flag(obj), get_global_flag(obj), get_pin_mapped_flag(obj), obj->base.size / 1024, obj->read_domains, obj->write_domain, i915_cache_level_str(dev_priv, obj->cache_level), obj->mm.dirty ? " dirty" : "", obj->mm.madv == I915_MADV_DONTNEED ? " purgeable" : "");
   if (obj->base.name) seq_printf(m, " (name: %d)", obj->base.name);
   list_for_each_entry(vma, &obj->vma_list, obj_link) {
     if (i915_vma_is_pinned(vma)) pin_count++;
   }
   seq_printf(m, " (pinned x %d)", pin_count);
   if (obj->pin_global) seq_printf(m, " (global)");
   list_for_each_entry(vma, &obj->vma_list, obj_link) {
     if (!drm_mm_node_allocated(&vma->node)) continue;
     seq_printf(m, " (%sgtt offset: %08llx, size: %08llx, pages: %s", i915_vma_is_ggtt(vma) ? "g" : "pp", vma->node.start, vma->node.size, stringify_page_sizes(vma->page_sizes.gtt, NULL, 0));
     if (i915_vma_is_ggtt(vma)) {
       switch (vma->ggtt_view.type) {
       case I915_GGTT_VIEW_NORMAL: seq_puts(m, ", normal"); break;
       case I915_GGTT_VIEW_PARTIAL: seq_printf(m, ", partial [%08llx+%x]", vma->ggtt_view.partial.offset << PAGE_SHIFT, vma->ggtt_view.partial.size << PAGE_SHIFT); break;
       case I915_GGTT_VIEW_ROTATED: seq_printf(m, ", rotated [(%ux%u, stride=%u, offset=%u), (%ux%u, stride=%u, offset=%u)]", vma->ggtt_view.rotated.plane[0].width, vma->ggtt_view.rotated.plane[0].height, vma->ggtt_view.rotated.plane[0].stride, vma->ggtt_view.rotated.plane[0].offset, vma->ggtt_view.rotated.plane[1].width, vma->ggtt_view.rotated.plane[1].height, vma->ggtt_view.rotated.plane[1].stride, vma->ggtt_view.rotated.plane[1].offset); break;
       default: MISSING_CASE(vma->ggtt_view.type); break;
       }
     }
     if (vma->fence) seq_printf(m, " , fence: %d%s", vma->fence->id, i915_gem_active_isset(&vma->last_fence) ? "*" : "");
     seq_puts(m, ")");
   }
   if (obj->stolen) seq_printf(m, " (stolen: %08llx)", obj->stolen->start);
   engine = i915_gem_object_last_write_engine(obj);
   if (engine) seq_printf(m, " (%s)", engine->name);
   frontbuffer_bits = atomic_read(&obj->frontbuffer_bits);
   if (frontbuffer_bits) seq_printf(m, " (frontbuffer: 0x%03x)", frontbuffer_bits);
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,9 +1,9 @@
 static void __i915_gem_object_flush_for_display(struct drm_i915_gem_object *obj) {
   /*
    * We manually flush the CPU domain so that we can override and
    * force the flush for the display, and perform it asyncrhonously.
    */
   flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
   if (obj->cache_dirty) i915_gem_clflush_object(obj, I915_CLFLUSH_FORCE);
-  obj->base.write_domain = 0;
+  obj->write_domain = 0;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,6 +1,6 @@
 static void __i915_gem_object_release_shmem(struct drm_i915_gem_object *obj, struct sg_table *pages, bool needs_clflush) {
   GEM_BUG_ON(obj->mm.madv == __I915_MADV_PURGED);
   if (obj->mm.madv == I915_MADV_DONTNEED) obj->mm.dirty = false;
-  if (needs_clflush && (obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0 && !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) drm_clflush_sg(pages);
+  if (needs_clflush && (obj->read_domains & I915_GEM_DOMAIN_CPU) == 0 && !(obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ)) drm_clflush_sg(pages);
   __start_cpu_write(obj);
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains
--- initial
+++ final
@@ -1,5 +1,5 @@
 static void __start_cpu_write(struct drm_i915_gem_object *obj) {
-  obj->base.read_domains = I915_GEM_DOMAIN_CPU;
-  obj->base.write_domain = I915_GEM_DOMAIN_CPU;
+  obj->read_domains = I915_GEM_DOMAIN_CPU;
+  obj->write_domain = I915_GEM_DOMAIN_CPU;
   if (cpu_write_needs_clflush(obj)) obj->cache_dirty = true;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,45 +1,45 @@
 bool i915_gem_clflush_object(struct drm_i915_gem_object *obj, unsigned int flags) {
   struct clflush *clflush;
   /*
    * Stolen memory is always coherent with the GPU as it is explicitly
    * marked as wc by the system, or the system is cache-coherent.
    * Similarly, we only access struct pages through the CPU cache, so
    * anything not backed by physical memory we consider to be always
    * coherent and not need clflushing.
    */
   if (!i915_gem_object_has_struct_page(obj)) {
     obj->cache_dirty = false;
     return false;
   }
   /* If the GPU is snooping the contents of the CPU cache,
    * we do not need to manually clear the CPU cache lines.  However,
    * the caches are only snooped when the render cache is
    * flushed/invalidated.  As we always have to emit invalidations
    * and flushes when moving into and out of the RENDER domain, correct
    * snooping behaviour occurs naturally as the result of our domain
    * tracking.
    */
   if (!(flags & I915_CLFLUSH_FORCE) && obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ) return false;
   trace_i915_gem_object_clflush(obj);
   clflush = NULL;
   if (!(flags & I915_CLFLUSH_SYNC)) clflush = kmalloc(sizeof(*clflush), GFP_KERNEL);
   if (clflush) {
     GEM_BUG_ON(!obj->cache_dirty);
     dma_fence_init(&clflush->dma, &i915_clflush_ops, &clflush_lock, to_i915(obj->base.dev)->mm.unordered_timeline, 0);
     i915_sw_fence_init(&clflush->wait, i915_clflush_notify);
     clflush->obj = i915_gem_object_get(obj);
     INIT_WORK(&clflush->work, i915_clflush_work);
     dma_fence_get(&clflush->dma);
     i915_sw_fence_await_reservation(&clflush->wait, obj->resv, NULL, true, I915_FENCE_TIMEOUT, I915_FENCE_GFP);
     reservation_object_lock(obj->resv, NULL);
     reservation_object_add_excl_fence(obj->resv, &clflush->dma);
     reservation_object_unlock(obj->resv);
     i915_sw_fence_commit(&clflush->wait);
   } else if (obj->mm.pages) {
     __i915_do_clflush(obj);
   } else {
-    GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);
+    GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU);
   }
   obj->cache_dirty = false;
   return true;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,19 +1,19 @@
 static int cpu_fill(struct drm_i915_gem_object *obj, u32 value) {
   const bool has_llc = HAS_LLC(to_i915(obj->base.dev));
   unsigned int n, m, need_flush;
   int err;
   err = i915_gem_obj_prepare_shmem_write(obj, &need_flush);
   if (err) return err;
   for (n = 0; n < real_page_count(obj); n++) {
     u32 *map;
     map = kmap_atomic(i915_gem_object_get_page(obj, n));
     for (m = 0; m < DW_PER_PAGE; m++)
       map[m] = value;
     if (!has_llc) drm_clflush_virt_range(map, PAGE_SIZE);
     kunmap_atomic(map);
   }
   i915_gem_obj_finish_shmem_access(obj);
-  obj->base.read_domains = I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU;
-  obj->base.write_domain = 0;
+  obj->read_domains = I915_GEM_DOMAIN_GTT | I915_GEM_DOMAIN_CPU;
+  obj->write_domain = 0;
   return 0;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,44 +1,44 @@
 struct drm_gem_object *i915_gem_prime_import(struct drm_device *dev, struct dma_buf *dma_buf) {
   struct dma_buf_attachment *attach;
   struct drm_i915_gem_object *obj;
   int ret;
   /* is this one of own objects? */
   if (dma_buf->ops == &i915_dmabuf_ops) {
     obj = dma_buf_to_obj(dma_buf);
     /* is it from our device? */
     if (obj->base.dev == dev) {
       /*
        * Importing dmabuf exported from out own gem increases
        * refcount on gem itself instead of f_count of dmabuf.
        */
       return &i915_gem_object_get(obj)->base;
     }
   }
   /* need to attach */
   attach = dma_buf_attach(dma_buf, dev->dev);
   if (IS_ERR(attach)) return ERR_CAST(attach);
   get_dma_buf(dma_buf);
   obj = i915_gem_object_alloc(to_i915(dev));
   if (obj == NULL) {
     ret = -ENOMEM;
     goto fail_detach;
   }
   drm_gem_private_object_init(dev, &obj->base, dma_buf->size);
   i915_gem_object_init(obj, &i915_gem_object_dmabuf_ops);
   obj->base.import_attach = attach;
   obj->resv = dma_buf->resv;
   /* We use GTT as shorthand for a coherent domain, one that is
    * neither in the GPU cache nor in the CPU cache, where all
    * writes are immediately visible in memory. (That's not strictly
    * true, but it's close! There are internal buffers such as the
    * write-combined buffer or a delay through the chipset for GTT
    * writes that do require us to treat GTT as a separate cache domain.)
    */
-  obj->base.read_domains = I915_GEM_DOMAIN_GTT;
-  obj->base.write_domain = 0;
+  obj->read_domains = I915_GEM_DOMAIN_GTT;
+  obj->write_domain = 0;
   return &obj->base;
 fail_detach:
   dma_buf_detach(dma_buf, attach);
   dma_buf_put(dma_buf);
   return ERR_PTR(ret);
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,55 +1,55 @@
 static int __reloc_gpu_alloc(struct i915_execbuffer *eb, struct i915_vma *vma, unsigned int len) {
   struct reloc_cache *cache = &eb->reloc_cache;
   struct drm_i915_gem_object *obj;
   struct drm_i915_gem_request *rq;
   struct i915_vma *batch;
   u32 *cmd;
   int err;
-  GEM_BUG_ON(vma->obj->base.write_domain & I915_GEM_DOMAIN_CPU);
+  GEM_BUG_ON(vma->obj->write_domain & I915_GEM_DOMAIN_CPU);
   obj = i915_gem_batch_pool_get(&eb->engine->batch_pool, PAGE_SIZE);
   if (IS_ERR(obj)) return PTR_ERR(obj);
   cmd = i915_gem_object_pin_map(obj, cache->has_llc ? I915_MAP_FORCE_WB : I915_MAP_FORCE_WC);
   i915_gem_object_unpin_pages(obj);
   if (IS_ERR(cmd)) return PTR_ERR(cmd);
   err = i915_gem_object_set_to_wc_domain(obj, false);
   if (err) goto err_unmap;
   batch = i915_vma_instance(obj, vma->vm, NULL);
   if (IS_ERR(batch)) {
     err = PTR_ERR(batch);
     goto err_unmap;
   }
   err = i915_vma_pin(batch, 0, 0, PIN_USER | PIN_NONBLOCK);
   if (err) goto err_unmap;
   rq = i915_gem_request_alloc(eb->engine, eb->ctx);
   if (IS_ERR(rq)) {
     err = PTR_ERR(rq);
     goto err_unpin;
   }
   err = i915_gem_request_await_object(rq, vma->obj, true);
   if (err) goto err_request;
   err = eb->engine->emit_bb_start(rq, batch->node.start, PAGE_SIZE, cache->gen > 5 ? 0 : I915_DISPATCH_SECURE);
   if (err) goto err_request;
   GEM_BUG_ON(!reservation_object_test_signaled_rcu(batch->resv, true));
   i915_vma_move_to_active(batch, rq, 0);
   reservation_object_lock(batch->resv, NULL);
   reservation_object_add_excl_fence(batch->resv, &rq->fence);
   reservation_object_unlock(batch->resv);
   i915_vma_unpin(batch);
   i915_vma_move_to_active(vma, rq, EXEC_OBJECT_WRITE);
   reservation_object_lock(vma->resv, NULL);
   reservation_object_add_excl_fence(vma->resv, &rq->fence);
   reservation_object_unlock(vma->resv);
   rq->batch = batch;
   cache->rq = rq;
   cache->rq_cmd = cmd;
   cache->rq_size = 0;
   /* Return with batch mapping (cmd) still pinned */
   return 0;
 err_request:
   i915_add_request(rq);
 err_unpin:
   i915_vma_unpin(batch);
 err_unmap:
   i915_gem_object_unpin_map(obj);
   return err;
 }<sep>@@
struct i915_vma *vma;
@@
- vma->obj->base.write_domain
+ vma->obj->write_domain
--- initial
+++ final
@@ -1,26 +1,26 @@
 void i915_vma_move_to_active(struct i915_vma *vma, struct drm_i915_gem_request *req, unsigned int flags) {
   struct drm_i915_gem_object *obj = vma->obj;
   const unsigned int idx = req->engine->id;
   lockdep_assert_held(&req->i915->drm.struct_mutex);
   GEM_BUG_ON(!drm_mm_node_allocated(&vma->node));
   /*
    * Add a reference if we're newly entering the active list.
    * The order in which we add operations to the retirement queue is
    * vital here: mark_active adds to the start of the callback list,
    * such that subsequent callbacks are called first. Therefore we
    * add the active reference first and queue for it to be dropped
    * *last*.
    */
   if (!i915_vma_is_active(vma)) obj->active_count++;
   i915_vma_set_active(vma, idx);
   i915_gem_active_set(&vma->last_read[idx], req);
   list_move_tail(&vma->vm_link, &vma->vm->active_list);
-  obj->base.write_domain = 0;
+  obj->write_domain = 0;
   if (flags & EXEC_OBJECT_WRITE) {
-    obj->base.write_domain = I915_GEM_DOMAIN_RENDER;
+    obj->write_domain = I915_GEM_DOMAIN_RENDER;
     if (intel_fb_obj_invalidate(obj, ORIGIN_CS)) i915_gem_active_set(&obj->frontbuffer_write, req);
-    obj->base.read_domains = 0;
+    obj->read_domains = 0;
   }
-  obj->base.read_domains |= I915_GEM_GPU_DOMAINS;
+  obj->read_domains |= I915_GEM_GPU_DOMAINS;
   if (flags & EXEC_OBJECT_NEEDS_FENCE) i915_gem_active_set(&vma->last_fence, req);
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,20 +1,20 @@
 static void flush_write_domain(struct drm_i915_gem_object *obj, unsigned int flush_domains) {
   struct drm_i915_private *dev_priv = to_i915(obj->base.dev);
   struct i915_vma *vma;
-  if (!(obj->base.write_domain & flush_domains)) return;
-  switch (obj->base.write_domain) {
+  if (!(obj->write_domain & flush_domains)) return;
+  switch (obj->write_domain) {
   case I915_GEM_DOMAIN_GTT:
     i915_gem_flush_ggtt_writes(dev_priv);
     intel_fb_obj_flush(obj, fb_write_origin(obj, I915_GEM_DOMAIN_GTT));
     for_each_ggtt_vma(vma, obj) {
       if (vma->iomap) continue;
       i915_vma_unset_ggtt_write(vma);
     }
     break;
   case I915_GEM_DOMAIN_CPU: i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC); break;
   case I915_GEM_DOMAIN_RENDER:
     if (gpu_write_needs_clflush(obj)) obj->cache_dirty = true;
     break;
   }
-  obj->base.write_domain = 0;
+  obj->write_domain = 0;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain