imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,71 +1,65 @@
 static int plgpio_probe(struct platform_device *pdev) {
   struct plgpio *plgpio;
   struct resource *res;
   int ret, irq;
   plgpio = devm_kzalloc(&pdev->dev, sizeof(*plgpio), GFP_KERNEL);
-  if (!plgpio) {
-    dev_err(&pdev->dev, "memory allocation fail\n");
-    return -ENOMEM;
-  }
+  if (!plgpio) return -ENOMEM;
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   plgpio->base = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(plgpio->base)) return PTR_ERR(plgpio->base);
   ret = plgpio_probe_dt(pdev, plgpio);
   if (ret) {
     dev_err(&pdev->dev, "DT probe failed\n");
     return ret;
   }
   plgpio->clk = devm_clk_get(&pdev->dev, NULL);
   if (IS_ERR(plgpio->clk)) dev_warn(&pdev->dev, "clk_get() failed, work without it\n");
 #ifdef CONFIG_PM_SLEEP
   plgpio->csave_regs = devm_kzalloc(&pdev->dev, sizeof(*plgpio->csave_regs) * DIV_ROUND_UP(plgpio->chip.ngpio, MAX_GPIO_PER_REG), GFP_KERNEL);
-  if (!plgpio->csave_regs) {
-    dev_err(&pdev->dev, "csave registers memory allocation fail\n");
-    return -ENOMEM;
-  }
+  if (!plgpio->csave_regs) return -ENOMEM;
 #endif
   platform_set_drvdata(pdev, plgpio);
   spin_lock_init(&plgpio->lock);
   plgpio->chip.base = -1;
   plgpio->chip.request = plgpio_request;
   plgpio->chip.free = plgpio_free;
   plgpio->chip.direction_input = plgpio_direction_input;
   plgpio->chip.direction_output = plgpio_direction_output;
   plgpio->chip.get = plgpio_get_value;
   plgpio->chip.set = plgpio_set_value;
   plgpio->chip.label = dev_name(&pdev->dev);
   plgpio->chip.parent = &pdev->dev;
   plgpio->chip.owner = THIS_MODULE;
   plgpio->chip.of_node = pdev->dev.of_node;
   if (!IS_ERR(plgpio->clk)) {
     ret = clk_prepare(plgpio->clk);
     if (ret) {
       dev_err(&pdev->dev, "clk prepare failed\n");
       return ret;
     }
   }
   ret = gpiochip_add_data(&plgpio->chip, plgpio);
   if (ret) {
     dev_err(&pdev->dev, "unable to add gpio chip\n");
     goto unprepare_clk;
   }
   irq = platform_get_irq(pdev, 0);
   if (irq < 0) {
     dev_info(&pdev->dev, "PLGPIO registered without IRQs\n");
     return 0;
   }
   ret = gpiochip_irqchip_add(&plgpio->chip, &plgpio_irqchip, 0, handle_simple_irq, IRQ_TYPE_NONE);
   if (ret) {
     dev_err(&pdev->dev, "failed to add irqchip to gpiochip\n");
     goto remove_gpiochip;
   }
   gpiochip_set_chained_irqchip(&plgpio->chip, &plgpio_irqchip, irq, plgpio_irq_handler);
   dev_info(&pdev->dev, "PLGPIO registered with IRQs\n");
   return 0;
 remove_gpiochip:
   dev_info(&pdev->dev, "Remove gpiochip\n");
   gpiochip_remove(&plgpio->chip);
 unprepare_clk:
   if (!IS_ERR(plgpio->clk)) clk_unprepare(plgpio->clk);
   return ret;
 }<sep>@@
expression x;
identifier f;
constant char[] c;
statement S1,S2;
@@

x = \(kmalloc\|kcalloc\|kzalloc\|devm_kmalloc\|devm_kcalloc\|devm_kzalloc
	\|kmemdup\|kmem_cache_alloc\|kmem_cache_zalloc
	\|rhashtable_lookup_fast\)
      (...);
if (x == NULL)
- {
- f(...,c,...);
  S1
- }
 else S2
--- initial
+++ final
@@ -1,35 +1,32 @@
 static int i40e_init_interrupt_scheme(struct i40e_pf *pf) {
   int vectors = 0;
   ssize_t size;
   if (pf->flags & I40E_FLAG_MSIX_ENABLED) {
     vectors = i40e_init_msix(pf);
     if (vectors < 0) {
       pf->flags &= ~(I40E_FLAG_MSIX_ENABLED | I40E_FLAG_IWARP_ENABLED | I40E_FLAG_RSS_ENABLED | I40E_FLAG_DCB_CAPABLE | I40E_FLAG_DCB_ENABLED | I40E_FLAG_SRIOV_ENABLED | I40E_FLAG_FD_SB_ENABLED | I40E_FLAG_FD_ATR_ENABLED | I40E_FLAG_VMDQ_ENABLED);
       pf->flags |= I40E_FLAG_FD_SB_INACTIVE;
       /* rework the queue expectations without MSIX */
       i40e_determine_queue_usage(pf);
     }
   }
   if (!(pf->flags & I40E_FLAG_MSIX_ENABLED) && (pf->flags & I40E_FLAG_MSI_ENABLED)) {
     dev_info(&pf->pdev->dev, "MSI-X not available, trying MSI\n");
     vectors = pci_enable_msi(pf->pdev);
     if (vectors < 0) {
       dev_info(&pf->pdev->dev, "MSI init failed - %d\n", vectors);
       pf->flags &= ~I40E_FLAG_MSI_ENABLED;
     }
     vectors = 1; /* one MSI or Legacy vector */
   }
   if (!(pf->flags & (I40E_FLAG_MSIX_ENABLED | I40E_FLAG_MSI_ENABLED))) dev_info(&pf->pdev->dev, "MSI-X and MSI not available, falling back to Legacy IRQ\n");
   /* set up vector assignment tracking */
   size = sizeof(struct i40e_lump_tracking) + (sizeof(u16) * vectors);
   pf->irq_pile = kzalloc(size, GFP_KERNEL);
-  if (!pf->irq_pile) {
-    dev_err(&pf->pdev->dev, "error allocating irq_pile memory\n");
-    return -ENOMEM;
-  }
+  if (!pf->irq_pile) return -ENOMEM;
   pf->irq_pile->num_entries = vectors;
   pf->irq_pile->search_hint = 0;
   /* track first vector for misc interrupts, ignore return */
   (void)i40e_get_lump(pf, pf->irq_pile, 1, I40E_PILE_VALID_BIT - 1);
   return 0;
 }<sep>@@
expression x;
identifier f;
constant char[] c;
statement S1,S2;
@@

x = \(kmalloc\|kcalloc\|kzalloc\|devm_kmalloc\|devm_kcalloc\|devm_kzalloc
	\|kmemdup\|kmem_cache_alloc\|kmem_cache_zalloc
	\|rhashtable_lookup_fast\)
      (...);
if (x == NULL)
- {
- f(...,c,...);
  S1
- }
 else S2
--- initial
+++ final
@@ -1,65 +1,62 @@
 void acpiphp_enumerate_slots(struct pci_bus *bus) {
   struct acpiphp_bridge *bridge;
   struct acpi_device *adev;
   acpi_handle handle;
   acpi_status status;
   if (acpiphp_disabled) return;
   adev = ACPI_COMPANION(bus->bridge);
   if (!adev) return;
   handle = adev->handle;
   bridge = kzalloc(sizeof(struct acpiphp_bridge), GFP_KERNEL);
-  if (!bridge) {
-    acpi_handle_err(handle, "No memory for bridge object\n");
-    return;
-  }
+  if (!bridge) return;
   INIT_LIST_HEAD(&bridge->slots);
   kref_init(&bridge->ref);
   bridge->pci_dev = pci_dev_get(bus->self);
   bridge->pci_bus = bus;
   /*
    * Grab a ref to the subordinate PCI bus in case the bus is
    * removed via PCI core logical hotplug. The ref pins the bus
    * (which we access during module unload).
    */
   get_device(&bus->dev);
   acpi_lock_hp_context();
   if (pci_is_root_bus(bridge->pci_bus)) {
     struct acpiphp_root_context *root_context;
     root_context = kzalloc(sizeof(*root_context), GFP_KERNEL);
     if (!root_context) goto err;
     root_context->root_bridge = bridge;
     acpi_set_hp_context(adev, &root_context->hp);
   } else {
     struct acpiphp_context *context;
     /*
      * This bridge should have been registered as a hotplug function
      * under its parent, so the context should be there, unless the
      * parent is going to be handled by pciehp, in which case this
      * bridge is not interesting to us either.
      */
     context = acpiphp_get_context(adev);
     if (!context) goto err;
     bridge->context = context;
     context->bridge = bridge;
     /* Get a reference to the parent bridge. */
     get_bridge(context->func.parent);
   }
   acpi_unlock_hp_context();
   /* Must be added to the list prior to calling acpiphp_add_context(). */
   mutex_lock(&bridge_mutex);
   list_add(&bridge->list, &bridge_list);
   mutex_unlock(&bridge_mutex);
   /* register all slot objects under this bridge */
   status = acpi_walk_namespace(ACPI_TYPE_DEVICE, handle, 1, acpiphp_add_context, NULL, bridge, NULL);
   if (ACPI_FAILURE(status)) {
     acpi_handle_err(handle, "failed to register slots\n");
     cleanup_bridge(bridge);
     put_bridge(bridge);
   }
   return;
 err:
   acpi_unlock_hp_context();
   put_device(&bus->dev);
   pci_dev_put(bridge->pci_dev);
   kfree(bridge);
 }<sep>@@
expression x;
identifier f;
constant char[] c;
statement S1,S2;
@@

x = \(kmalloc\|kcalloc\|kzalloc\|devm_kmalloc\|devm_kcalloc\|devm_kzalloc
	\|kmemdup\|kmem_cache_alloc\|kmem_cache_zalloc
	\|rhashtable_lookup_fast\)
      (...);
if (x == NULL)
- {
- f(...,c,...);
  S1
- }
 else S2
--- initial
+++ final
@@ -1,18 +1,15 @@
 static struct resource_node *__init alloc_resources(struct ebda_pci_rsrc *curr) {
   struct resource_node *rs;
   if (!curr) {
     err("NULL passed to allocate\n");
     return NULL;
   }
   rs = kzalloc(sizeof(struct resource_node), GFP_KERNEL);
-  if (!rs) {
-    err("out of system memory\n");
-    return NULL;
-  }
+  if (!rs) return NULL;
   rs->busno = curr->bus_num;
   rs->devfunc = curr->dev_fun;
   rs->start = curr->start_addr;
   rs->end = curr->end_addr;
   rs->len = curr->end_addr - curr->start_addr + 1;
   return rs;
 }<sep>@@
expression x;
identifier f;
constant char[] c;
statement S1,S2;
@@

x = \(kmalloc\|kcalloc\|kzalloc\|devm_kmalloc\|devm_kcalloc\|devm_kzalloc
	\|kmemdup\|kmem_cache_alloc\|kmem_cache_zalloc
	\|rhashtable_lookup_fast\)
      (...);
if (x == NULL)
- {
- f(...,c,...);
  S1
- }
 else S2
--- initial
+++ final
@@ -1,60 +1,57 @@
 static struct se_wwn *tcm_loop_make_scsi_hba(struct target_fabric_configfs *tf, struct config_group *group, const char *name) {
   struct tcm_loop_hba *tl_hba;
   struct Scsi_Host *sh;
   char *ptr;
   int ret, off = 0;
   tl_hba = kzalloc(sizeof(struct tcm_loop_hba), GFP_KERNEL);
-  if (!tl_hba) {
-    pr_err("Unable to allocate struct tcm_loop_hba\n");
-    return ERR_PTR(-ENOMEM);
-  }
+  if (!tl_hba) return ERR_PTR(-ENOMEM);
   /*
    * Determine the emulated Protocol Identifier and Target Port Name
    * based on the incoming configfs directory name.
    */
   ptr = strstr(name, "naa.");
   if (ptr) {
     tl_hba->tl_proto_id = SCSI_PROTOCOL_SAS;
     goto check_len;
   }
   ptr = strstr(name, "fc.");
   if (ptr) {
     tl_hba->tl_proto_id = SCSI_PROTOCOL_FCP;
     off = 3; /* Skip over "fc." */
     goto check_len;
   }
   ptr = strstr(name, "iqn.");
   if (!ptr) {
     pr_err("Unable to locate prefix for emulated Target "
            "Port: %s\n",
            name);
     ret = -EINVAL;
     goto out;
   }
   tl_hba->tl_proto_id = SCSI_PROTOCOL_ISCSI;
 check_len:
   if (strlen(name) >= TL_WWN_ADDR_LEN) {
     pr_err("Emulated NAA %s Address: %s, exceeds"
            " max: %d\n",
            name, tcm_loop_dump_proto_id(tl_hba), TL_WWN_ADDR_LEN);
     ret = -EINVAL;
     goto out;
   }
   snprintf(&tl_hba->tl_wwn_address[0], TL_WWN_ADDR_LEN, "%s", &name[off]);
   /*
    * Call device_register(tl_hba->dev) to register the emulated
    * Linux/SCSI LLD of type struct Scsi_Host at tl_hba->sh after
    * device_register() callbacks in tcm_loop_driver_probe()
    */
   ret = tcm_loop_setup_hba_bus(tl_hba, tcm_loop_hba_no_cnt);
   if (ret) goto out;
   sh = tl_hba->sh;
   tcm_loop_hba_no_cnt++;
   pr_debug("TCM_Loop_ConfigFS: Allocated emulated Target"
            " %s Address: %s at Linux/SCSI Host ID: %d\n",
            tcm_loop_dump_proto_id(tl_hba), name, sh->host_no);
   return &tl_hba->tl_hba_wwn;
 out:
   kfree(tl_hba);
   return ERR_PTR(ret);
 }<sep>@@
expression x;
identifier f;
constant char[] c;
statement S1,S2;
@@

x = \(kmalloc\|kcalloc\|kzalloc\|devm_kmalloc\|devm_kcalloc\|devm_kzalloc
	\|kmemdup\|kmem_cache_alloc\|kmem_cache_zalloc
	\|rhashtable_lookup_fast\)
      (...);
if (x == NULL)
- {
- f(...,c,...);
  S1
- }
 else S2
--- initial
+++ final
@@ -1,15 +1,12 @@
 static int wm8650_pinctrl_probe(struct platform_device *pdev) {
   struct wmt_pinctrl_data *data;
   data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
-  if (!data) {
-    dev_err(&pdev->dev, "failed to allocate data\n");
-    return -ENOMEM;
-  }
+  if (!data) return -ENOMEM;
   data->banks = wm8650_banks;
   data->nbanks = ARRAY_SIZE(wm8650_banks);
   data->pins = wm8650_pins;
   data->npins = ARRAY_SIZE(wm8650_pins);
   data->groups = wm8650_groups;
   data->ngroups = ARRAY_SIZE(wm8650_groups);
   return wmt_pinctrl_probe(pdev, data);
 }<sep>@@
expression x;
identifier f;
constant char[] c;
statement S1,S2;
@@

x = \(kmalloc\|kcalloc\|kzalloc\|devm_kmalloc\|devm_kcalloc\|devm_kzalloc
	\|kmemdup\|kmem_cache_alloc\|kmem_cache_zalloc
	\|rhashtable_lookup_fast\)
      (...);
if (x == NULL)
- {
- f(...,c,...);
  S1
- }
 else S2
--- initial
+++ final
@@ -1,6 +1,6 @@
 static int exynos_suspend(void) {
   if (read_cpuid_part() == ARM_CPU_PART_CORTEX_A9) exynos_save_cp15();
   writel(EXYNOS_SLEEP_MAGIC, sysram_ns_base_addr + EXYNOS_BOOT_FLAG);
-  writel(virt_to_phys(exynos_cpu_resume_ns), sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
+  writel(__pa_symbol(exynos_cpu_resume_ns), sysram_ns_base_addr + EXYNOS_BOOT_ADDR);
   return cpu_suspend(0, exynos_cpu_suspend);
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1 +1 @@
-void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr) { writel(virt_to_phys(boot_addr), pmsu_mp_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); }
+void mvebu_pmsu_set_cpu_boot_addr(int hw_cpu, void *boot_addr) { writel(__pa_symbol(boot_addr), pmsu_mp_base + PMSU_BOOT_ADDR_REDIRECT_OFFSET(hw_cpu)); }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,63 +1,63 @@
 static int exynos_boot_secondary(unsigned int cpu, struct task_struct *idle) {
   unsigned long timeout;
   u32 mpidr = cpu_logical_map(cpu);
   u32 core_id = MPIDR_AFFINITY_LEVEL(mpidr, 0);
   int ret = -ENOSYS;
   /*
    * Set synchronisation state between this boot processor
    * and the secondary one
    */
   spin_lock(&boot_lock);
   /*
    * The secondary processor is waiting to be released from
    * the holding pen - release it, then wait for it to flag
    * that it has been released by resetting pen_release.
    *
    * Note that "pen_release" is the hardware CPU core ID, whereas
    * "cpu" is Linux's internal ID.
    */
   write_pen_release(core_id);
   if (!exynos_cpu_power_state(core_id)) {
     exynos_cpu_power_up(core_id);
     timeout = 10;
     /* wait max 10 ms until cpu1 is on */
     while (exynos_cpu_power_state(core_id) != S5P_CORE_LOCAL_PWR_EN) {
       if (timeout-- == 0) break;
       mdelay(1);
     }
     if (timeout == 0) {
       printk(KERN_ERR "cpu1 power enable failed");
       spin_unlock(&boot_lock);
       return -ETIMEDOUT;
     }
   }
   exynos_core_restart(core_id);
   /*
    * Send the secondary CPU a soft interrupt, thereby causing
    * the boot monitor to read the system wide flags register,
    * and branch to the address found there.
    */
   timeout = jiffies + (1 * HZ);
   while (time_before(jiffies, timeout)) {
     unsigned long boot_addr;
     smp_rmb();
-    boot_addr = virt_to_phys(exynos4_secondary_startup);
+    boot_addr = __pa_symbol(exynos4_secondary_startup);
     ret = exynos_set_boot_addr(core_id, boot_addr);
     if (ret) goto fail;
     call_firmware_op(cpu_boot, core_id);
     if (soc_is_exynos3250())
       dsb_sev();
     else
       arch_send_wakeup_ipi_mask(cpumask_of(cpu));
     if (pen_release == -1) break;
     udelay(10);
   }
   if (pen_release != -1) ret = -ETIMEDOUT;
   /*
    * now the secondary core is starting up let it run its
    * calibrations, then wait for it to finish
    */
 fail:
   spin_unlock(&boot_lock);
   return pen_release != -1 ? ret : 0;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,35 +1,35 @@
 static int bcm63138_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) {
   void __iomem *bootlut_base;
   struct device_node *dn;
   int ret = 0;
   u32 val;
   dn = of_find_matching_node(NULL, bcm63138_bootlut_ids);
   if (!dn) {
     pr_err("SMP: unable to find bcm63138 boot LUT node\n");
     return -ENODEV;
   }
   bootlut_base = of_iomap(dn, 0);
   of_node_put(dn);
   if (!bootlut_base) {
     pr_err("SMP: unable to remap boot LUT base register\n");
     return -ENOMEM;
   }
   /* Locate the secondary CPU node */
   dn = of_get_cpu_node(cpu, NULL);
   if (!dn) {
     pr_err("SMP: failed to locate secondary CPU%d node\n", cpu);
     ret = -ENODEV;
     goto out;
   }
   /* Write the secondary init routine to the BootLUT reset vector */
-  val = virt_to_phys(secondary_startup);
+  val = __pa_symbol(secondary_startup);
   writel_relaxed(val, bootlut_base + BOOTLUT_RESET_VECT);
   /* Power up the core, will jump straight to its reset vector when we
    * return
    */
   ret = bcm63xx_pmb_power_on_cpu(dn);
   if (ret) goto out;
 out:
   iounmap(bootlut_base);
   return ret;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,20 +1,20 @@
 static int sun8i_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) {
   u32 reg;
   if (!(prcm_membase && cpucfg_membase)) return -EFAULT;
   spin_lock(&cpu_lock);
   /* Set CPU boot address */
-  writel(virt_to_phys(secondary_startup), cpucfg_membase + CPUCFG_PRIVATE0_REG);
+  writel(__pa_symbol(secondary_startup), cpucfg_membase + CPUCFG_PRIVATE0_REG);
   /* Assert the CPU core in reset */
   writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
   /* Assert the L1 cache in reset */
   reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
   writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
   /* Clear CPU power-off gating */
   reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
   writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
   mdelay(1);
   /* Deassert the CPU core reset */
   writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
   spin_unlock(&cpu_lock);
   return 0;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,9 +1,9 @@
 static void s3c2416_pm_prepare(void) {
   /*
    * write the magic value u-boot uses to check for resume into
    * the INFORM0 register, and ensure INFORM1 is set to the
    * correct address to resume from.
    */
   __raw_writel(0x2BED, S3C2412_INFORM0);
-  __raw_writel(virt_to_phys(s3c_cpu_resume), S3C2412_INFORM1);
+  __raw_writel(__pa_symbol(s3c_cpu_resume), S3C2412_INFORM1);
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,21 +1,21 @@
 static void s5pv210_pm_prepare(void) {
   unsigned int tmp;
   /* Set wake-up mask registers */
   __raw_writel(exynos_get_eint_wake_mask(), S5P_EINT_WAKEUP_MASK);
   __raw_writel(s5pv210_irqwake_intmask, S5P_WAKEUP_MASK);
   /* ensure at least INFORM0 has the resume address */
-  __raw_writel(virt_to_phys(s5pv210_cpu_resume), S5P_INFORM0);
+  __raw_writel(__pa_symbol(s5pv210_cpu_resume), S5P_INFORM0);
   tmp = __raw_readl(S5P_SLEEP_CFG);
   tmp &= ~(S5P_SLEEP_CFG_OSC_EN | S5P_SLEEP_CFG_USBOSC_EN);
   __raw_writel(tmp, S5P_SLEEP_CFG);
   /* WFI for SLEEP mode configuration by SYSCON */
   tmp = __raw_readl(S5P_PWR_CFG);
   tmp &= S5P_CFG_WFI_CLEAN;
   tmp |= S5P_CFG_WFI_SLEEP;
   __raw_writel(tmp, S5P_PWR_CFG);
   /* SYSCON interrupt handling disable */
   tmp = __raw_readl(S5P_OTHERS);
   tmp |= S5P_OTHER_SYSC_INTOFF;
   __raw_writel(tmp, S5P_OTHERS);
   s3c_pm_do_save(s5pv210_core_save, ARRAY_SIZE(s5pv210_core_save));
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,70 +1,70 @@
 static int exynos_cpu0_enter_aftr(void) {
   int ret = -1;
   /*
    * If the other cpu is powered on, we have to power it off, because
    * the AFTR state won't work otherwise
    */
   if (cpu_online(1)) {
     /*
      * We reach a sync point with the coupled idle state, we know
      * the other cpu will power down itself or will abort the
      * sequence, let's wait for one of these to happen
      */
     while (exynos_cpu_power_state(1)) {
       unsigned long boot_addr;
       /*
        * The other cpu may skip idle and boot back
        * up again
        */
       if (atomic_read(&cpu1_wakeup)) goto abort;
       /*
        * The other cpu may bounce through idle and
        * boot back up again, getting stuck in the
        * boot rom code
        */
       ret = exynos_get_boot_addr(1, &boot_addr);
       if (ret) goto fail;
       ret = -1;
       if (boot_addr == 0) goto abort;
       cpu_relax();
     }
   }
   exynos_enter_aftr();
   ret = 0;
 abort:
   if (cpu_online(1)) {
-    unsigned long boot_addr = virt_to_phys(exynos_cpu_resume);
+    unsigned long boot_addr = __pa_symbol(exynos_cpu_resume);
     /*
      * Set the boot vector to something non-zero
      */
     ret = exynos_set_boot_addr(1, boot_addr);
     if (ret) goto fail;
     dsb();
     /*
      * Turn on cpu1 and wait for it to be on
      */
     exynos_cpu_power_up(1);
     while (exynos_cpu_power_state(1) != S5P_CORE_LOCAL_PWR_EN)
       cpu_relax();
     if (soc_is_exynos3250()) {
       while (!pmu_raw_readl(S5P_PMU_SPARE2) && !atomic_read(&cpu1_wakeup))
         cpu_relax();
       if (!atomic_read(&cpu1_wakeup)) exynos_core_restart(1);
     }
     while (!atomic_read(&cpu1_wakeup)) {
       smp_rmb();
       /*
        * Poke cpu1 out of the boot rom
        */
       ret = exynos_set_boot_addr(1, boot_addr);
       if (ret) goto fail;
       call_firmware_op(cpu_boot, 1);
       if (soc_is_exynos3250())
         dsb_sev();
       else
         arch_send_wakeup_ipi_mask(cpumask_of(1));
     }
   }
 fail:
   return ret;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,11 +1,11 @@
 static void exynos3250_pm_prepare(void) {
   unsigned int tmp;
   /* Set wake-up mask registers */
   exynos_pm_set_wakeup_mask();
   tmp = pmu_raw_readl(EXYNOS3_ARM_L2_OPTION);
   tmp &= ~EXYNOS5_OPTION_USE_RETENTION;
   pmu_raw_writel(tmp, EXYNOS3_ARM_L2_OPTION);
   exynos_pm_enter_sleep_mode();
   /* ensure at least INFORM0 has the resume address */
-  pmu_raw_writel(virt_to_phys(exynos_cpu_resume), S5P_INFORM0);
+  pmu_raw_writel(__pa_symbol(exynos_cpu_resume), S5P_INFORM0);
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,5 +1,5 @@
 static int pxa25x_cpu_pm_prepare(void) {
   /* set resume return address */
-  PSPR = virt_to_phys(cpu_resume);
+  PSPR = __pa_symbol(cpu_resume);
   return 0;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,31 +1,31 @@
 static int sun6i_smp_boot_secondary(unsigned int cpu, struct task_struct *idle) {
   u32 reg;
   int i;
   if (!(prcm_membase && cpucfg_membase)) return -EFAULT;
   spin_lock(&cpu_lock);
   /* Set CPU boot address */
-  writel(virt_to_phys(secondary_startup), cpucfg_membase + CPUCFG_PRIVATE0_REG);
+  writel(__pa_symbol(secondary_startup), cpucfg_membase + CPUCFG_PRIVATE0_REG);
   /* Assert the CPU core in reset */
   writel(0, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
   /* Assert the L1 cache in reset */
   reg = readl(cpucfg_membase + CPUCFG_GEN_CTRL_REG);
   writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_GEN_CTRL_REG);
   /* Disable external debug access */
   reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
   writel(reg & ~BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
   /* Power up the CPU */
   for (i = 0; i <= 8; i++)
     writel(0xff >> i, prcm_membase + PRCM_CPU_PWR_CLAMP_REG(cpu));
   mdelay(10);
   /* Clear CPU power-off gating */
   reg = readl(prcm_membase + PRCM_CPU_PWROFF_REG);
   writel(reg & ~BIT(cpu), prcm_membase + PRCM_CPU_PWROFF_REG);
   mdelay(1);
   /* Deassert the CPU core reset */
   writel(3, cpucfg_membase + CPUCFG_CPU_RST_CTRL_REG(cpu));
   /* Enable back the external debug accesses */
   reg = readl(cpucfg_membase + CPUCFG_DBG_CTL1_REG);
   writel(reg | BIT(cpu), cpucfg_membase + CPUCFG_DBG_CTL1_REG);
   spin_unlock(&cpu_lock);
   return 0;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,5 +1,5 @@
 void mcpm_set_entry_vector(unsigned cpu, unsigned cluster, void *ptr) {
-  unsigned long val = ptr ? virt_to_phys(ptr) : 0;
+  unsigned long val = ptr ? __pa_symbol(ptr) : 0;
   mcpm_entry_vectors[cluster][cpu] = val;
   sync_cache_w(&mcpm_entry_vectors[cluster][cpu]);
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,9 +1,9 @@
 static int palmz72_pm_suspend(void) {
   /* setup the resume_info struct for the original bootloader */
   palmz72_resume_info.resume_addr = (u32)cpu_resume;
   /* Storing memory touched by ROM */
   store_ptr = *PALMZ72_SAVE_DWORD;
   /* Setting PSPR to a proper value */
-  PSPR = virt_to_phys(&palmz72_resume_info);
+  PSPR = __pa_symbol(&palmz72_resume_info);
   return 0;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)