--- initial
+++ final
@@ -1,100 +1,100 @@
 int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring, struct amdgpu_sync *sync, struct dma_fence *fence, struct amdgpu_job *job) {
   struct amdgpu_device *adev = ring->adev;
   unsigned vmhub = ring->funcs->vmhub;
   struct amdgpu_vmid_mgr *id_mgr = &adev->vm_manager.id_mgr[vmhub];
   uint64_t fence_context = adev->fence_context + ring->idx;
   struct dma_fence *updates = sync->last_vm_update;
   struct amdgpu_vmid *id, *idle;
   struct dma_fence **fences;
   unsigned i;
   int r = 0;
   mutex_lock(&id_mgr->lock);
   if (vm->reserved_vmid[vmhub]) {
     r = amdgpu_vmid_grab_reserved_locked(vm, ring, sync, fence, job);
     mutex_unlock(&id_mgr->lock);
     return r;
   }
   fences = kmalloc_array(sizeof(void *), id_mgr->num_ids, GFP_KERNEL);
   if (!fences) {
     mutex_unlock(&id_mgr->lock);
     return -ENOMEM;
   }
   /* Check if we have an idle VMID */
   i = 0;
   list_for_each_entry(idle, &id_mgr->ids_lru, list) {
     fences[i] = amdgpu_sync_peek_fence(&idle->active, ring);
     if (!fences[i]) break;
     ++i;
   }
   /* If we can't find a idle VMID to use, wait till one becomes available */
   if (&idle->list == &id_mgr->ids_lru) {
     u64 fence_context = adev->vm_manager.fence_context + ring->idx;
     unsigned seqno = ++adev->vm_manager.seqno[ring->idx];
     struct dma_fence_array *array;
     unsigned j;
     for (j = 0; j < i; ++j)
       dma_fence_get(fences[j]);
     array = dma_fence_array_create(i, fences, fence_context, seqno, true);
     if (!array) {
       for (j = 0; j < i; ++j)
         dma_fence_put(fences[j]);
       kfree(fences);
       r = -ENOMEM;
       goto error;
     }
     r = amdgpu_sync_fence(ring->adev, sync, &array->base, false);
     dma_fence_put(&array->base);
     if (r) goto error;
     mutex_unlock(&id_mgr->lock);
     return 0;
   }
   kfree(fences);
   job->vm_needs_flush = vm->use_cpu_for_update;
   /* Check if we can use a VMID already assigned to this VM */
   list_for_each_entry_reverse(id, &id_mgr->ids_lru, list) {
     struct dma_fence *flushed;
     bool needs_flush = vm->use_cpu_for_update;
     /* Check all the prerequisites to using this VMID */
     if (amdgpu_vmid_had_gpu_reset(adev, id)) continue;
     if (atomic64_read(&id->owner) != vm->client_id) continue;
     if (job->vm_pd_addr != id->pd_gpu_addr) continue;
     if (!id->last_flush || (id->last_flush->context != fence_context && !dma_fence_is_signaled(id->last_flush))) needs_flush = true;
     flushed = id->flushed_updates;
     if (updates && (!flushed || dma_fence_is_later(updates, flushed))) needs_flush = true;
     /* Concurrent flushes are only possible starting with Vega10 */
     if (adev->asic_type < CHIP_VEGA10 && needs_flush) continue;
     /* Good we can use this VMID. Remember this submission as
      * user of the VMID.
      */
     r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
     if (r) goto error;
     if (updates && (!flushed || dma_fence_is_later(updates, flushed))) {
       dma_fence_put(id->flushed_updates);
       id->flushed_updates = dma_fence_get(updates);
     }
     if (needs_flush)
       goto needs_flush;
     else
       goto no_flush_needed;
   };
   /* Still no ID to use? Then use the idle one found earlier */
   id = idle;
   /* Remember this submission as user of the VMID */
   r = amdgpu_sync_fence(ring->adev, &id->active, fence, false);
   if (r) goto error;
   id->pd_gpu_addr = job->vm_pd_addr;
   dma_fence_put(id->flushed_updates);
   id->flushed_updates = dma_fence_get(updates);
   atomic64_set(&id->owner, vm->client_id);
 needs_flush:
   job->vm_needs_flush = true;
   dma_fence_put(id->last_flush);
   id->last_flush = NULL;
 no_flush_needed:
   list_move_tail(&id->list, &id_mgr->ids_lru);
-  job->vm_id = id - id_mgr->ids;
+  job->vmid = id - id_mgr->ids;
   trace_amdgpu_vm_grab_id(vm, ring, job);
 error:
   mutex_unlock(&id_mgr->lock);
   return r;
 }<sep>@@
struct amdgpu_job x;
@@

 x.
-   vm_id
+   vmid