imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,64 +1,64 @@
 static int uvd_v7_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   struct drm_sched_rq *rq;
   int i, j, r;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
     /* UVD TRAP */
-    r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], 124, &adev->uvd.inst[j].irq);
+    r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst[j].irq);
     if (r) return r;
     /* UVD ENC TRAP */
     for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
-      r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + 119, &adev->uvd.inst[j].irq);
+      r = amdgpu_irq_add_id(adev, amdgpu_ih_clientid_uvds[j], i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst[j].irq);
       if (r) return r;
     }
   }
   r = amdgpu_uvd_sw_init(adev);
   if (r) return r;
   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
     const struct common_firmware_header *hdr;
     hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
     adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
     adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
     adev->firmware.fw_size += ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
     DRM_INFO("PSP loading UVD firmware\n");
   }
   for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
     ring = &adev->uvd.inst[j].ring_enc[0];
     rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
     r = drm_sched_entity_init(&ring->sched, &adev->uvd.inst[j].entity_enc, rq, NULL);
     if (r) {
       DRM_ERROR("(%d)Failed setting up UVD ENC run queue.\n", j);
       return r;
     }
   }
   r = amdgpu_uvd_resume(adev);
   if (r) return r;
   for (j = 0; j < adev->uvd.num_uvd_inst; j++) {
     if (!amdgpu_sriov_vf(adev)) {
       ring = &adev->uvd.inst[j].ring;
       sprintf(ring->name, "uvd<%d>", j);
       r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
       if (r) return r;
     }
     for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
       ring = &adev->uvd.inst[j].ring_enc[i];
       sprintf(ring->name, "uvd_enc%d<%d>", i, j);
       if (amdgpu_sriov_vf(adev)) {
         ring->use_doorbell = true;
         /* currently only use the first enconding ring for
          * sriov, so set unused location for other unused rings.
          */
         if (i == 0)
           ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
         else
           ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
       }
       r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst[j].irq, 0);
       if (r) return r;
     }
   }
   r = amdgpu_virt_alloc_mm_table(adev);
   if (r) return r;
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 119
+ VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP 
...+>,e3)
@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 124
+ VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE 
...+>,e3)
--- initial
+++ final
@@ -1,46 +1,46 @@
 static int vce_v4_0_sw_init(void *handle) {
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   struct amdgpu_ring *ring;
   unsigned size;
   int r, i;
-  r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCE0, 167, &adev->vce.irq);
+  r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCE0, VISLANDS30_IV_SRCID_VCE_TRAP, &adev->vce.irq);
   if (r) return r;
   size = VCE_V4_0_STACK_SIZE + VCE_V4_0_DATA_SIZE;
   if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) size += VCE_V4_0_FW_SIZE;
   r = amdgpu_vce_sw_init(adev, size);
   if (r) return r;
   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
     const struct common_firmware_header *hdr;
     unsigned size = amdgpu_bo_size(adev->vce.vcpu_bo);
     adev->vce.saved_bo = kmalloc(size, GFP_KERNEL);
     if (!adev->vce.saved_bo) return -ENOMEM;
     hdr = (const struct common_firmware_header *)adev->vce.fw->data;
     adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].ucode_id = AMDGPU_UCODE_ID_VCE;
     adev->firmware.ucode[AMDGPU_UCODE_ID_VCE].fw = adev->vce.fw;
     adev->firmware.fw_size += ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
     DRM_INFO("PSP loading VCE firmware\n");
   } else {
     r = amdgpu_vce_resume(adev);
     if (r) return r;
   }
   for (i = 0; i < adev->vce.num_rings; i++) {
     ring = &adev->vce.ring[i];
     sprintf(ring->name, "vce%d", i);
     if (amdgpu_sriov_vf(adev)) {
       /* DOORBELL only works under SRIOV */
       ring->use_doorbell = true;
       /* currently only use the first encoding ring for sriov,
        * so set unused location for other unused rings.
        */
       if (i == 0)
         ring->doorbell_index = AMDGPU_DOORBELL64_VCE_RING0_1 * 2;
       else
         ring->doorbell_index = AMDGPU_DOORBELL64_VCE_RING2_3 * 2 + 1;
     }
     r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0);
     if (r) return r;
   }
   r = amdgpu_virt_alloc_mm_table(adev);
   if (r) return r;
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 167
+ VISLANDS30_IV_SRCID_VCE_TRAP
...+>,e3)
--- initial
+++ final
@@ -1,35 +1,35 @@
 static int vcn_v1_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   int i, r;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   /* VCN DEC TRAP */
-  r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 124, &adev->vcn.irq);
+  r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->vcn.irq);
   if (r) return r;
   /* VCN ENC TRAP */
   for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
-    r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + 119, &adev->vcn.irq);
+    r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->vcn.irq);
     if (r) return r;
   }
   /* VCN JPEG TRAP */
   r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_VCN, 126, &adev->vcn.irq);
   if (r) return r;
   r = amdgpu_vcn_sw_init(adev);
   if (r) return r;
   r = amdgpu_vcn_resume(adev);
   if (r) return r;
   ring = &adev->vcn.ring_dec;
   sprintf(ring->name, "vcn_dec");
   r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
   if (r) return r;
   for (i = 0; i < adev->vcn.num_enc_rings; ++i) {
     ring = &adev->vcn.ring_enc[i];
     sprintf(ring->name, "vcn_enc%d", i);
     r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
     if (r) return r;
   }
   ring = &adev->vcn.ring_jpeg;
   sprintf(ring->name, "vcn_jpeg");
   r = amdgpu_ring_init(adev, ring, 512, &adev->vcn.irq, 0);
   if (r) return r;
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 119
+ VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP 
...+>,e3)
@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 124
+ VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE 
...+>,e3)
--- initial
+++ final
@@ -1,48 +1,48 @@
 int alloc_gtt_mem(struct kgd_dev *kgd, size_t size, void **mem_obj, uint64_t *gpu_addr, void **cpu_ptr) {
   struct amdgpu_device *adev = (struct amdgpu_device *)kgd;
   struct amdgpu_bo *bo = NULL;
   struct amdgpu_bo_param bp;
   int r;
   uint64_t gpu_addr_tmp = 0;
   void *cpu_ptr_tmp = NULL;
   memset(&bp, 0, sizeof(bp));
   bp.size = size;
   bp.byte_align = PAGE_SIZE;
   bp.domain = AMDGPU_GEM_DOMAIN_GTT;
   bp.flags = AMDGPU_GEM_CREATE_CPU_GTT_USWC;
   bp.type = ttm_bo_type_kernel;
   bp.resv = NULL;
   r = amdgpu_bo_create(adev, &bp, &bo);
   if (r) {
     dev_err(adev->dev, "failed to allocate BO for amdkfd (%d)\n", r);
     return r;
   }
   /* map the buffer */
   r = amdgpu_bo_reserve(bo, true);
   if (r) {
     dev_err(adev->dev, "(%d) failed to reserve bo for amdkfd\n", r);
     goto allocate_mem_reserve_bo_failed;
   }
-  r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, &gpu_addr_tmp);
+  r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
   if (r) {
     dev_err(adev->dev, "(%d) failed to pin bo for amdkfd\n", r);
     goto allocate_mem_pin_bo_failed;
   }
   r = amdgpu_bo_kmap(bo, &cpu_ptr_tmp);
   if (r) {
     dev_err(adev->dev, "(%d) failed to map bo to kernel for amdkfd\n", r);
     goto allocate_mem_kmap_bo_failed;
   }
   *mem_obj = bo;
-  *gpu_addr = gpu_addr_tmp;
+  *gpu_addr = amdgpu_bo_gpu_offset(bo);
   *cpu_ptr = cpu_ptr_tmp;
   amdgpu_bo_unreserve(bo);
   return 0;
 allocate_mem_kmap_bo_failed:
   amdgpu_bo_unpin(bo);
 allocate_mem_pin_bo_failed:
   amdgpu_bo_unreserve(bo);
 allocate_mem_reserve_bo_failed:
   amdgpu_bo_unref(&bo);
   return r;
 }<sep>@@
expression e1,e2,r;
local idexpression i;
@@

        r = amdgpu_bo_pin(e1,e2
-                     ,&i
                     );
	...
-	i
+	amdgpu_bo_gpu_offset(e1)
	... when != i
--- initial
+++ final
@@ -1,40 +1,40 @@
 int amdgpu_amdkfd_gpuvm_map_gtt_bo_to_kernel(struct kgd_dev *kgd, struct kgd_mem *mem, void **kptr, uint64_t *size) {
   int ret;
   struct amdgpu_bo *bo = mem->bo;
   if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) {
     pr_err("userptr can't be mapped to kernel\n");
     return -EINVAL;
   }
   /* delete kgd_mem from kfd_bo_list to avoid re-validating
    * this BO in BO's restoring after eviction.
    */
   mutex_lock(&mem->process_info->lock);
   ret = amdgpu_bo_reserve(bo, true);
   if (ret) {
     pr_err("Failed to reserve bo. ret %d\n", ret);
     goto bo_reserve_failed;
   }
-  ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL);
+  ret = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
   if (ret) {
     pr_err("Failed to pin bo. ret %d\n", ret);
     goto pin_failed;
   }
   ret = amdgpu_bo_kmap(bo, kptr);
   if (ret) {
     pr_err("Failed to map bo to kernel. ret %d\n", ret);
     goto kmap_failed;
   }
   amdgpu_amdkfd_remove_eviction_fence(bo, mem->process_info->eviction_fence, NULL, NULL);
   list_del_init(&mem->validate_list.head);
   if (size) *size = amdgpu_bo_size(bo);
   amdgpu_bo_unreserve(bo);
   mutex_unlock(&mem->process_info->lock);
   return 0;
 kmap_failed:
   amdgpu_bo_unpin(bo);
 pin_failed:
   amdgpu_bo_unreserve(bo);
 bo_reserve_failed:
   mutex_unlock(&mem->process_info->lock);
   return ret;
 }<sep>@@
expression e1,e2;
@@

        amdgpu_bo_pin(e1,e2
-                     , NULL
                     )
--- initial
+++ final
@@ -1,55 +1,57 @@
 static void amdgpu_benchmark_move(struct amdgpu_device *adev, unsigned size, unsigned sdomain, unsigned ddomain) {
   struct amdgpu_bo *dobj = NULL;
   struct amdgpu_bo *sobj = NULL;
   struct amdgpu_bo_param bp;
   uint64_t saddr, daddr;
   int r, n;
   int time;
   memset(&bp, 0, sizeof(bp));
   bp.size = size;
   bp.byte_align = PAGE_SIZE;
   bp.domain = sdomain;
   bp.flags = 0;
   bp.type = ttm_bo_type_kernel;
   bp.resv = NULL;
   n = AMDGPU_BENCHMARK_ITERATIONS;
   r = amdgpu_bo_create(adev, &bp, &sobj);
   if (r) { goto out_cleanup; }
   r = amdgpu_bo_reserve(sobj, false);
   if (unlikely(r != 0)) goto out_cleanup;
-  r = amdgpu_bo_pin(sobj, sdomain, &saddr);
+  r = amdgpu_bo_pin(sobj, sdomain);
   amdgpu_bo_unreserve(sobj);
   if (r) { goto out_cleanup; }
+  saddr = amdgpu_bo_gpu_offset(sobj);
   bp.domain = ddomain;
   r = amdgpu_bo_create(adev, &bp, &dobj);
   if (r) { goto out_cleanup; }
   r = amdgpu_bo_reserve(dobj, false);
   if (unlikely(r != 0)) goto out_cleanup;
-  r = amdgpu_bo_pin(dobj, ddomain, &daddr);
+  r = amdgpu_bo_pin(dobj, ddomain);
   amdgpu_bo_unreserve(dobj);
   if (r) { goto out_cleanup; }
+  daddr = amdgpu_bo_gpu_offset(dobj);
   if (adev->mman.buffer_funcs) {
     time = amdgpu_benchmark_do_move(adev, size, saddr, daddr, n);
     if (time < 0) goto out_cleanup;
     if (time > 0) amdgpu_benchmark_log_results(n, size, time, sdomain, ddomain, "dma");
   }
 out_cleanup:
   /* Check error value now. The value can be overwritten when clean up.*/
   if (r) { DRM_ERROR("Error while benchmarking BO move.\n"); }
   if (sobj) {
     r = amdgpu_bo_reserve(sobj, true);
     if (likely(r == 0)) {
       amdgpu_bo_unpin(sobj);
       amdgpu_bo_unreserve(sobj);
     }
     amdgpu_bo_unref(&sobj);
   }
   if (dobj) {
     r = amdgpu_bo_reserve(dobj, true);
     if (likely(r == 0)) {
       amdgpu_bo_unpin(dobj);
       amdgpu_bo_unreserve(dobj);
     }
     amdgpu_bo_unref(&dobj);
   }
 }<sep>@@
expression e1,e2,e3,r;
statement S;
@@

        r = amdgpu_bo_pin(e1,e2
-                     ,&e3
                     );
	... when != r
	if (<+...r...+>) S
+       e3 = amdgpu_bo_gpu_offset(e1);
--- initial
+++ final
@@ -1,77 +1,78 @@
 int amdgpu_device_resume(struct drm_device *dev, bool resume, bool fbcon) {
   struct drm_connector *connector;
   struct amdgpu_device *adev = dev->dev_private;
   struct drm_crtc *crtc;
   int r = 0;
   if (dev->switch_power_state == DRM_SWITCH_POWER_OFF) return 0;
   if (fbcon) console_lock();
   if (resume) {
     pci_set_power_state(dev->pdev, PCI_D0);
     pci_restore_state(dev->pdev);
     r = pci_enable_device(dev->pdev);
     if (r) goto unlock;
   }
   /* post card */
   if (amdgpu_device_need_post(adev)) {
     r = amdgpu_atom_asic_init(adev->mode_info.atom_context);
     if (r) DRM_ERROR("amdgpu asic init failed\n");
   }
   r = amdgpu_device_ip_resume(adev);
   if (r) {
     DRM_ERROR("amdgpu_device_ip_resume failed (%d).\n", r);
     goto unlock;
   }
   amdgpu_fence_driver_resume(adev);
   r = amdgpu_device_ip_late_init(adev);
   if (r) goto unlock;
   /* pin cursors */
   list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
     struct amdgpu_crtc *amdgpu_crtc = to_amdgpu_crtc(crtc);
     if (amdgpu_crtc->cursor_bo) {
       struct amdgpu_bo *aobj = gem_to_amdgpu_bo(amdgpu_crtc->cursor_bo);
       r = amdgpu_bo_reserve(aobj, true);
       if (r == 0) {
-        r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM, &amdgpu_crtc->cursor_addr);
+        r = amdgpu_bo_pin(aobj, AMDGPU_GEM_DOMAIN_VRAM);
         if (r != 0) DRM_ERROR("Failed to pin cursor BO (%d)\n", r);
+        amdgpu_crtc->cursor_addr = amdgpu_bo_gpu_offset(aobj);
         amdgpu_bo_unreserve(aobj);
       }
     }
   }
   r = amdgpu_amdkfd_resume(adev);
   if (r) return r;
   /* blat the mode back in */
   if (fbcon) {
     if (!amdgpu_device_has_dc_support(adev)) {
       /* pre DCE11 */
       drm_helper_resume_force_mode(dev);
       /* turn on display hw */
       drm_modeset_lock_all(dev);
       list_for_each_entry(connector, &dev->mode_config.connector_list, head) { drm_helper_connector_dpms(connector, DRM_MODE_DPMS_ON); }
       drm_modeset_unlock_all(dev);
     }
   }
   drm_kms_helper_poll_enable(dev);
   /*
    * Most of the connector probing functions try to acquire runtime pm
    * refs to ensure that the GPU is powered on when connector polling is
    * performed. Since we're calling this from a runtime PM callback,
    * trying to acquire rpm refs will cause us to deadlock.
    *
    * Since we're guaranteed to be holding the rpm lock, it's safe to
    * temporarily disable the rpm helpers so this doesn't deadlock us.
    */
 #ifdef CONFIG_PM
   dev->dev->power.disable_depth++;
 #endif
   if (!amdgpu_device_has_dc_support(adev))
     drm_helper_hpd_irq_event(dev);
   else
     drm_kms_helper_hotplug_event(dev);
 #ifdef CONFIG_PM
   dev->dev->power.disable_depth--;
 #endif
   if (fbcon) amdgpu_fbdev_set_suspend(adev, 0);
 unlock:
   if (fbcon) console_unlock();
   return r;
 }<sep>@@
expression e1,e2,e3,r;
statement S;
@@

        r = amdgpu_bo_pin(e1,e2
-                     ,&e3
                     );
	... when != r
	if (<+...r...+>) S
+       e3 = amdgpu_bo_gpu_offset(e1);
--- initial
+++ final
@@ -1,50 +1,51 @@
 static int dm_plane_helper_prepare_fb(struct drm_plane *plane, struct drm_plane_state *new_state) {
   struct amdgpu_framebuffer *afb;
   struct drm_gem_object *obj;
   struct amdgpu_device *adev;
   struct amdgpu_bo *rbo;
   uint64_t chroma_addr = 0;
   struct dm_plane_state *dm_plane_state_new, *dm_plane_state_old;
   unsigned int awidth;
   uint32_t domain;
   int r;
   dm_plane_state_old = to_dm_plane_state(plane->state);
   dm_plane_state_new = to_dm_plane_state(new_state);
   if (!new_state->fb) {
     DRM_DEBUG_DRIVER("No FB bound\n");
     return 0;
   }
   afb = to_amdgpu_framebuffer(new_state->fb);
   obj = new_state->fb->obj[0];
   rbo = gem_to_amdgpu_bo(obj);
   adev = amdgpu_ttm_adev(rbo->tbo.bdev);
   r = amdgpu_bo_reserve(rbo, false);
   if (unlikely(r != 0)) return r;
   if (plane->type != DRM_PLANE_TYPE_CURSOR)
     domain = amdgpu_display_supported_domains(adev);
   else
     domain = AMDGPU_GEM_DOMAIN_VRAM;
-  r = amdgpu_bo_pin(rbo, domain, &afb->address);
+  r = amdgpu_bo_pin(rbo, domain);
   amdgpu_bo_unreserve(rbo);
   if (unlikely(r != 0)) {
     if (r != -ERESTARTSYS) DRM_ERROR("Failed to pin framebuffer with error %d\n", r);
     return r;
   }
+  afb->address = amdgpu_bo_gpu_offset(rbo);
   amdgpu_bo_ref(rbo);
   if (dm_plane_state_new->dc_state && dm_plane_state_old->dc_state != dm_plane_state_new->dc_state) {
     struct dc_plane_state *plane_state = dm_plane_state_new->dc_state;
     if (plane_state->format < SURFACE_PIXEL_FORMAT_VIDEO_BEGIN) {
       plane_state->address.grph.addr.low_part = lower_32_bits(afb->address);
       plane_state->address.grph.addr.high_part = upper_32_bits(afb->address);
     } else {
       awidth = ALIGN(new_state->fb->width, 64);
       plane_state->address.type = PLN_ADDR_TYPE_VIDEO_PROGRESSIVE;
       plane_state->address.video_progressive.luma_addr.low_part = lower_32_bits(afb->address);
       plane_state->address.video_progressive.luma_addr.high_part = upper_32_bits(afb->address);
       chroma_addr = afb->address + (u64)awidth * new_state->fb->height;
       plane_state->address.video_progressive.chroma_addr.low_part = lower_32_bits(chroma_addr);
       plane_state->address.video_progressive.chroma_addr.high_part = upper_32_bits(chroma_addr);
     }
   }
   return 0;
 }<sep>@@
expression e1,e2,e3,r;
statement S;
@@

        r = amdgpu_bo_pin(e1,e2
-                     ,&e3
                     );
	... when != r
	if (<+...r...+>) S
+       e3 = amdgpu_bo_gpu_offset(e1);
--- initial
+++ final
@@ -1,45 +1,45 @@
 static int amdgpufb_create_pinned_object(struct amdgpu_fbdev *rfbdev, struct drm_mode_fb_cmd2 *mode_cmd, struct drm_gem_object **gobj_p) {
   struct amdgpu_device *adev = rfbdev->adev;
   struct drm_gem_object *gobj = NULL;
   struct amdgpu_bo *abo = NULL;
   bool fb_tiled = false; /* useful for testing */
   u32 tiling_flags = 0, domain;
   int ret;
   int aligned_size, size;
   int height = mode_cmd->height;
   u32 cpp;
   cpp = drm_format_plane_cpp(mode_cmd->pixel_format, 0);
   /* need to align pitch with crtc limits */
   mode_cmd->pitches[0] = amdgpu_align_pitch(adev, mode_cmd->width, cpp, fb_tiled);
   domain = amdgpu_display_supported_domains(adev);
   height = ALIGN(mode_cmd->height, 8);
   size = mode_cmd->pitches[0] * height;
   aligned_size = ALIGN(size, PAGE_SIZE);
   ret = amdgpu_gem_object_create(adev, aligned_size, 0, domain, AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS | AMDGPU_GEM_CREATE_VRAM_CLEARED, ttm_bo_type_kernel, NULL, &gobj);
   if (ret) {
     pr_err("failed to allocate framebuffer (%d)\n", aligned_size);
     return -ENOMEM;
   }
   abo = gem_to_amdgpu_bo(gobj);
   if (fb_tiled) tiling_flags = AMDGPU_TILING_SET(ARRAY_MODE, GRPH_ARRAY_2D_TILED_THIN1);
   ret = amdgpu_bo_reserve(abo, false);
   if (unlikely(ret != 0)) goto out_unref;
   if (tiling_flags) {
     ret = amdgpu_bo_set_tiling_flags(abo, tiling_flags);
     if (ret) dev_err(adev->dev, "FB failed to set tiling flags\n");
   }
-  ret = amdgpu_bo_pin(abo, domain, NULL);
+  ret = amdgpu_bo_pin(abo, domain);
   if (ret) {
     amdgpu_bo_unreserve(abo);
     goto out_unref;
   }
   ret = amdgpu_bo_kmap(abo, NULL);
   amdgpu_bo_unreserve(abo);
   if (ret) { goto out_unref; }
   *gobj_p = gobj;
   return 0;
 out_unref:
   amdgpufb_destroy_pinned_object(gobj);
   *gobj_p = NULL;
   return ret;
 }<sep>@@
expression e1,e2;
@@

        amdgpu_bo_pin(e1,e2
-                     , NULL
                     )
--- initial
+++ final
@@ -1,16 +1,16 @@
 int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev) {
   uint64_t gpu_addr;
   int r;
   r = amdgpu_bo_reserve(adev->gart.robj, false);
   if (unlikely(r != 0)) return r;
-  r = amdgpu_bo_pin(adev->gart.robj, AMDGPU_GEM_DOMAIN_VRAM, &gpu_addr);
+  r = amdgpu_bo_pin(adev->gart.robj, AMDGPU_GEM_DOMAIN_VRAM);
   if (r) {
     amdgpu_bo_unreserve(adev->gart.robj);
     return r;
   }
   r = amdgpu_bo_kmap(adev->gart.robj, &adev->gart.ptr);
   if (r) amdgpu_bo_unpin(adev->gart.robj);
   amdgpu_bo_unreserve(adev->gart.robj);
-  adev->gart.table_addr = gpu_addr;
+  adev->gart.table_addr = amdgpu_bo_gpu_offset(adev->gart.robj);
   return r;
 }<sep>@@
expression e1,e2,r;
local idexpression i;
@@

        r = amdgpu_bo_pin(e1,e2
-                     ,&i
                     );
	...
-	i
+	amdgpu_bo_gpu_offset(e1)
	... when != i
--- initial
+++ final
@@ -1,43 +1,44 @@
 int amdgpu_bo_create_reserved(struct amdgpu_device *adev, unsigned long size, int align, u32 domain, struct amdgpu_bo **bo_ptr, u64 *gpu_addr, void **cpu_addr) {
   struct amdgpu_bo_param bp;
   bool free = false;
   int r;
   memset(&bp, 0, sizeof(bp));
   bp.size = size;
   bp.byte_align = align;
   bp.domain = domain;
   bp.flags = AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED | AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
   bp.type = ttm_bo_type_kernel;
   bp.resv = NULL;
   if (!*bo_ptr) {
     r = amdgpu_bo_create(adev, &bp, bo_ptr);
     if (r) {
       dev_err(adev->dev, "(%d) failed to allocate kernel bo\n", r);
       return r;
     }
     free = true;
   }
   r = amdgpu_bo_reserve(*bo_ptr, false);
   if (r) {
     dev_err(adev->dev, "(%d) failed to reserve kernel bo\n", r);
     goto error_free;
   }
-  r = amdgpu_bo_pin(*bo_ptr, domain, gpu_addr);
+  r = amdgpu_bo_pin(*bo_ptr, domain);
   if (r) {
     dev_err(adev->dev, "(%d) kernel bo pin failed\n", r);
     goto error_unreserve;
   }
+  if (gpu_addr) *gpu_addr = amdgpu_bo_gpu_offset(*bo_ptr);
   if (cpu_addr) {
     r = amdgpu_bo_kmap(*bo_ptr, cpu_addr);
     if (r) {
       dev_err(adev->dev, "(%d) kernel bo map failed\n", r);
       goto error_unreserve;
     }
   }
   return 0;
 error_unreserve:
   amdgpu_bo_unreserve(*bo_ptr);
 error_free:
   if (free) amdgpu_bo_unref(bo_ptr);
   return r;
 }<sep>@@
expression e1,e2,e3,r;
statement S;
@@

        r = amdgpu_bo_pin(e1,e2
-                     ,e3
                     );
	... when != r
	if (<+...r...+>) S
+       if (e3) *e3 = amdgpu_bo_gpu_offset(e1);
--- initial
+++ final
@@ -1,30 +1,30 @@
 static int amdgpu_gem_map_attach(struct dma_buf *dma_buf, struct dma_buf_attachment *attach) {
   struct drm_gem_object *obj = dma_buf->priv;
   struct amdgpu_bo *bo = gem_to_amdgpu_bo(obj);
   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
   long r;
   r = drm_gem_map_attach(dma_buf, attach);
   if (r) return r;
   r = amdgpu_bo_reserve(bo, false);
   if (unlikely(r != 0)) goto error_detach;
   if (attach->dev->driver != adev->dev->driver) {
     /*
      * Wait for all shared fences to complete before we switch to future
      * use of exclusive fence on this prime shared bo.
      */
     r = reservation_object_wait_timeout_rcu(bo->tbo.resv, true, false, MAX_SCHEDULE_TIMEOUT);
     if (unlikely(r < 0)) {
       DRM_DEBUG_PRIME("Fence wait failed: %li\n", r);
       goto error_unreserve;
     }
   }
   /* pin buffer into GTT */
-  r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT, NULL);
+  r = amdgpu_bo_pin(bo, AMDGPU_GEM_DOMAIN_GTT);
   if (r) goto error_unreserve;
   if (attach->dev->driver != adev->dev->driver) bo->prime_shared_count++;
 error_unreserve:
   amdgpu_bo_unreserve(bo);
 error_detach:
   if (r) drm_gem_map_detach(dma_buf, attach);
   return r;
 }<sep>@@
expression e1,e2;
@@

        amdgpu_bo_pin(e1,e2
-                     , NULL
                     )