--- initial
+++ final
@@ -1,113 +1,113 @@
 static int __init fsmc_nand_probe(struct platform_device *pdev) {
   struct fsmc_nand_data *host;
   struct mtd_info *mtd;
   struct nand_chip *nand;
   struct resource *res;
   void __iomem *base;
   dma_cap_mask_t mask;
   int ret = 0;
   u32 pid;
   int i;
   /* Allocate memory for the device structure (and zero it) */
   host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
   if (!host) return -ENOMEM;
   nand = &host->nand;
   ret = fsmc_nand_probe_config_dt(pdev, host, nand);
   if (ret) return ret;
   res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
   host->data_va = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(host->data_va)) return PTR_ERR(host->data_va);
   host->data_pa = (dma_addr_t)res->start;
   res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr");
   host->addr_va = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(host->addr_va)) return PTR_ERR(host->addr_va);
   res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd");
   host->cmd_va = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(host->cmd_va)) return PTR_ERR(host->cmd_va);
   res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs");
   base = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(base)) return PTR_ERR(base);
   host->regs_va = base + FSMC_NOR_REG_SIZE + (host->bank * FSMC_NAND_BANK_SZ);
   host->clk = devm_clk_get(&pdev->dev, NULL);
   if (IS_ERR(host->clk)) {
     dev_err(&pdev->dev, "failed to fetch block clock\n");
     return PTR_ERR(host->clk);
   }
   ret = clk_prepare_enable(host->clk);
   if (ret) return ret;
   /*
    * This device ID is actually a common AMBA ID as used on the
    * AMBA PrimeCell bus. However it is not a PrimeCell.
    */
   for (pid = 0, i = 0; i < 4; i++)
     pid |= (readl(base + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8);
   host->pid = pid;
   dev_info(&pdev->dev,
            "FSMC device partno %03x, manufacturer %02x, "
            "revision %02x, config %02x\n",
            AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid), AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid));
   host->dev = &pdev->dev;
   if (host->mode == USE_DMA_ACCESS) init_completion(&host->dma_access_complete);
   /* Link all private pointers */
   mtd = nand_to_mtd(&host->nand);
   nand_set_controller_data(nand, host);
   nand_set_flash_node(nand, pdev->dev.of_node);
   mtd->dev.parent = &pdev->dev;
   nand->exec_op = fsmc_exec_op;
   nand->select_chip = fsmc_select_chip;
-  nand->chip_delay = 30;
+  nand->legacy.chip_delay = 30;
   /*
    * Setup default ECC mode. nand_dt_init() called from nand_scan_ident()
    * can overwrite this value if the DT provides a different value.
    */
   nand->ecc.mode = NAND_ECC_HW;
   nand->ecc.hwctl = fsmc_enable_hwecc;
   nand->ecc.size = 512;
   nand->badblockbits = 7;
   if (host->mode == USE_DMA_ACCESS) {
     dma_cap_zero(mask);
     dma_cap_set(DMA_MEMCPY, mask);
     host->read_dma_chan = dma_request_channel(mask, filter, NULL);
     if (!host->read_dma_chan) {
       dev_err(&pdev->dev, "Unable to get read dma channel\n");
       goto disable_clk;
     }
     host->write_dma_chan = dma_request_channel(mask, filter, NULL);
     if (!host->write_dma_chan) {
       dev_err(&pdev->dev, "Unable to get write dma channel\n");
       goto release_dma_read_chan;
     }
   }
   if (host->dev_timings)
     fsmc_nand_setup(host, host->dev_timings);
   else
     nand->setup_data_interface = fsmc_setup_data_interface;
   if (AMBA_REV_BITS(host->pid) >= 8) {
     nand->ecc.read_page = fsmc_read_page_hwecc;
     nand->ecc.calculate = fsmc_read_hwecc_ecc4;
     nand->ecc.correct = fsmc_bch8_correct_data;
     nand->ecc.bytes = 13;
     nand->ecc.strength = 8;
   }
   /*
    * Scan to find existence of the device
    */
   nand->dummy_controller.ops = &fsmc_nand_controller_ops;
   ret = nand_scan(nand, 1);
   if (ret) goto release_dma_write_chan;
   mtd->name = "nand";
   ret = mtd_device_register(mtd, NULL, 0);
   if (ret) goto cleanup_nand;
   platform_set_drvdata(pdev, host);
   dev_info(&pdev->dev, "FSMC NAND driver registration successful\n");
   return 0;
 cleanup_nand:
   nand_cleanup(nand);
 release_dma_write_chan:
   if (host->mode == USE_DMA_ACCESS) dma_release_channel(host->write_dma_chan);
 release_dma_read_chan:
   if (host->mode == USE_DMA_ACCESS) dma_release_channel(host->read_dma_chan);
 disable_clk:
   clk_disable_unprepare(host->clk);
   return ret;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay