imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,64 +1,64 @@
 static int oxnas_nand_probe(struct platform_device *pdev) {
   struct device_node *np = pdev->dev.of_node;
   struct device_node *nand_np;
   struct oxnas_nand_ctrl *oxnas;
   struct nand_chip *chip;
   struct mtd_info *mtd;
   struct resource *res;
   int nchips = 0;
   int count = 0;
   int err = 0;
   /* Allocate memory for the device structure (and zero it) */
   oxnas = devm_kzalloc(&pdev->dev, sizeof(*oxnas), GFP_KERNEL);
   if (!oxnas) return -ENOMEM;
   nand_controller_init(&oxnas->base);
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(oxnas->io_base)) return PTR_ERR(oxnas->io_base);
   oxnas->clk = devm_clk_get(&pdev->dev, NULL);
   if (IS_ERR(oxnas->clk)) oxnas->clk = NULL;
   /* Only a single chip node is supported */
   count = of_get_child_count(np);
   if (count > 1) return -EINVAL;
   err = clk_prepare_enable(oxnas->clk);
   if (err) return err;
   device_reset_optional(&pdev->dev);
   for_each_child_of_node(np, nand_np) {
     chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip), GFP_KERNEL);
     if (!chip) {
       err = -ENOMEM;
       goto err_clk_unprepare;
     }
     chip->controller = &oxnas->base;
     nand_set_flash_node(chip, nand_np);
     nand_set_controller_data(chip, oxnas);
     mtd = nand_to_mtd(chip);
     mtd->dev.parent = &pdev->dev;
     mtd->priv = chip;
     chip->cmd_ctrl = oxnas_nand_cmd_ctrl;
     chip->read_buf = oxnas_nand_read_buf;
     chip->read_byte = oxnas_nand_read_byte;
     chip->write_buf = oxnas_nand_write_buf;
     chip->chip_delay = 30;
     /* Scan to find existence of the device */
-    err = nand_scan(mtd, 1);
+    err = nand_scan(chip, 1);
     if (err) goto err_clk_unprepare;
     err = mtd_device_register(mtd, NULL, 0);
     if (err) {
       nand_release(mtd);
       goto err_clk_unprepare;
     }
     oxnas->chips[nchips] = chip;
     ++nchips;
   }
   /* Exit if no chips found */
   if (!nchips) {
     err = -ENODEV;
     goto err_clk_unprepare;
   }
   platform_set_drvdata(pdev, oxnas);
   return 0;
 err_clk_unprepare:
   clk_disable_unprepare(oxnas->clk);
   return err;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,66 +1,66 @@
 static int pasemi_nand_probe(struct platform_device *ofdev) {
   struct device *dev = &ofdev->dev;
   struct pci_dev *pdev;
   struct device_node *np = dev->of_node;
   struct resource res;
   struct nand_chip *chip;
   int err = 0;
   err = of_address_to_resource(np, 0, &res);
   if (err) return -EINVAL;
   /* We only support one device at the moment */
   if (pasemi_nand_mtd) return -ENODEV;
   dev_dbg(dev, "pasemi_nand at %pR\n", &res);
   /* Allocate memory for MTD device structure and private data */
   chip = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
   if (!chip) {
     err = -ENOMEM;
     goto out;
   }
   pasemi_nand_mtd = nand_to_mtd(chip);
   /* Link the private data with the MTD structure */
   pasemi_nand_mtd->dev.parent = dev;
   chip->IO_ADDR_R = of_iomap(np, 0);
   chip->IO_ADDR_W = chip->IO_ADDR_R;
   if (!chip->IO_ADDR_R) {
     err = -EIO;
     goto out_mtd;
   }
   pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa008, NULL);
   if (!pdev) {
     err = -ENODEV;
     goto out_ior;
   }
   lpcctl = pci_resource_start(pdev, 0);
   pci_dev_put(pdev);
   if (!request_region(lpcctl, 4, driver_name)) {
     err = -EBUSY;
     goto out_ior;
   }
   chip->cmd_ctrl = pasemi_hwcontrol;
   chip->dev_ready = pasemi_device_ready;
   chip->read_buf = pasemi_read_buf;
   chip->write_buf = pasemi_write_buf;
   chip->chip_delay = 0;
   chip->ecc.mode = NAND_ECC_SOFT;
   chip->ecc.algo = NAND_ECC_HAMMING;
   /* Enable the following for a flash based bad block table */
   chip->bbt_options = NAND_BBT_USE_FLASH;
   /* Scan to find existence of the device */
-  err = nand_scan(pasemi_nand_mtd, 1);
+  err = nand_scan(chip, 1);
   if (err) goto out_lpc;
   if (mtd_device_register(pasemi_nand_mtd, NULL, 0)) {
     dev_err(dev, "Unable to register MTD device\n");
     err = -ENODEV;
     goto out_lpc;
   }
   dev_info(dev, "PA Semi NAND flash at %pR, control at I/O %x\n", &res, lpcctl);
   return 0;
 out_lpc:
   release_region(lpcctl, 4);
 out_ior:
   iounmap(chip->IO_ADDR_R);
 out_mtd:
   kfree(chip);
 out:
   return err;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,42 +1,42 @@
 static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, struct qcom_nand_host *host, struct device_node *dn) {
   struct nand_chip *chip = &host->chip;
   struct mtd_info *mtd = nand_to_mtd(chip);
   struct device *dev = nandc->dev;
   int ret;
   ret = of_property_read_u32(dn, "reg", &host->cs);
   if (ret) {
     dev_err(dev, "can't get chip-select\n");
     return -ENXIO;
   }
   nand_set_flash_node(chip, dn);
   mtd->name = devm_kasprintf(dev, GFP_KERNEL, "qcom_nand.%d", host->cs);
   if (!mtd->name) return -ENOMEM;
   mtd->owner = THIS_MODULE;
   mtd->dev.parent = dev;
   chip->cmdfunc = qcom_nandc_command;
   chip->select_chip = qcom_nandc_select_chip;
   chip->read_byte = qcom_nandc_read_byte;
   chip->read_buf = qcom_nandc_read_buf;
   chip->write_buf = qcom_nandc_write_buf;
   chip->set_features = nand_get_set_features_notsupp;
   chip->get_features = nand_get_set_features_notsupp;
   /*
    * the bad block marker is readable only when we read the last codeword
    * of a page with ECC disabled. currently, the nand_base and nand_bbt
    * helpers don't allow us to read BB from a nand chip with ECC
    * disabled (MTD_OPS_PLACE_OOB is set by default). use the block_bad
    * and block_markbad helpers until we permanently switch to using
    * MTD_OPS_RAW for all drivers (with the help of badblockbits)
    */
   chip->block_bad = qcom_nandc_block_bad;
   chip->block_markbad = qcom_nandc_block_markbad;
   chip->controller = &nandc->controller;
   chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER | NAND_SKIP_BBTSCAN;
   /* set up initial status value */
   host->status = NAND_STATUS_READY | NAND_STATUS_WP;
-  ret = nand_scan(mtd, 1);
+  ret = nand_scan(chip, 1);
   if (ret) return ret;
   ret = mtd_device_register(mtd, NULL, 0);
   if (ret) nand_cleanup(chip);
   return ret;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,69 +1,69 @@
 static int flctl_probe(struct platform_device *pdev) {
   struct resource *res;
   struct sh_flctl *flctl;
   struct mtd_info *flctl_mtd;
   struct nand_chip *nand;
   struct sh_flctl_platform_data *pdata;
   int ret;
   int irq;
   flctl = devm_kzalloc(&pdev->dev, sizeof(struct sh_flctl), GFP_KERNEL);
   if (!flctl) return -ENOMEM;
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   flctl->reg = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(flctl->reg)) return PTR_ERR(flctl->reg);
   flctl->fifo = res->start + 0x24; /* FLDTFIFO */
   irq = platform_get_irq(pdev, 0);
   if (irq < 0) {
     dev_err(&pdev->dev, "failed to get flste irq data: %d\n", irq);
     return irq;
   }
   ret = devm_request_irq(&pdev->dev, irq, flctl_handle_flste, IRQF_SHARED, "flste", flctl);
   if (ret) {
     dev_err(&pdev->dev, "request interrupt failed.\n");
     return ret;
   }
   if (pdev->dev.of_node)
     pdata = flctl_parse_dt(&pdev->dev);
   else
     pdata = dev_get_platdata(&pdev->dev);
   if (!pdata) {
     dev_err(&pdev->dev, "no setup data defined\n");
     return -EINVAL;
   }
   platform_set_drvdata(pdev, flctl);
   nand = &flctl->chip;
   flctl_mtd = nand_to_mtd(nand);
   nand_set_flash_node(nand, pdev->dev.of_node);
   flctl_mtd->dev.parent = &pdev->dev;
   flctl->pdev = pdev;
   flctl->hwecc = pdata->has_hwecc;
   flctl->holden = pdata->use_holden;
   flctl->flcmncr_base = pdata->flcmncr_val;
   flctl->flintdmacr_base = flctl->hwecc ? (STERINTE | ECERB) : STERINTE;
   /* Set address of hardware control function */
   /* 20 us command delay time */
   nand->chip_delay = 20;
   nand->read_byte = flctl_read_byte;
   nand->write_buf = flctl_write_buf;
   nand->read_buf = flctl_read_buf;
   nand->select_chip = flctl_select_chip;
   nand->cmdfunc = flctl_cmdfunc;
   nand->set_features = nand_get_set_features_notsupp;
   nand->get_features = nand_get_set_features_notsupp;
   if (pdata->flcmncr_val & SEL_16BIT) nand->options |= NAND_BUSWIDTH_16;
   pm_runtime_enable(&pdev->dev);
   pm_runtime_resume(&pdev->dev);
   flctl_setup_dma(flctl);
   nand->dummy_controller.ops = &flctl_nand_controller_ops;
-  ret = nand_scan(flctl_mtd, 1);
+  ret = nand_scan(nand, 1);
   if (ret) goto err_chip;
   ret = mtd_device_register(flctl_mtd, pdata->parts, pdata->nr_parts);
   if (ret) goto cleanup_nand;
   return 0;
 cleanup_nand:
   nand_cleanup(nand);
 err_chip:
   flctl_release_dma(flctl);
   pm_runtime_disable(&pdev->dev);
   return ret;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,73 +1,73 @@
 static int sharpsl_nand_probe(struct platform_device *pdev) {
   struct nand_chip *this;
   struct mtd_info *mtd;
   struct resource *r;
   int err = 0;
   struct sharpsl_nand *sharpsl;
   struct sharpsl_nand_platform_data *data = dev_get_platdata(&pdev->dev);
   if (!data) {
     dev_err(&pdev->dev, "no platform data!\n");
     return -EINVAL;
   }
   /* Allocate memory for MTD device structure and private data */
   sharpsl = kzalloc(sizeof(struct sharpsl_nand), GFP_KERNEL);
   if (!sharpsl) return -ENOMEM;
   r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   if (!r) {
     dev_err(&pdev->dev, "no io memory resource defined!\n");
     err = -ENODEV;
     goto err_get_res;
   }
   /* map physical address */
   sharpsl->io = ioremap(r->start, resource_size(r));
   if (!sharpsl->io) {
     dev_err(&pdev->dev, "ioremap to access Sharp SL NAND chip failed\n");
     err = -EIO;
     goto err_ioremap;
   }
   /* Get pointer to private data */
   this = (struct nand_chip *)(&sharpsl->chip);
   /* Link the private data with the MTD structure */
   mtd = nand_to_mtd(this);
   mtd->dev.parent = &pdev->dev;
   mtd_set_ooblayout(mtd, data->ecc_layout);
   platform_set_drvdata(pdev, sharpsl);
   /*
    * PXA initialize
    */
   writeb(readb(sharpsl->io + FLASHCTL) | FLWP, sharpsl->io + FLASHCTL);
   /* Set address of NAND IO lines */
   this->IO_ADDR_R = sharpsl->io + FLASHIO;
   this->IO_ADDR_W = sharpsl->io + FLASHIO;
   /* Set address of hardware control function */
   this->cmd_ctrl = sharpsl_nand_hwcontrol;
   this->dev_ready = sharpsl_nand_dev_ready;
   /* 15 us command delay time */
   this->chip_delay = 15;
   /* set eccmode using hardware ECC */
   this->ecc.mode = NAND_ECC_HW;
   this->ecc.size = 256;
   this->ecc.bytes = 3;
   this->ecc.strength = 1;
   this->badblock_pattern = data->badblock_pattern;
   this->ecc.hwctl = sharpsl_nand_enable_hwecc;
   this->ecc.calculate = sharpsl_nand_calculate_ecc;
   this->ecc.correct = nand_correct_data;
   /* Scan to find existence of the device */
-  err = nand_scan(mtd, 1);
+  err = nand_scan(this, 1);
   if (err) goto err_scan;
   /* Register the partitions */
   mtd->name = "sharpsl-nand";
   err = mtd_device_parse_register(mtd, data->part_parsers, NULL, data->partitions, data->nr_partitions);
   if (err) goto err_add;
   /* Return happy */
   return 0;
 err_add:
   nand_release(mtd);
 err_scan:
   iounmap(sharpsl->io);
 err_ioremap:
 err_get_res:
   kfree(sharpsl);
   return err;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,43 +1,43 @@
 static int socrates_nand_probe(struct platform_device *ofdev) {
   struct socrates_nand_host *host;
   struct mtd_info *mtd;
   struct nand_chip *nand_chip;
   int res;
   /* Allocate memory for the device structure (and zero it) */
   host = devm_kzalloc(&ofdev->dev, sizeof(*host), GFP_KERNEL);
   if (!host) return -ENOMEM;
   host->io_base = of_iomap(ofdev->dev.of_node, 0);
   if (host->io_base == NULL) {
     dev_err(&ofdev->dev, "ioremap failed\n");
     return -EIO;
   }
   nand_chip = &host->nand_chip;
   mtd = nand_to_mtd(nand_chip);
   host->dev = &ofdev->dev;
   /* link the private data structures */
   nand_set_controller_data(nand_chip, host);
   nand_set_flash_node(nand_chip, ofdev->dev.of_node);
   mtd->name = "socrates_nand";
   mtd->dev.parent = &ofdev->dev;
   /*should never be accessed directly */
   nand_chip->IO_ADDR_R = (void *)0xdeadbeef;
   nand_chip->IO_ADDR_W = (void *)0xdeadbeef;
   nand_chip->cmd_ctrl = socrates_nand_cmd_ctrl;
   nand_chip->read_byte = socrates_nand_read_byte;
   nand_chip->write_buf = socrates_nand_write_buf;
   nand_chip->read_buf = socrates_nand_read_buf;
   nand_chip->dev_ready = socrates_nand_device_ready;
   nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
   nand_chip->ecc.algo = NAND_ECC_HAMMING;
   /* TODO: I have no idea what real delay is. */
   nand_chip->chip_delay = 20; /* 20us command delay time */
   dev_set_drvdata(&ofdev->dev, host);
-  res = nand_scan(mtd, 1);
+  res = nand_scan(nand_chip, 1);
   if (res) goto out;
   res = mtd_device_register(mtd, NULL, 0);
   if (!res) return res;
   nand_release(mtd);
 out:
   iounmap(host->io_base);
   return res;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,46 +1,46 @@
 static int chip_init(struct device *dev, struct device_node *np) {
   u32 cs;
   int err, res;
   struct mtd_info *mtd;
   struct nand_chip *chip;
   struct tango_chip *tchip;
   struct nand_ecc_ctrl *ecc;
   struct tango_nfc *nfc = dev_get_drvdata(dev);
   tchip = devm_kzalloc(dev, sizeof(*tchip), GFP_KERNEL);
   if (!tchip) return -ENOMEM;
   res = of_property_count_u32_elems(np, "reg");
   if (res < 0) return res;
   if (res != 1) return -ENOTSUPP; /* Multi-CS chips are not supported */
   err = of_property_read_u32_index(np, "reg", 0, &cs);
   if (err) return err;
   if (cs >= MAX_CS) return -EINVAL;
   chip = &tchip->nand_chip;
   ecc = &chip->ecc;
   mtd = nand_to_mtd(chip);
   chip->read_byte = tango_read_byte;
   chip->write_buf = tango_write_buf;
   chip->read_buf = tango_read_buf;
   chip->select_chip = tango_select_chip;
   chip->cmd_ctrl = tango_cmd_ctrl;
   chip->dev_ready = tango_dev_ready;
   chip->setup_data_interface = tango_set_timings;
   chip->options = NAND_USE_BOUNCE_BUFFER | NAND_NO_SUBPAGE_WRITE | NAND_WAIT_TCCS;
   chip->controller = &nfc->hw;
   tchip->base = nfc->pbus_base + (cs * 256);
   nand_set_flash_node(chip, np);
   mtd_set_ooblayout(mtd, &tango_nand_ooblayout_ops);
   mtd->dev.parent = dev;
-  err = nand_scan(mtd, 1);
+  err = nand_scan(chip, 1);
   if (err) return err;
   tchip->xfer_cfg = XFER_CFG(cs, 1, ecc->steps, METADATA_SIZE);
   tchip->pkt_0_cfg = PKT_CFG(ecc->size + METADATA_SIZE, ecc->strength);
   tchip->pkt_n_cfg = PKT_CFG(ecc->size, ecc->strength);
   tchip->bb_cfg = BB_CFG(mtd->writesize, BBM_SIZE);
   err = mtd_device_register(mtd, NULL, 0);
   if (err) {
     nand_cleanup(chip);
     return err;
   }
   nfc->chips[cs] = tchip;
   return 0;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,57 +1,57 @@
 static int tegra_nand_chips_init(struct device *dev, struct tegra_nand_controller *ctrl) {
   struct device_node *np = dev->of_node;
   struct device_node *np_nand;
   int nsels, nchips = of_get_child_count(np);
   struct tegra_nand_chip *nand;
   struct mtd_info *mtd;
   struct nand_chip *chip;
   int ret;
   u32 cs;
   if (nchips != 1) {
     dev_err(dev, "Currently only one NAND chip supported\n");
     return -EINVAL;
   }
   np_nand = of_get_next_child(np, NULL);
   nsels = of_property_count_elems_of_size(np_nand, "reg", sizeof(u32));
   if (nsels != 1) {
     dev_err(dev, "Missing/invalid reg property\n");
     return -EINVAL;
   }
   /* Retrieve CS id, currently only single die NAND supported */
   ret = of_property_read_u32(np_nand, "reg", &cs);
   if (ret) {
     dev_err(dev, "could not retrieve reg property: %d\n", ret);
     return ret;
   }
   nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
   if (!nand) return -ENOMEM;
   nand->cs[0] = cs;
   nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
   if (IS_ERR(nand->wp_gpio)) {
     ret = PTR_ERR(nand->wp_gpio);
     dev_err(dev, "Failed to request WP GPIO: %d\n", ret);
     return ret;
   }
   chip = &nand->chip;
   chip->controller = &ctrl->controller;
   mtd = nand_to_mtd(chip);
   mtd->dev.parent = dev;
   mtd->owner = THIS_MODULE;
   nand_set_flash_node(chip, np_nand);
   if (!mtd->name) mtd->name = "tegra_nand";
   chip->options = NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER;
   chip->exec_op = tegra_nand_exec_op;
   chip->select_chip = tegra_nand_select_chip;
   chip->setup_data_interface = tegra_nand_setup_data_interface;
-  ret = nand_scan(mtd, 1);
+  ret = nand_scan(chip, 1);
   if (ret) return ret;
   mtd_ooblayout_ecc(mtd, 0, &nand->ecc);
   ret = mtd_device_register(mtd, NULL, 0);
   if (ret) {
     dev_err(dev, "Failed to register mtd device: %d\n", ret);
     nand_cleanup(chip);
     return ret;
   }
   ctrl->chip = chip;
   return 0;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,63 +1,63 @@
 static int tmio_probe(struct platform_device *dev) {
   struct tmio_nand_data *data = dev_get_platdata(&dev->dev);
   struct resource *fcr = platform_get_resource(dev, IORESOURCE_MEM, 0);
   struct resource *ccr = platform_get_resource(dev, IORESOURCE_MEM, 1);
   int irq = platform_get_irq(dev, 0);
   struct tmio_nand *tmio;
   struct mtd_info *mtd;
   struct nand_chip *nand_chip;
   int retval;
   if (data == NULL) dev_warn(&dev->dev, "NULL platform data!\n");
   tmio = devm_kzalloc(&dev->dev, sizeof(*tmio), GFP_KERNEL);
   if (!tmio) return -ENOMEM;
   tmio->dev = dev;
   platform_set_drvdata(dev, tmio);
   nand_chip = &tmio->chip;
   mtd = nand_to_mtd(nand_chip);
   mtd->name = "tmio-nand";
   mtd->dev.parent = &dev->dev;
   tmio->ccr = devm_ioremap(&dev->dev, ccr->start, resource_size(ccr));
   if (!tmio->ccr) return -EIO;
   tmio->fcr_base = fcr->start & 0xfffff;
   tmio->fcr = devm_ioremap(&dev->dev, fcr->start, resource_size(fcr));
   if (!tmio->fcr) return -EIO;
   retval = tmio_hw_init(dev, tmio);
   if (retval) return retval;
   /* Set address of NAND IO lines */
   nand_chip->IO_ADDR_R = tmio->fcr;
   nand_chip->IO_ADDR_W = tmio->fcr;
   /* Set address of hardware control function */
   nand_chip->cmd_ctrl = tmio_nand_hwcontrol;
   nand_chip->dev_ready = tmio_nand_dev_ready;
   nand_chip->read_byte = tmio_nand_read_byte;
   nand_chip->write_buf = tmio_nand_write_buf;
   nand_chip->read_buf = tmio_nand_read_buf;
   /* set eccmode using hardware ECC */
   nand_chip->ecc.mode = NAND_ECC_HW;
   nand_chip->ecc.size = 512;
   nand_chip->ecc.bytes = 6;
   nand_chip->ecc.strength = 2;
   nand_chip->ecc.hwctl = tmio_nand_enable_hwecc;
   nand_chip->ecc.calculate = tmio_nand_calculate_ecc;
   nand_chip->ecc.correct = tmio_nand_correct_data;
   if (data) nand_chip->badblock_pattern = data->badblock_pattern;
   /* 15 us command delay time */
   nand_chip->chip_delay = 15;
   retval = devm_request_irq(&dev->dev, irq, &tmio_irq, 0, dev_name(&dev->dev), tmio);
   if (retval) {
     dev_err(&dev->dev, "request_irq error %d\n", retval);
     goto err_irq;
   }
   tmio->irq = irq;
   nand_chip->waitfunc = tmio_nand_wait;
   /* Scan to find existence of the device */
-  retval = nand_scan(mtd, 1);
+  retval = nand_scan(nand_chip, 1);
   if (retval) goto err_irq;
   /* Register the partitions */
   retval = mtd_device_parse_register(mtd, data ? data->part_parsers : NULL, NULL, data ? data->partition : NULL, data ? data->num_partitions : 0);
   if (!retval) return retval;
   nand_release(mtd);
 err_irq:
   tmio_hw_stop(dev, tmio);
   return retval;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,75 +1,75 @@
 static int __init txx9ndfmc_probe(struct platform_device *dev) {
   struct txx9ndfmc_platform_data *plat = dev_get_platdata(&dev->dev);
   int hold, spw;
   int i;
   struct txx9ndfmc_drvdata *drvdata;
   unsigned long gbusclk = plat->gbus_clock;
   struct resource *res;
   drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
   if (!drvdata) return -ENOMEM;
   res = platform_get_resource(dev, IORESOURCE_MEM, 0);
   drvdata->base = devm_ioremap_resource(&dev->dev, res);
   if (IS_ERR(drvdata->base)) return PTR_ERR(drvdata->base);
   hold = plat->hold ?: 20; /* tDH */
   spw = plat->spw ?: 90;   /* max(tREADID, tWP, tRP) */
   hold = TXX9NDFMC_NS_TO_CYC(gbusclk, hold);
   spw = TXX9NDFMC_NS_TO_CYC(gbusclk, spw);
   if (plat->flags & NDFMC_PLAT_FLAG_HOLDADD) hold -= 2; /* actual hold time : (HOLD + 2) BUSCLK */
   spw -= 1;                                             /* actual wait time : (SPW + 1) BUSCLK */
   hold = clamp(hold, 1, 15);
   drvdata->hold = hold;
   spw = clamp(spw, 1, 15);
   drvdata->spw = spw;
   dev_info(&dev->dev, "CLK:%ldMHz HOLD:%d SPW:%d\n", (gbusclk + 500000) / 1000000, hold, spw);
   nand_controller_init(&drvdata->controller);
   drvdata->controller.ops = &txx9ndfmc_controller_ops;
   platform_set_drvdata(dev, drvdata);
   txx9ndfmc_initialize(dev);
   for (i = 0; i < MAX_TXX9NDFMC_DEV; i++) {
     struct txx9ndfmc_priv *txx9_priv;
     struct nand_chip *chip;
     struct mtd_info *mtd;
     if (!(plat->ch_mask & (1 << i))) continue;
     txx9_priv = kzalloc(sizeof(struct txx9ndfmc_priv), GFP_KERNEL);
     if (!txx9_priv) continue;
     chip = &txx9_priv->chip;
     mtd = nand_to_mtd(chip);
     mtd->dev.parent = &dev->dev;
     chip->read_byte = txx9ndfmc_read_byte;
     chip->read_buf = txx9ndfmc_read_buf;
     chip->write_buf = txx9ndfmc_write_buf;
     chip->cmd_ctrl = txx9ndfmc_cmd_ctrl;
     chip->dev_ready = txx9ndfmc_dev_ready;
     chip->ecc.calculate = txx9ndfmc_calculate_ecc;
     chip->ecc.correct = txx9ndfmc_correct_data;
     chip->ecc.hwctl = txx9ndfmc_enable_hwecc;
     chip->ecc.mode = NAND_ECC_HW;
     chip->ecc.strength = 1;
     chip->chip_delay = 100;
     chip->controller = &drvdata->controller;
     nand_set_controller_data(chip, txx9_priv);
     txx9_priv->dev = dev;
     if (plat->ch_mask != 1) {
       txx9_priv->cs = i;
       txx9_priv->mtdname = kasprintf(GFP_KERNEL, "%s.%u", dev_name(&dev->dev), i);
     } else {
       txx9_priv->cs = -1;
       txx9_priv->mtdname = kstrdup(dev_name(&dev->dev), GFP_KERNEL);
     }
     if (!txx9_priv->mtdname) {
       kfree(txx9_priv);
       dev_err(&dev->dev, "Unable to allocate MTD name.\n");
       continue;
     }
     if (plat->wide_mask & (1 << i)) chip->options |= NAND_BUSWIDTH_16;
-    if (nand_scan(mtd, 1)) {
+    if (nand_scan(chip, 1)) {
       kfree(txx9_priv->mtdname);
       kfree(txx9_priv);
       continue;
     }
     mtd->name = txx9_priv->mtdname;
     mtd_device_register(mtd, NULL, 0);
     drvdata->mtds[i] = mtd;
   }
   return 0;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)