--- initial
+++ final
@@ -1,46 +1,46 @@
 static int gfx_v9_0_init_rlc_save_restore_list(struct amdgpu_device *adev) {
   int unique_indirect_regs[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
   int unique_indirect_reg_count = 0;
   int indirect_start_offsets[] = {0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0};
   int indirect_start_offsets_count = 0;
   int list_size = 0;
   int i = 0;
   u32 tmp = 0;
   u32 *register_list_format = kmalloc(adev->gfx.rlc.reg_list_format_size_bytes, GFP_KERNEL);
   if (!register_list_format) return -ENOMEM;
   memcpy(register_list_format, adev->gfx.rlc.register_list_format, adev->gfx.rlc.reg_list_format_size_bytes);
   /* setup unique_indirect_regs array and indirect_start_offsets array */
-  gfx_v9_0_parse_ind_reg_list(register_list_format, GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH, adev->gfx.rlc.reg_list_format_size_bytes >> 2, unique_indirect_regs, &unique_indirect_reg_count, sizeof(unique_indirect_regs) / sizeof(int), indirect_start_offsets, &indirect_start_offsets_count, sizeof(indirect_start_offsets) / sizeof(int));
+  gfx_v9_0_parse_ind_reg_list(register_list_format, GFX9_RLC_FORMAT_DIRECT_REG_LIST_LENGTH, adev->gfx.rlc.reg_list_format_size_bytes >> 2, unique_indirect_regs, &unique_indirect_reg_count, ARRAY_SIZE(unique_indirect_regs), indirect_start_offsets, &indirect_start_offsets_count, ARRAY_SIZE(indirect_start_offsets));
   /* enable auto inc in case it is disabled */
   tmp = RREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL));
   tmp |= RLC_SRM_CNTL__AUTO_INCR_ADDR_MASK;
   WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_CNTL), tmp);
   /* write register_restore table to offset 0x0 using RLC_SRM_ARAM_ADDR/DATA */
   WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), RLC_SAVE_RESTORE_ADDR_STARTING_OFFSET);
   for (i = 0; i<adev->gfx.rlc.reg_list_size_bytes> > 2; i++)
     WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), adev->gfx.rlc.register_restore[i]);
   /* load direct register */
   WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_ADDR), 0);
   for (i = 0; i<adev->gfx.rlc.reg_list_size_bytes> > 2; i++)
     WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_ARAM_DATA), adev->gfx.rlc.register_restore[i]);
   /* load indirect register */
   WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), adev->gfx.rlc.reg_list_format_start);
   for (i = 0; i<adev->gfx.rlc.reg_list_format_size_bytes> > 2; i++)
     WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), register_list_format[i]);
   /* set save/restore list size */
   list_size = adev->gfx.rlc.reg_list_size_bytes >> 2;
   list_size = list_size >> 1;
   WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), adev->gfx.rlc.reg_restore_list_size);
   WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), list_size);
   /* write the starting offsets to RLC scratch ram */
   WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_ADDR), adev->gfx.rlc.starting_offsets_start);
-  for (i = 0; i < sizeof(indirect_start_offsets) / sizeof(int); i++)
+  for (i = 0; i < ARRAY_SIZE(indirect_start_offsets); i++)
     WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_GPM_SCRATCH_DATA), indirect_start_offsets[i]);
   /* load unique indirect regs*/
-  for (i = 0; i < sizeof(unique_indirect_regs) / sizeof(int); i++) {
+  for (i = 0; i < ARRAY_SIZE(unique_indirect_regs); i++) {
     WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_ADDR_0) + i, unique_indirect_regs[i] & 0x3FFFF);
     WREG32(SOC15_REG_OFFSET(GC, 0, mmRLC_SRM_INDEX_CNTL_DATA_0) + i, unique_indirect_regs[i] >> 20);
   }
   kfree(register_list_format);
   return 0;
 }<sep>@@
type T;
T[] E;
@@
- ((sizeof(E) /sizeof(T)))
+ ARRAY_SIZE(E)