--- initial
+++ final
@@ -1,76 +1,76 @@
 static void __init tsunami_init_one_pchip(tsunami_pchip *pchip, int index) {
   struct pci_controller *hose;
   if (tsunami_probe_read(&pchip->pctl.csr) == 0) return;
   hose = alloc_pci_controller();
   if (index == 0) pci_isa_hose = hose;
   hose->io_space = alloc_resource();
   hose->mem_space = alloc_resource();
   /* This is for userland consumption.  For some reason, the 40-bit
      PIO bias that we use in the kernel through KSEG didn't work for
      the page table based user mappings.  So make sure we get the
      43-bit PIO bias.  */
   hose->sparse_mem_base = 0;
   hose->sparse_io_base = 0;
   hose->dense_mem_base = (TSUNAMI_MEM(index) & 0xffffffffffL) | 0x80000000000L;
   hose->dense_io_base = (TSUNAMI_IO(index) & 0xffffffffffL) | 0x80000000000L;
   hose->config_space_base = TSUNAMI_CONF(index);
   hose->index = index;
   hose->io_space->start = TSUNAMI_IO(index) - TSUNAMI_IO_BIAS;
   hose->io_space->end = hose->io_space->start + TSUNAMI_IO_SPACE - 1;
   hose->io_space->name = pci_io_names[index];
   hose->io_space->flags = IORESOURCE_IO;
   hose->mem_space->start = TSUNAMI_MEM(index) - TSUNAMI_MEM_BIAS;
   hose->mem_space->end = hose->mem_space->start + 0xffffffff;
   hose->mem_space->name = pci_mem_names[index];
   hose->mem_space->flags = IORESOURCE_MEM;
   if (request_resource(&ioport_resource, hose->io_space) < 0) printk(KERN_ERR "Failed to request IO on hose %d\n", index);
   if (request_resource(&iomem_resource, hose->mem_space) < 0) printk(KERN_ERR "Failed to request MEM on hose %d\n", index);
   /*
    * Save the existing PCI window translations.  SRM will
    * need them when we go to reboot.
    */
   saved_config[index].wsba[0] = pchip->wsba[0].csr;
   saved_config[index].wsm[0] = pchip->wsm[0].csr;
   saved_config[index].tba[0] = pchip->tba[0].csr;
   saved_config[index].wsba[1] = pchip->wsba[1].csr;
   saved_config[index].wsm[1] = pchip->wsm[1].csr;
   saved_config[index].tba[1] = pchip->tba[1].csr;
   saved_config[index].wsba[2] = pchip->wsba[2].csr;
   saved_config[index].wsm[2] = pchip->wsm[2].csr;
   saved_config[index].tba[2] = pchip->tba[2].csr;
   saved_config[index].wsba[3] = pchip->wsba[3].csr;
   saved_config[index].wsm[3] = pchip->wsm[3].csr;
   saved_config[index].tba[3] = pchip->tba[3].csr;
   /*
    * Set up the PCI to main memory translation windows.
    *
    * Note: Window 3 is scatter-gather only
    *
    * Window 0 is scatter-gather 8MB at 8MB (for isa)
    * Window 1 is scatter-gather (up to) 1GB at 1GB
    * Window 2 is direct access 2GB at 2GB
    *
    * NOTE: we need the align_entry settings for Acer devices on ES40,
    * specifically floppy and IDE when memory is larger than 2GB.
    */
-  hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
+  hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, SMP_CACHE_BYTES);
   /* Initially set for 4 PTEs, but will be overridden to 64K for ISA. */
   hose->sg_isa->align_entry = 4;
-  hose->sg_pci = iommu_arena_new(hose, 0x40000000, size_for_memory(0x40000000), 0);
+  hose->sg_pci = iommu_arena_new(hose, 0x40000000, size_for_memory(0x40000000), SMP_CACHE_BYTES);
   hose->sg_pci->align_entry = 4; /* Tsunami caches 4 PTEs at a time */
   __direct_map_base = 0x80000000;
   __direct_map_size = 0x80000000;
   pchip->wsba[0].csr = hose->sg_isa->dma_base | 3;
   pchip->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000;
   pchip->tba[0].csr = virt_to_phys(hose->sg_isa->ptes);
   pchip->wsba[1].csr = hose->sg_pci->dma_base | 3;
   pchip->wsm[1].csr = (hose->sg_pci->size - 1) & 0xfff00000;
   pchip->tba[1].csr = virt_to_phys(hose->sg_pci->ptes);
   pchip->wsba[2].csr = 0x80000000 | 1;
   pchip->wsm[2].csr = (0x80000000 - 1) & 0xfff00000;
   pchip->tba[2].csr = 0;
   pchip->wsba[3].csr = 0;
   /* Enable the Monster Window to make DAC pci64 possible. */
   pchip->pctl.csr |= pctl_m_mwin;
   tsunami_pci_tbi(hose, 0, -1);
 }<sep>@@
expression hose, base, length;
@@

-	iommu_arena_new(hose, base, length, 0)
+	iommu_arena_new(hose, base, length, SMP_CACHE_BYTES)