--- initial
+++ final
@@ -1,135 +1,135 @@
 void __init trap_init(void) {
   extern char except_vec3_generic;
   extern char except_vec4;
   extern char except_vec3_r4000;
   unsigned long i;
   check_wait();
   if (cpu_has_veic || cpu_has_vint) {
     unsigned long size = 0x200 + VECTORSPACING * 64;
     phys_addr_t ebase_pa;
     memblock_set_bottom_up(true);
-    ebase = (unsigned long)__alloc_bootmem(size, 1 << fls(size), 0);
+    ebase = (unsigned long)memblock_alloc_from(size, 1 << fls(size), 0);
     memblock_set_bottom_up(false);
     /*
      * Try to ensure ebase resides in KSeg0 if possible.
      *
      * It shouldn't generally be in XKPhys on MIPS64 to avoid
      * hitting a poorly defined exception base for Cache Errors.
      * The allocation is likely to be in the low 512MB of physical,
      * in which case we should be able to convert to KSeg0.
      *
      * EVA is special though as it allows segments to be rearranged
      * and to become uncached during cache error handling.
      */
     ebase_pa = __pa(ebase);
     if (!IS_ENABLED(CONFIG_EVA) && !WARN_ON(ebase_pa >= 0x20000000)) ebase = CKSEG0ADDR(ebase_pa);
   } else {
     ebase = CAC_BASE;
     if (cpu_has_mips_r2_r6) {
       if (cpu_has_ebase_wg) {
 #ifdef CONFIG_64BIT
         ebase = (read_c0_ebase_64() & ~0xfff);
 #else
         ebase = (read_c0_ebase() & ~0xfff);
 #endif
       } else {
         ebase += (read_c0_ebase() & 0x3ffff000);
       }
     }
   }
   if (cpu_has_mmips) {
     unsigned int config3 = read_c0_config3();
     if (IS_ENABLED(CONFIG_CPU_MICROMIPS))
       write_c0_config3(config3 | MIPS_CONF3_ISA_OE);
     else
       write_c0_config3(config3 & ~MIPS_CONF3_ISA_OE);
   }
   if (board_ebase_setup) board_ebase_setup();
   per_cpu_trap_init(true);
   /*
    * Copy the generic exception handlers to their final destination.
    * This will be overridden later as suitable for a particular
    * configuration.
    */
   set_handler(0x180, &except_vec3_generic, 0x80);
   /*
    * Setup default vectors
    */
   for (i = 0; i <= 31; i++)
     set_except_vector(i, handle_reserved);
   /*
    * Copy the EJTAG debug exception vector handler code to it's final
    * destination.
    */
   if (cpu_has_ejtag && board_ejtag_handler_setup) board_ejtag_handler_setup();
   /*
    * Only some CPUs have the watch exceptions.
    */
   if (cpu_has_watch) set_except_vector(EXCCODE_WATCH, handle_watch);
   /*
    * Initialise interrupt handlers
    */
   if (cpu_has_veic || cpu_has_vint) {
     int nvec = cpu_has_veic ? 64 : 8;
     for (i = 0; i < nvec; i++)
       set_vi_handler(i, NULL);
   } else if (cpu_has_divec)
     set_handler(0x200, &except_vec4, 0x8);
   /*
    * Some CPUs can enable/disable for cache parity detection, but does
    * it different ways.
    */
   parity_protection_init();
   /*
    * The Data Bus Errors / Instruction Bus Errors are signaled
    * by external hardware.  Therefore these two exceptions
    * may have board specific handlers.
    */
   if (board_be_init) board_be_init();
   set_except_vector(EXCCODE_INT, using_rollback_handler() ? rollback_handle_int : handle_int);
   set_except_vector(EXCCODE_MOD, handle_tlbm);
   set_except_vector(EXCCODE_TLBL, handle_tlbl);
   set_except_vector(EXCCODE_TLBS, handle_tlbs);
   set_except_vector(EXCCODE_ADEL, handle_adel);
   set_except_vector(EXCCODE_ADES, handle_ades);
   set_except_vector(EXCCODE_IBE, handle_ibe);
   set_except_vector(EXCCODE_DBE, handle_dbe);
   set_except_vector(EXCCODE_SYS, handle_sys);
   set_except_vector(EXCCODE_BP, handle_bp);
   if (rdhwr_noopt)
     set_except_vector(EXCCODE_RI, handle_ri);
   else {
     if (cpu_has_vtag_icache)
       set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
     else if (current_cpu_type() == CPU_LOONGSON3)
       set_except_vector(EXCCODE_RI, handle_ri_rdhwr_tlbp);
     else
       set_except_vector(EXCCODE_RI, handle_ri_rdhwr);
   }
   set_except_vector(EXCCODE_CPU, handle_cpu);
   set_except_vector(EXCCODE_OV, handle_ov);
   set_except_vector(EXCCODE_TR, handle_tr);
   set_except_vector(EXCCODE_MSAFPE, handle_msa_fpe);
   if (board_nmi_handler_setup) board_nmi_handler_setup();
   if (cpu_has_fpu && !cpu_has_nofpuex) set_except_vector(EXCCODE_FPE, handle_fpe);
   set_except_vector(MIPS_EXCCODE_TLBPAR, handle_ftlb);
   if (cpu_has_rixiex) {
     set_except_vector(EXCCODE_TLBRI, tlb_do_page_fault_0);
     set_except_vector(EXCCODE_TLBXI, tlb_do_page_fault_0);
   }
   set_except_vector(EXCCODE_MSADIS, handle_msa);
   set_except_vector(EXCCODE_MDMX, handle_mdmx);
   if (cpu_has_mcheck) set_except_vector(EXCCODE_MCHECK, handle_mcheck);
   if (cpu_has_mipsmt) set_except_vector(EXCCODE_THREAD, handle_mt);
   set_except_vector(EXCCODE_DSPDIS, handle_dsp);
   if (board_cache_error_setup) board_cache_error_setup();
   if (cpu_has_vce) /* Special exception: R4[04]00 uses also the divec space. */
     set_handler(0x180, &except_vec3_r4000, 0x100);
   else if (cpu_has_4kex)
     set_handler(0x180, &except_vec3_generic, 0x80);
   else
     set_handler(0x080, &except_vec3_generic, 0x80);
   local_flush_icache_range(ebase, ebase + 0x400);
   sort_extable(__start___dbe_table, __stop___dbe_table);
   cu2_notifier(default_cu2_call, 0x80000000); /* Run last  */
 }<sep>@@
expression size, align, goal;
@@
- __alloc_bootmem(size, align, goal)
+ memblock_alloc_from(size, align, goal)