imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,11 +1,11 @@
 static void __init ls1021a_smp_prepare_cpus(unsigned int max_cpus) {
   struct device_node *np;
   void __iomem *dcfg_base;
   unsigned long paddr;
   np = of_find_compatible_node(NULL, NULL, "fsl,ls1021a-dcfg");
   dcfg_base = of_iomap(np, 0);
   BUG_ON(!dcfg_base);
-  paddr = virt_to_phys(secondary_startup);
+  paddr = __pa_symbol(secondary_startup);
   writel_relaxed(cpu_to_be32(paddr), dcfg_base + DCFG_CCSR_SCRATCHRW1);
   iounmap(dcfg_base);
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,30 +1,30 @@
 static void __init berlin_smp_prepare_cpus(unsigned int max_cpus) {
   struct device_node *np;
   void __iomem *scu_base;
   void __iomem *vectors_base;
   np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
   scu_base = of_iomap(np, 0);
   of_node_put(np);
   if (!scu_base) return;
   np = of_find_compatible_node(NULL, NULL, "marvell,berlin-cpu-ctrl");
   cpu_ctrl = of_iomap(np, 0);
   of_node_put(np);
   if (!cpu_ctrl) goto unmap_scu;
   vectors_base = ioremap(CONFIG_VECTORS_BASE, SZ_32K);
   if (!vectors_base) goto unmap_scu;
   scu_enable(scu_base);
   flush_cache_all();
   /*
    * Write the first instruction the CPU will execute after being reset
    * in the reset exception vector.
    */
   writel(boot_inst, vectors_base + RESET_VECT);
   /*
    * Write the secondary startup address into the SW reset address
    * vector. This is used by boot_inst.
    */
-  writel(virt_to_phys(secondary_startup), vectors_base + SW_RESET_ADDR);
+  writel(__pa_symbol(secondary_startup), vectors_base + SW_RESET_ADDR);
   iounmap(vectors_base);
 unmap_scu:
   iounmap(scu_base);
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,48 +1,48 @@
 static int sirfsoc_boot_secondary(unsigned int cpu, struct task_struct *idle) {
   unsigned long timeout;
   struct device_node *np;
   np = of_find_matching_node(NULL, clk_ids);
   if (!np) return -ENODEV;
   clk_base = of_iomap(np, 0);
   if (!clk_base) return -ENOMEM;
     /*
      * write the address of secondary startup into the clkc register
      * at offset 0x2bC, then write the magic number 0x3CAF5D62 to the
      * clkc register at offset 0x2b8, which is what boot rom code is
      * waiting for. This would wake up the secondary core from WFE
      */
 #define SIRFSOC_CPU1_JUMPADDR_OFFSET 0x2bc
-  __raw_writel(virt_to_phys(sirfsoc_secondary_startup), clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
+  __raw_writel(__pa_symbol(sirfsoc_secondary_startup), clk_base + SIRFSOC_CPU1_JUMPADDR_OFFSET);
 #define SIRFSOC_CPU1_WAKEMAGIC_OFFSET 0x2b8
   __raw_writel(0x3CAF5D62, clk_base + SIRFSOC_CPU1_WAKEMAGIC_OFFSET);
   /* make sure write buffer is drained */
   mb();
   spin_lock(&boot_lock);
   /*
    * The secondary processor is waiting to be released from
    * the holding pen - release it, then wait for it to flag
    * that it has been released by resetting pen_release.
    *
    * Note that "pen_release" is the hardware CPU ID, whereas
    * "cpu" is Linux's internal ID.
    */
   pen_release = cpu_logical_map(cpu);
   sync_cache_w(&pen_release);
   /*
    * Send the secondary CPU SEV, thereby causing the boot monitor to read
    * the JUMPADDR and WAKEMAGIC, and branch to the address found there.
    */
   dsb_sev();
   timeout = jiffies + (1 * HZ);
   while (time_before(jiffies, timeout)) {
     smp_rmb();
     if (pen_release == -1) break;
     udelay(10);
   }
   /*
    * now the secondary core is starting up let it run its
    * calibrations, then wait for it to finish
    */
   spin_unlock(&boot_lock);
   return pen_release != -1 ? -ENOSYS : 0;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,9 +1,9 @@
 static int alpine_boot_secondary(unsigned int cpu, struct task_struct *idle) {
   phys_addr_t addr;
-  addr = virt_to_phys(secondary_startup);
+  addr = __pa_symbol(secondary_startup);
   if (addr > (phys_addr_t)(uint32_t)(-1)) {
     pr_err("FAIL: resume address over 32bit (%pa)", &addr);
     return -EINVAL;
   }
   return alpine_cpu_wakeup(cpu_logical_map(cpu), (uint32_t)addr);
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,41 +1,41 @@
 static void __init sti_smp_prepare_cpus(unsigned int max_cpus) {
   struct device_node *np;
   void __iomem *scu_base;
   u32 __iomem *cpu_strt_ptr;
   u32 release_phys;
   int cpu;
-  unsigned long entry_pa = virt_to_phys(sti_secondary_startup);
+  unsigned long entry_pa = __pa_symbol(sti_secondary_startup);
   np = of_find_compatible_node(NULL, NULL, "arm,cortex-a9-scu");
   if (np) {
     scu_base = of_iomap(np, 0);
     scu_enable(scu_base);
     of_node_put(np);
   }
   if (max_cpus <= 1) return;
   for_each_possible_cpu(cpu) {
     np = of_get_cpu_node(cpu, NULL);
     if (!np) continue;
     if (of_property_read_u32(np, "cpu-release-addr", &release_phys)) {
       pr_err("CPU %d: missing or invalid cpu-release-addr "
              "property\n",
              cpu);
       continue;
     }
     /*
      * holding pen is usually configured in SBC DMEM but can also be
      * in RAM.
      */
     if (!memblock_is_memory(release_phys))
       cpu_strt_ptr = ioremap(release_phys, sizeof(release_phys));
     else
       cpu_strt_ptr = (u32 __iomem *)phys_to_virt(release_phys);
     __raw_writel(entry_pa, cpu_strt_ptr);
     /*
      * wmb so that data is actually written
      * before cache flush is done
      */
     smp_wmb();
     sync_cache_w(cpu_strt_ptr);
     if (!memblock_is_memory(release_phys)) iounmap(cpu_strt_ptr);
   }
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,5 +1,5 @@
 static int shmobile_scu_cpu_prepare(unsigned int cpu) {
   /* For this particular CPU register SCU SMP boot vector */
-  shmobile_smp_hook(cpu, virt_to_phys(shmobile_boot_scu), shmobile_scu_base_phys);
+  shmobile_smp_hook(cpu, __pa_symbol(shmobile_boot_scu), shmobile_scu_base_phys);
   return 0;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,31 +1,31 @@
 static void pxa3xx_cpu_pm_suspend(void) {
   volatile unsigned long *p = (volatile void *)0xc0000000;
   unsigned long saved_data = *p;
 #ifndef CONFIG_IWMMXT
   u64 acc0;
   asm volatile(".arch_extension xscale\n\t"
                "mra %Q0, %R0, acc0"
                : "=r"(acc0));
 #endif
   /* resuming from D2 requires the HSIO2/BOOT/TPM clocks enabled */
   CKENA |= (1 << CKEN_BOOT) | (1 << CKEN_TPM);
   CKENB |= 1 << (CKEN_HSIO2 & 0x1f);
   /* clear and setup wakeup source */
   AD3SR = ~0;
   AD3ER = wakeup_src;
   ASCR = ASCR;
   ARSR = ARSR;
   PCFR |= (1u << 13);                /* L1_DIS */
   PCFR &= ~((1u << 12) | (1u << 1)); /* L0_EN | SL_ROD */
   PSPR = 0x5c014000;
   /* overwrite with the resume address */
-  *p = virt_to_phys(cpu_resume);
+  *p = __pa_symbol(cpu_resume);
   cpu_suspend(0, pxa3xx_finish_suspend);
   *p = saved_data;
   AD3ER = 0;
 #ifndef CONFIG_IWMMXT
   asm volatile(".arch_extension xscale\n\t"
                "mar acc0, %Q0, %R0"
                : "=r"(acc0));
 #endif
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,45 +1,45 @@
 void __init zx_smp_prepare_cpus(unsigned int max_cpus) {
   struct device_node *np;
   unsigned long base = 0;
   void __iomem *aonsysctrl_base;
   void __iomem *sys_iram;
   base = scu_a9_get_base();
   scu_base = ioremap(base, SZ_256);
   if (!scu_base) {
     pr_err("%s: failed to map scu\n", __func__);
     return;
   }
   scu_enable(scu_base);
   np = of_find_compatible_node(NULL, NULL, "zte,sysctrl");
   if (!np) {
     pr_err("%s: failed to find sysctrl node\n", __func__);
     return;
   }
   aonsysctrl_base = of_iomap(np, 0);
   if (!aonsysctrl_base) {
     pr_err("%s: failed to map aonsysctrl\n", __func__);
     of_node_put(np);
     return;
   }
   /*
    * Write the address of secondary startup into the
    * system-wide flags register. The BootMonitor waits
    * until it receives a soft interrupt, and then the
    * secondary CPU branches to this address.
    */
-  __raw_writel(virt_to_phys(zx_secondary_startup), aonsysctrl_base + AON_SYS_CTRL_RESERVED1);
+  __raw_writel(__pa_symbol(zx_secondary_startup), aonsysctrl_base + AON_SYS_CTRL_RESERVED1);
   iounmap(aonsysctrl_base);
   of_node_put(np);
   np = of_find_compatible_node(NULL, NULL, "zte,zx296702-pcu");
   pcu_base = of_iomap(np, 0);
   of_node_put(np);
   WARN_ON(!pcu_base);
   np = of_find_compatible_node(NULL, NULL, "zte,zx-bus-matrix");
   matrix_base = of_iomap(np, 0);
   of_node_put(np);
   WARN_ON(!matrix_base);
   /* Map the first 4 KB IRAM for suspend usage */
   sys_iram = __arm_ioremap_exec(ZX_IRAM_BASE, PAGE_SIZE, false);
-  zx_secondary_startup_pa = virt_to_phys(zx_secondary_startup);
+  zx_secondary_startup_pa = __pa_symbol(zx_secondary_startup);
   fncpy(sys_iram, &zx_resume_jump, zx_suspend_iram_sz);
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,11 +1,11 @@
 static void exynos_mcpm_setup_entry_point(void) {
   /*
    * U-Boot SPL is hardcoded to jump to the start of ns_sram_base_addr
    * as part of secondary_cpu_start().  Let's redirect it to the
    * mcpm_entry_point(). This is done during both secondary boot-up as
    * well as system resume.
    */
   __raw_writel(0xe59f0000, ns_sram_base_addr);     /* ldr r0, [pc, #0] */
   __raw_writel(0xe12fff10, ns_sram_base_addr + 4); /* bx  r0 */
-  __raw_writel(virt_to_phys(mcpm_entry_point), ns_sram_base_addr + 8);
+  __raw_writel(__pa_symbol(mcpm_entry_point), ns_sram_base_addr + 8);
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,18 +1,18 @@
 static int hip01_boot_secondary(unsigned int cpu, struct task_struct *idle) {
   phys_addr_t jumpaddr;
   unsigned int remap_reg_value = 0;
   struct device_node *node;
-  jumpaddr = virt_to_phys(secondary_startup);
+  jumpaddr = __pa_symbol(secondary_startup);
   hip01_set_boot_addr(HIP01_BOOT_ADDRESS, jumpaddr);
   node = of_find_compatible_node(NULL, NULL, "hisilicon,hip01-sysctrl");
   if (WARN_ON(!node)) return -1;
   ctrl_base = of_iomap(node, 0);
   /* set the secondary core boot from DDR */
   remap_reg_value = readl_relaxed(ctrl_base + REG_SC_CTRL);
   barrier();
   remap_reg_value |= SC_SCTL_REMAP_CLR;
   barrier();
   writel_relaxed(remap_reg_value, ctrl_base + REG_SC_CTRL);
   hip01_set_cpu(cpu, true);
   return 0;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,17 +1,17 @@
 static int __init nocache_trampoline(unsigned long _arg) {
   void (*cache_disable)(void) = (void *)_arg;
   unsigned int mpidr = read_cpuid_mpidr();
   unsigned int cpu = MPIDR_AFFINITY_LEVEL(mpidr, 0);
   unsigned int cluster = MPIDR_AFFINITY_LEVEL(mpidr, 1);
   phys_reset_t phys_reset;
   mcpm_set_entry_vector(cpu, cluster, cpu_resume);
   setup_mm_for_reboot();
   __mcpm_cpu_going_down(cpu, cluster);
   BUG_ON(!__mcpm_outbound_enter_critical(cpu, cluster));
   cache_disable();
   __mcpm_outbound_leave_critical(cluster, CLUSTER_DOWN);
   __mcpm_cpu_down(cpu, cluster);
-  phys_reset = (phys_reset_t)(unsigned long)virt_to_phys(cpu_reset);
-  phys_reset(virt_to_phys(mcpm_entry_point));
+  phys_reset = (phys_reset_t)(unsigned long)__pa_symbol(cpu_reset);
+  phys_reset(__pa_symbol(mcpm_entry_point));
   BUG();
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,58 +1,58 @@
 int omap4_enter_lowpower(unsigned int cpu, unsigned int power_state) {
   struct omap4_cpu_pm_info *pm_info = &per_cpu(omap4_pm_info, cpu);
   unsigned int save_state = 0, cpu_logic_state = PWRDM_POWER_RET;
   unsigned int wakeup_cpu;
   if (omap_rev() == OMAP4430_REV_ES1_0) return -ENXIO;
   switch (power_state) {
   case PWRDM_POWER_ON:
   case PWRDM_POWER_INACTIVE: save_state = 0; break;
   case PWRDM_POWER_OFF:
     cpu_logic_state = PWRDM_POWER_OFF;
     save_state = 1;
     break;
   case PWRDM_POWER_RET:
     if (IS_PM44XX_ERRATUM(PM_OMAP4_CPU_OSWR_DISABLE)) save_state = 0;
     break;
   default:
     /*
      * CPUx CSWR is invalid hardware state. Also CPUx OSWR
      * doesn't make much scense, since logic is lost and $L1
      * needs to be cleaned because of coherency. This makes
      * CPUx OSWR equivalent to CPUX OFF and hence not supported
      */
     WARN_ON(1);
     return -ENXIO;
   }
   pwrdm_pre_transition(NULL);
   /*
    * Check MPUSS next state and save interrupt controller if needed.
    * In MPUSS OSWR or device OFF, interrupt controller  contest is lost.
    */
   mpuss_clear_prev_logic_pwrst();
   if ((pwrdm_read_next_pwrst(mpuss_pd) == PWRDM_POWER_RET) && (pwrdm_read_logic_retst(mpuss_pd) == PWRDM_POWER_OFF)) save_state = 2;
   cpu_clear_prev_logic_pwrst(cpu);
   pwrdm_set_next_pwrst(pm_info->pwrdm, power_state);
   pwrdm_set_logic_retst(pm_info->pwrdm, cpu_logic_state);
-  set_cpu_wakeup_addr(cpu, virt_to_phys(omap_pm_ops.resume));
+  set_cpu_wakeup_addr(cpu, __pa_symbol(omap_pm_ops.resume));
   omap_pm_ops.scu_prepare(cpu, power_state);
   l2x0_pwrst_prepare(cpu, save_state);
   /*
    * Call low level function  with targeted low power state.
    */
   if (save_state)
     cpu_suspend(save_state, omap_pm_ops.finish_suspend);
   else
     omap_pm_ops.finish_suspend(save_state);
   if (IS_PM44XX_ERRATUM(PM_OMAP4_ROM_SMP_BOOT_ERRATUM_GICD) && cpu) gic_dist_enable();
   /*
    * Restore the CPUx power state to ON otherwise CPUx
    * power domain can transitions to programmed low power
    * state while doing WFI outside the low powe code. On
    * secure devices, CPUx does WFI which can result in
    * domain transition
    */
   wakeup_cpu = smp_processor_id();
   pwrdm_set_next_pwrst(pm_info->pwrdm, PWRDM_POWER_ON);
   pwrdm_post_transition(NULL);
   return 0;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,14 +1,14 @@
 static int socfpga_a10_boot_secondary(unsigned int cpu, struct task_struct *idle) {
   int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
   if (socfpga_cpu1start_addr) {
     writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST);
     memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
-    writel(virt_to_phys(secondary_startup), sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff));
+    writel(__pa_symbol(secondary_startup), sys_manager_base_addr + (socfpga_cpu1start_addr & 0x00000fff));
     flush_cache_all();
     smp_wmb();
     outer_clean_range(0, trampoline_size);
     /* This will release CPU #1 out of reset. */
     writel(0, rst_manager_base_addr + SOCFPGA_A10_RSTMGR_MODMPURST);
   }
   return 0;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,39 +1,39 @@
 static int kona_boot_secondary(unsigned int cpu, struct task_struct *idle) {
   void __iomem *boot_reg;
   phys_addr_t boot_func;
   u64 start_clock;
   u32 cpu_id;
   u32 boot_val;
   bool timeout = false;
   const u32 secondary_boot_addr = secondary_boot_addr_for(cpu);
   cpu_id = cpu_logical_map(cpu);
   if (cpu_id & ~BOOT_ADDR_CPUID_MASK) {
     pr_err("bad cpu id (%u > %u)\n", cpu_id, BOOT_ADDR_CPUID_MASK);
     return -EINVAL;
   }
   if (!secondary_boot_addr) return -EINVAL;
   boot_reg = ioremap_nocache((phys_addr_t)secondary_boot_addr, sizeof(phys_addr_t));
   if (!boot_reg) {
     pr_err("unable to map boot register for cpu %u\n", cpu_id);
     return -ENOMEM;
   }
   /*
    * Secondary cores will start in secondary_startup(),
    * defined in "arch/arm/kernel/head.S"
    */
-  boot_func = virt_to_phys(secondary_startup);
+  boot_func = __pa_symbol(secondary_startup);
   BUG_ON(boot_func & BOOT_ADDR_CPUID_MASK);
   BUG_ON(boot_func > (phys_addr_t)U32_MAX);
   /* The core to start is encoded in the low bits */
   boot_val = (u32)boot_func | cpu_id;
   writel_relaxed(boot_val, boot_reg);
   sev();
   /* The low bits will be cleared once the core has started */
   start_clock = local_clock();
   while (!timeout && readl_relaxed(boot_reg) == boot_val)
     timeout = local_clock() - start_clock > SECONDARY_TIMEOUT_NS;
   iounmap(boot_reg);
   if (!timeout) return 0;
   pr_err("timeout waiting for cpu %u to start\n", cpu_id);
   return -ENXIO;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1 +1 @@
-static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle) { return zynq_cpun_start(virt_to_phys(secondary_startup), cpu); }
+static int zynq_boot_secondary(unsigned int cpu, struct task_struct *idle) { return zynq_cpun_start(__pa_symbol(secondary_startup), cpu); }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,17 +1,17 @@
 void __init omap4_mpuss_early_init(void) {
   unsigned long startup_pa;
   if (!(cpu_is_omap44xx() || soc_is_omap54xx())) return;
   sar_base = omap4_get_sar_ram_base();
   if (cpu_is_omap443x())
-    startup_pa = virt_to_phys(omap4_secondary_startup);
+    startup_pa = __pa_symbol(omap4_secondary_startup);
   else if (cpu_is_omap446x())
-    startup_pa = virt_to_phys(omap4460_secondary_startup);
+    startup_pa = __pa_symbol(omap4460_secondary_startup);
   else if ((__boot_cpu_mode & MODE_MASK) == HYP_MODE)
-    startup_pa = virt_to_phys(omap5_secondary_hyp_startup);
+    startup_pa = __pa_symbol(omap5_secondary_hyp_startup);
   else
-    startup_pa = virt_to_phys(omap5_secondary_startup);
+    startup_pa = __pa_symbol(omap5_secondary_startup);
   if (cpu_is_omap44xx())
     writel_relaxed(startup_pa, sar_base + CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
   else
     writel_relaxed(startup_pa, sar_base + OMAP5_CPU1_WAKEUP_NS_PA_ADDR_OFFSET);
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,15 +1,15 @@
 static int socfpga_boot_secondary(unsigned int cpu, struct task_struct *idle) {
   int trampoline_size = &secondary_trampoline_end - &secondary_trampoline;
   if (socfpga_cpu1start_addr) {
     /* This will put CPU #1 into reset. */
     writel(RSTMGR_MPUMODRST_CPU1, rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
     memcpy(phys_to_virt(0), &secondary_trampoline, trampoline_size);
-    writel(virt_to_phys(secondary_startup), sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
+    writel(__pa_symbol(secondary_startup), sys_manager_base_addr + (socfpga_cpu1start_addr & 0x000000ff));
     flush_cache_all();
     smp_wmb();
     outer_clean_range(0, trampoline_size);
     /* This will release CPU #1 out of reset. */
     writel(0, rst_manager_base_addr + SOCFPGA_RSTMGR_MODMPURST);
   }
   return 0;
 }<sep>@@
expression e;
@@

- virt_to_phys
+ __pa_symbol
   (e)
--- initial
+++ final
@@ -1,13 +1,10 @@
 static void snd_mpu401_uart_add_timer(struct snd_mpu401 *mpu, int input) {
   unsigned long flags;
   spin_lock_irqsave(&mpu->timer_lock, flags);
   if (mpu->timer_invoked == 0) {
-    init_timer(&mpu->timer);
-    mpu->timer.data = (unsigned long)mpu;
-    mpu->timer.function = snd_mpu401_uart_timer;
-    mpu->timer.expires = 1 + jiffies;
-    add_timer(&mpu->timer);
+    setup_timer(&mpu->timer, snd_mpu401_uart_timer, (unsigned long)mpu);
+    mod_timer(&mpu->timer, 1 + jiffies);
   }
   mpu->timer_invoked |= input ? MPU401_MODE_INPUT_TIMER : MPU401_MODE_OUTPUT_TIMER;
   spin_unlock_irqrestore(&mpu->timer_lock, flags);
 }<sep>@@
expression E0;
expression E1,e1;
expression E2;
@@
- init_timer(&E0);
+ setup_timer(&E0, E1, E2);
  ... when != E0.function = e1;
- E0.data = E2;
  ... when != init_timer(&E0);
- E0.function = E1;

@@
expression E0,v;
@@

-	E0.expires = v;
	...
-	add_timer(&E0);
+	mod_timer(&E0, v);
--- initial
+++ final
@@ -1,20 +1,17 @@
 static void snd_sb8dsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) {
   unsigned long flags;
   struct snd_sb *chip;
   chip = substream->rmidi->private_data;
   spin_lock_irqsave(&chip->open_lock, flags);
   if (up) {
     if (!(chip->open & SB_OPEN_MIDI_OUTPUT_TRIGGER)) {
-      init_timer(&chip->midi_timer);
-      chip->midi_timer.function = snd_sb8dsp_midi_output_timer;
-      chip->midi_timer.data = (unsigned long)substream;
-      chip->midi_timer.expires = 1 + jiffies;
-      add_timer(&chip->midi_timer);
+      setup_timer(&chip->midi_timer, snd_sb8dsp_midi_output_timer, (unsigned long)substream);
+      mod_timer(&chip->midi_timer, 1 + jiffies);
       chip->open |= SB_OPEN_MIDI_OUTPUT_TRIGGER;
     }
   } else {
     if (chip->open & SB_OPEN_MIDI_OUTPUT_TRIGGER) { chip->open &= ~SB_OPEN_MIDI_OUTPUT_TRIGGER; }
   }
   spin_unlock_irqrestore(&chip->open_lock, flags);
   if (up) snd_sb8dsp_midi_output_write(substream);
 }<sep>@@
expression E0;
expression E1;
expression E2,e2;
@@
- init_timer(&E0);
+ setup_timer(&E0, E1, E2);
  ... when != E0.data = e2;
- E0.function = E1;
  ... when != init_timer(&E0);
- E0.data = E2;



@@
expression E0,v;
@@

-	E0.expires = v;
	...
-	add_timer(&E0);
+	mod_timer(&E0, v);
--- initial
+++ final
@@ -1,18 +1,17 @@
 static int srmcons_open(struct tty_struct *tty, struct file *filp) {
   struct srmcons_private *srmconsp;
   unsigned long flags;
   int retval;
   retval = srmcons_get_private_struct(&srmconsp);
   if (retval) return retval;
   spin_lock_irqsave(&srmconsp->lock, flags);
   if (!srmconsp->tty) {
     tty->driver_data = srmconsp;
     srmconsp->tty = tty;
     srmconsp->timer.function = srmcons_receive_chars;
     srmconsp->timer.data = (unsigned long)srmconsp;
-    srmconsp->timer.expires = jiffies + 10;
-    add_timer(&srmconsp->timer);
+    mod_timer(&srmconsp->timer, jiffies + 10);
   }
   spin_unlock_irqrestore(&srmconsp->lock, flags);
   return 0;
 }<sep>@@
expression E0,v;
@@

-	E0.expires = v;
	...
-	add_timer(&E0);
+	mod_timer(&E0, v);
--- initial
+++ final
@@ -1,20 +1,17 @@
 static void snd_hdsp_midi_output_trigger(struct snd_rawmidi_substream *substream, int up) {
   struct hdsp_midi *hmidi;
   unsigned long flags;
   hmidi = (struct hdsp_midi *)substream->rmidi->private_data;
   spin_lock_irqsave(&hmidi->lock, flags);
   if (up) {
     if (!hmidi->istimer) {
-      init_timer(&hmidi->timer);
-      hmidi->timer.function = snd_hdsp_midi_output_timer;
-      hmidi->timer.data = (unsigned long)hmidi;
-      hmidi->timer.expires = 1 + jiffies;
-      add_timer(&hmidi->timer);
+      setup_timer(&hmidi->timer, snd_hdsp_midi_output_timer, (unsigned long)hmidi);
+      mod_timer(&hmidi->timer, 1 + jiffies);
       hmidi->istimer++;
     }
   } else {
     if (hmidi->istimer && --hmidi->istimer <= 0) del_timer(&hmidi->timer);
   }
   spin_unlock_irqrestore(&hmidi->lock, flags);
   if (up) snd_hdsp_midi_output_write(hmidi);
 }<sep>@@
expression E0;
expression E1;
expression E2,e2;
@@
- init_timer(&E0);
+ setup_timer(&E0, E1, E2);
  ... when != E0.data = e2;
- E0.function = E1;
  ... when != init_timer(&E0);
- E0.data = E2;



@@
expression E0,v;
@@

-	E0.expires = v;
	...
-	add_timer(&E0);
+	mod_timer(&E0, v);