--- initial
+++ final
@@ -1,100 +1,100 @@
 static irqreturn_t gen8_de_irq_handler(struct drm_i915_private *dev_priv, u32 master_ctl) {
   irqreturn_t ret = IRQ_NONE;
   u32 iir;
   enum pipe pipe;
   if (master_ctl & GEN8_DE_MISC_IRQ) {
     iir = I915_READ(GEN8_DE_MISC_IIR);
     if (iir) {
       I915_WRITE(GEN8_DE_MISC_IIR, iir);
       ret = IRQ_HANDLED;
       if (iir & GEN8_DE_MISC_GSE)
         intel_opregion_asle_intr(dev_priv);
       else
         DRM_ERROR("Unexpected DE Misc interrupt\n");
     } else
       DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
   }
   if (master_ctl & GEN8_DE_PORT_IRQ) {
     iir = I915_READ(GEN8_DE_PORT_IIR);
     if (iir) {
       u32 tmp_mask;
       bool found = false;
       I915_WRITE(GEN8_DE_PORT_IIR, iir);
       ret = IRQ_HANDLED;
       tmp_mask = GEN8_AUX_CHANNEL_A;
       if (INTEL_INFO(dev_priv)->gen >= 9) tmp_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D;
       if (iir & tmp_mask) {
         dp_aux_irq_handler(dev_priv);
         found = true;
       }
-      if (IS_BROXTON(dev_priv)) {
+      if (IS_GEN9_LP(dev_priv)) {
         tmp_mask = iir & BXT_DE_PORT_HOTPLUG_MASK;
         if (tmp_mask) {
           bxt_hpd_irq_handler(dev_priv, tmp_mask, hpd_bxt);
           found = true;
         }
       } else if (IS_BROADWELL(dev_priv)) {
         tmp_mask = iir & GEN8_PORT_DP_A_HOTPLUG;
         if (tmp_mask) {
           ilk_hpd_irq_handler(dev_priv, tmp_mask, hpd_bdw);
           found = true;
         }
       }
-      if (IS_BROXTON(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
+      if (IS_GEN9_LP(dev_priv) && (iir & BXT_DE_PORT_GMBUS)) {
         gmbus_irq_handler(dev_priv);
         found = true;
       }
       if (!found) DRM_ERROR("Unexpected DE Port interrupt\n");
     } else
       DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
   }
   for_each_pipe(dev_priv, pipe) {
     u32 flip_done, fault_errors;
     if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe))) continue;
     iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
     if (!iir) {
       DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
       continue;
     }
     ret = IRQ_HANDLED;
     I915_WRITE(GEN8_DE_PIPE_IIR(pipe), iir);
     if (iir & GEN8_PIPE_VBLANK && intel_pipe_handle_vblank(dev_priv, pipe)) intel_check_page_flip(dev_priv, pipe);
     flip_done = iir;
     if (INTEL_INFO(dev_priv)->gen >= 9)
       flip_done &= GEN9_PIPE_PLANE1_FLIP_DONE;
     else
       flip_done &= GEN8_PIPE_PRIMARY_FLIP_DONE;
     if (flip_done) intel_finish_page_flip_cs(dev_priv, pipe);
     if (iir & GEN8_PIPE_CDCLK_CRC_DONE) hsw_pipe_crc_irq_handler(dev_priv, pipe);
     if (iir & GEN8_PIPE_FIFO_UNDERRUN) intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
     fault_errors = iir;
     if (INTEL_INFO(dev_priv)->gen >= 9)
       fault_errors &= GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
     else
       fault_errors &= GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
     if (fault_errors) DRM_ERROR("Fault errors on pipe %c: 0x%08x\n", pipe_name(pipe), fault_errors);
   }
   if (HAS_PCH_SPLIT(dev_priv) && !HAS_PCH_NOP(dev_priv) && master_ctl & GEN8_DE_PCH_IRQ) {
     /*
      * FIXME(BDW): Assume for now that the new interrupt handling
      * scheme also closed the SDE interrupt handling race we've seen
      * on older pch-split platforms. But this needs testing.
      */
     iir = I915_READ(SDEIIR);
     if (iir) {
       I915_WRITE(SDEIIR, iir);
       ret = IRQ_HANDLED;
       if (HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv))
         spt_irq_handler(dev_priv, iir);
       else
         cpt_irq_handler(dev_priv, iir);
     } else {
       /*
        * Like on previous PCH there seems to be something
        * fishy going on with forwarding PCH interrupts.
        */
       DRM_DEBUG_DRIVER("The master control interrupt lied (SDE)!\n");
     }
   }
   return ret;
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)