imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,69 +1,69 @@
 static int gmc_v8_0_sw_init(void *handle) {
   int r;
   int dma_bits;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   if (adev->flags & AMD_IS_APU) {
     adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
   } else {
     u32 tmp;
     if (adev->asic_type == CHIP_FIJI)
       tmp = RREG32(mmMC_SEQ_MISC0_FIJI);
     else
       tmp = RREG32(mmMC_SEQ_MISC0);
     tmp &= MC_SEQ_MISC0__MT__MASK;
     adev->mc.vram_type = gmc_v8_0_convert_vram_type(tmp);
   }
-  r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
   if (r) return r;
-  r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
   if (r) return r;
   /* Adjust VM size here.
    * Currently set to 4GB ((1 << 20) 4k pages).
    * Max GPUVM size for cayman and SI is 40 bits.
    */
   adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
   /* Set the internal MC address mask
    * This is the max address of the GPU's
    * internal address space.
    */
   adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
   /* set DMA mask + need_dma32 flags.
    * PCIE - can handle 40-bits.
    * IGP - can handle 40-bits
    * PCI - dma32 for legacy pci gart, 40 bits on newer asics
    */
   adev->need_dma32 = false;
   dma_bits = adev->need_dma32 ? 32 : 40;
   r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
   if (r) {
     adev->need_dma32 = true;
     dma_bits = 32;
     pr_warn("amdgpu: No suitable DMA available\n");
   }
   r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
   if (r) {
     pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
     pr_warn("amdgpu: No coherent DMA available\n");
   }
   r = gmc_v8_0_init_microcode(adev);
   if (r) {
     DRM_ERROR("Failed to load mc firmware!\n");
     return r;
   }
   r = gmc_v8_0_mc_init(adev);
   if (r) return r;
   /* Memory manager */
   r = amdgpu_bo_init(adev);
   if (r) return r;
   r = gmc_v8_0_gart_init(adev);
   if (r) return r;
   if (!adev->vm_manager.enabled) {
     r = gmc_v8_0_vm_init(adev);
     if (r) {
       dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
       return r;
     }
     adev->vm_manager.enabled = true;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,32 +1,32 @@
 static int kv_dpm_sw_init(void *handle) {
   int ret;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-  ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
+  ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
   if (ret) return ret;
-  ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
+  ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
   if (ret) return ret;
   /* default to balanced state */
   adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
   adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
   adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
   adev->pm.default_sclk = adev->clock.default_sclk;
   adev->pm.default_mclk = adev->clock.default_mclk;
   adev->pm.current_sclk = adev->clock.default_sclk;
   adev->pm.current_mclk = adev->clock.default_mclk;
   adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
   if (amdgpu_dpm == 0) return 0;
   INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
   mutex_lock(&adev->pm.mutex);
   ret = kv_dpm_init(adev);
   if (ret) goto dpm_failed;
   adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
   if (amdgpu_dpm == 1) amdgpu_pm_print_power_states(adev);
   mutex_unlock(&adev->pm.mutex);
   DRM_INFO("amdgpu: dpm initialized\n");
   return 0;
 dpm_failed:
   kv_dpm_fini(adev);
   mutex_unlock(&adev->pm.mutex);
   DRM_ERROR("amdgpu: dpm initialization failed\n");
   return ret;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,11 +1,11 @@
 int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev) {
   int r;
-  r = amdgpu_irq_add_id(adev, 135, &adev->virt.rcv_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 135, &adev->virt.rcv_irq);
   if (r) return r;
-  r = amdgpu_irq_add_id(adev, 138, &adev->virt.ack_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 138, &adev->virt.ack_irq);
   if (r) {
     amdgpu_irq_put(adev, &adev->virt.rcv_irq, 0);
     return r;
   }
   return 0;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,28 +1,28 @@
 static int sdma_v2_4_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   /* SDMA trap event */
-  r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, &adev->sdma.trap_irq);
   if (r) return r;
   /* SDMA Privileged inst */
-  r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, &adev->sdma.illegal_inst_irq);
   if (r) return r;
   /* SDMA Privileged inst */
-  r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, &adev->sdma.illegal_inst_irq);
   if (r) return r;
   r = sdma_v2_4_init_microcode(adev);
   if (r) {
     DRM_ERROR("Failed to load sdma firmware!\n");
     return r;
   }
   for (i = 0; i < adev->sdma.num_instances; i++) {
     ring = &adev->sdma.instance[i].ring;
     ring->ring_obj = NULL;
     ring->use_doorbell = false;
     sprintf(ring->name, "sdma%d", i);
     r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, (i == 0) ? AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1);
     if (r) return r;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,29 +1,29 @@
 static int sdma_v3_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   /* SDMA trap event */
-  r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, &adev->sdma.trap_irq);
   if (r) return r;
   /* SDMA Privileged inst */
-  r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, &adev->sdma.illegal_inst_irq);
   if (r) return r;
   /* SDMA Privileged inst */
-  r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, &adev->sdma.illegal_inst_irq);
   if (r) return r;
   r = sdma_v3_0_init_microcode(adev);
   if (r) {
     DRM_ERROR("Failed to load sdma firmware!\n");
     return r;
   }
   for (i = 0; i < adev->sdma.num_instances; i++) {
     ring = &adev->sdma.instance[i].ring;
     ring->ring_obj = NULL;
     ring->use_doorbell = true;
     ring->doorbell_index = (i == 0) ? AMDGPU_DOORBELL_sDMA_ENGINE0 : AMDGPU_DOORBELL_sDMA_ENGINE1;
     sprintf(ring->name, "sdma%d", i);
     r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, (i == 0) ? AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1);
     if (r) return r;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,20 +1,20 @@
 static int si_dma_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   /* DMA0 trap event */
-  r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, &adev->sdma.trap_irq);
   if (r) return r;
   /* DMA1 trap event */
-  r = amdgpu_irq_add_id(adev, 244, &adev->sdma.trap_irq_1);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 244, &adev->sdma.trap_irq_1);
   if (r) return r;
   for (i = 0; i < adev->sdma.num_instances; i++) {
     ring = &adev->sdma.instance[i].ring;
     ring->ring_obj = NULL;
     ring->use_doorbell = false;
     sprintf(ring->name, "sdma%d", i);
     r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, (i == 0) ? AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1);
     if (r) return r;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,34 +1,34 @@
 static int si_dpm_sw_init(void *handle) {
   int ret;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-  ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
+  ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
   if (ret) return ret;
-  ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
+  ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
   if (ret) return ret;
   /* default to balanced state */
   adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
   adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
   adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
   adev->pm.default_sclk = adev->clock.default_sclk;
   adev->pm.default_mclk = adev->clock.default_mclk;
   adev->pm.current_sclk = adev->clock.default_sclk;
   adev->pm.current_mclk = adev->clock.default_mclk;
   adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
   if (amdgpu_dpm == 0) return 0;
   ret = si_dpm_init_microcode(adev);
   if (ret) return ret;
   INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
   mutex_lock(&adev->pm.mutex);
   ret = si_dpm_init(adev);
   if (ret) goto dpm_failed;
   adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
   if (amdgpu_dpm == 1) amdgpu_pm_print_power_states(adev);
   mutex_unlock(&adev->pm.mutex);
   DRM_INFO("amdgpu: dpm initialized\n");
   return 0;
 dpm_failed:
   si_dpm_fini(adev);
   mutex_unlock(&adev->pm.mutex);
   DRM_ERROR("amdgpu: dpm initialization failed\n");
   return ret;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,16 +1,16 @@
 static int uvd_v4_2_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   int r;
   /* UVD TRAP */
-  r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
   if (r) return r;
   r = amdgpu_uvd_sw_init(adev);
   if (r) return r;
   r = amdgpu_uvd_resume(adev);
   if (r) return r;
   ring = &adev->uvd.ring;
   sprintf(ring->name, "uvd");
   r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,16 +1,16 @@
 static int uvd_v5_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   int r;
   /* UVD TRAP */
-  r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
   if (r) return r;
   r = amdgpu_uvd_sw_init(adev);
   if (r) return r;
   r = amdgpu_uvd_resume(adev);
   if (r) return r;
   ring = &adev->uvd.ring;
   sprintf(ring->name, "uvd");
   r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,16 +1,16 @@
 static int uvd_v6_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   int r;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   /* UVD TRAP */
-  r = amdgpu_irq_add_id(adev, 124, &adev->uvd.irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
   if (r) return r;
   r = amdgpu_uvd_sw_init(adev);
   if (r) return r;
   r = amdgpu_uvd_resume(adev);
   if (r) return r;
   ring = &adev->uvd.ring;
   sprintf(ring->name, "uvd");
   r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,19 +1,19 @@
 static int vce_v2_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   /* VCE */
-  r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 167, &adev->vce.irq);
   if (r) return r;
   r = amdgpu_vce_sw_init(adev, VCE_V2_0_FW_SIZE + VCE_V2_0_STACK_SIZE + VCE_V2_0_DATA_SIZE);
   if (r) return r;
   r = amdgpu_vce_resume(adev);
   if (r) return r;
   for (i = 0; i < adev->vce.num_rings; i++) {
     ring = &adev->vce.ring[i];
     sprintf(ring->name, "vce%d", i);
     r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0);
     if (r) return r;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,21 +1,21 @@
 static int vce_v3_0_sw_init(void *handle) {
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   struct amdgpu_ring *ring;
   int r, i;
   /* VCE */
-  r = amdgpu_irq_add_id(adev, 167, &adev->vce.irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 167, &adev->vce.irq);
   if (r) return r;
   r = amdgpu_vce_sw_init(adev, VCE_V3_0_FW_SIZE + (VCE_V3_0_STACK_SIZE + VCE_V3_0_DATA_SIZE) * 2);
   if (r) return r;
   /* 52.8.3 required for 3 ring support */
   if (adev->vce.fw_version < FW_52_8_3) adev->vce.num_rings = 2;
   r = amdgpu_vce_resume(adev);
   if (r) return r;
   for (i = 0; i < adev->vce.num_rings; i++) {
     ring = &adev->vce.ring[i];
     sprintf(ring->name, "vce%d", i);
     r = amdgpu_ring_init(adev, ring, 512, &adev->vce.irq, 0);
     if (r) return r;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,21 +1,21 @@
 static long __apm_bios_call(void *_call) {
   APM_DECL_SEGS
   unsigned long flags;
   int cpu;
   struct desc_struct save_desc_40;
   struct desc_struct *gdt;
   struct apm_bios_call *call = _call;
   cpu = get_cpu();
   BUG_ON(cpu != 0);
-  gdt = get_cpu_gdt_table(cpu);
+  gdt = get_cpu_gdt_rw(cpu);
   save_desc_40 = gdt[0x40 / 8];
   gdt[0x40 / 8] = bad_bios_desc;
   apm_irq_save(flags);
   APM_DO_SAVE_SEGS;
   apm_bios_call_asm(call->func, call->ebx, call->ecx, &call->eax, &call->ebx, &call->ecx, &call->edx, &call->esi);
   APM_DO_RESTORE_SEGS;
   apm_irq_restore(flags);
   gdt[0x40 / 8] = save_desc_40;
   put_cpu();
   return call->eax & 0xff;
 }<sep>@@
expression e;
@@

- get_cpu_gdt_table
+ get_cpu_gdt_rw
    (e)
--- initial
+++ final
@@ -1,22 +1,22 @@
 static long __apm_bios_call_simple(void *_call) {
   u8 error;
   APM_DECL_SEGS
   unsigned long flags;
   int cpu;
   struct desc_struct save_desc_40;
   struct desc_struct *gdt;
   struct apm_bios_call *call = _call;
   cpu = get_cpu();
   BUG_ON(cpu != 0);
-  gdt = get_cpu_gdt_table(cpu);
+  gdt = get_cpu_gdt_rw(cpu);
   save_desc_40 = gdt[0x40 / 8];
   gdt[0x40 / 8] = bad_bios_desc;
   apm_irq_save(flags);
   APM_DO_SAVE_SEGS;
   error = apm_bios_call_simple_asm(call->func, call->ebx, call->ecx, &call->eax);
   APM_DO_RESTORE_SEGS;
   apm_irq_restore(flags);
   gdt[0x40 / 8] = save_desc_40;
   put_cpu();
   return error;
 }<sep>@@
expression e;
@@

- get_cpu_gdt_table
+ get_cpu_gdt_rw
    (e)
--- initial
+++ final
@@ -1,51 +1,51 @@
 static inline u16 call_pnp_bios(u16 func, u16 arg1, u16 arg2, u16 arg3, u16 arg4, u16 arg5, u16 arg6, u16 arg7, void *ts1_base, u32 ts1_size, void *ts2_base, u32 ts2_size) {
   unsigned long flags;
   u16 status;
   struct desc_struct save_desc_40;
   int cpu;
   /*
    * PnP BIOSes are generally not terribly re-entrant.
    * Also, don't rely on them to save everything correctly.
    */
   if (pnp_bios_is_utter_crap) return PNP_FUNCTION_NOT_SUPPORTED;
   cpu = get_cpu();
-  save_desc_40 = get_cpu_gdt_table(cpu)[0x40 / 8];
-  get_cpu_gdt_table(cpu)[0x40 / 8] = bad_bios_desc;
+  save_desc_40 = get_cpu_gdt_rw(cpu)[0x40 / 8];
+  get_cpu_gdt_rw(cpu)[0x40 / 8] = bad_bios_desc;
   /* On some boxes IRQ's during PnP BIOS calls are deadly.  */
   spin_lock_irqsave(&pnp_bios_lock, flags);
   /* The lock prevents us bouncing CPU here */
   if (ts1_size) Q2_SET_SEL(smp_processor_id(), PNP_TS1, ts1_base, ts1_size);
   if (ts2_size) Q2_SET_SEL(smp_processor_id(), PNP_TS2, ts2_base, ts2_size);
   __asm__ __volatile__("pushl %%ebp\n\t"
                        "pushl %%edi\n\t"
                        "pushl %%esi\n\t"
                        "pushl %%ds\n\t"
                        "pushl %%es\n\t"
                        "pushl %%fs\n\t"
                        "pushl %%gs\n\t"
                        "pushfl\n\t"
                        "movl %%esp, pnp_bios_fault_esp\n\t"
                        "movl $1f, pnp_bios_fault_eip\n\t"
                        "lcall %5,%6\n\t"
                        "1:popfl\n\t"
                        "popl %%gs\n\t"
                        "popl %%fs\n\t"
                        "popl %%es\n\t"
                        "popl %%ds\n\t"
                        "popl %%esi\n\t"
                        "popl %%edi\n\t"
                        "popl %%ebp\n\t"
                        : "=a"(status)
                        : "0"((func) | (((u32)arg1) << 16)), "b"((arg2) | (((u32)arg3) << 16)), "c"((arg4) | (((u32)arg5) << 16)), "d"((arg6) | (((u32)arg7) << 16)), "i"(PNP_CS32), "i"(0)
                        : "memory");
   spin_unlock_irqrestore(&pnp_bios_lock, flags);
-  get_cpu_gdt_table(cpu)[0x40 / 8] = save_desc_40;
+  get_cpu_gdt_rw(cpu)[0x40 / 8] = save_desc_40;
   put_cpu();
   /* If we get here and this is set then the PnP BIOS faulted on us. */
   if (pnp_bios_is_utter_crap) {
     printk(KERN_ERR "PnPBIOS: Warning! Your PnP BIOS caused a fatal error. Attempting to continue\n");
     printk(KERN_ERR "PnPBIOS: You may need to reboot with the \"pnpbios=off\" option to operate stably\n");
     printk(KERN_ERR "PnPBIOS: Check with your vendor for an updated BIOS\n");
   }
   return status;
 }<sep>@@
expression e;
@@

- get_cpu_gdt_table
+ get_cpu_gdt_rw
    (e)
--- initial
+++ final
@@ -1,13 +1,13 @@
 void pnpbios_calls_init(union pnp_bios_install_struct *header) {
   int i;
   spin_lock_init(&pnp_bios_lock);
   pnp_bios_callpoint.offset = header->fields.pm16offset;
   pnp_bios_callpoint.segment = PNP_CS16;
   for_each_possible_cpu(i) {
-    struct desc_struct *gdt = get_cpu_gdt_table(i);
+    struct desc_struct *gdt = get_cpu_gdt_rw(i);
     if (!gdt) continue;
     set_desc_base(&gdt[GDT_ENTRY_PNPBIOS_CS32], (unsigned long)&pnp_bios_callfunc);
     set_desc_base(&gdt[GDT_ENTRY_PNPBIOS_CS16], (unsigned long)__va(header->fields.pm16cseg));
     set_desc_base(&gdt[GDT_ENTRY_PNPBIOS_DS], (unsigned long)__va(header->fields.pm16dseg));
   }
 }<sep>@@
expression e;
@@

- get_cpu_gdt_table
+ get_cpu_gdt_rw
    (e)
--- initial
+++ final
@@ -1,8 +1,8 @@
 void switch_to_new_gdt(int cpu) {
   struct desc_ptr gdt_descr;
-  gdt_descr.address = (long)get_cpu_gdt_table(cpu);
+  gdt_descr.address = (long)get_cpu_gdt_rw(cpu);
   gdt_descr.size = GDT_SIZE - 1;
   load_gdt(&gdt_descr);
   /* Reload the per-cpu base */
   load_percpu_segment(cpu);
 }<sep>@@
expression e;
@@

- get_cpu_gdt_table
+ get_cpu_gdt_rw
    (e)
--- initial
+++ final
@@ -1,58 +1,58 @@
 static void __save_processor_state(struct saved_context *ctxt) {
 #ifdef CONFIG_X86_32
   mtrr_save_fixed_ranges(NULL);
 #endif
   kernel_fpu_begin();
   /*
    * descriptor tables
    */
 #ifdef CONFIG_X86_32
   store_idt(&ctxt->idt);
 #else
   /* CONFIG_X86_64 */
   store_idt((struct desc_ptr *)&ctxt->idt_limit);
 #endif
   /*
    * We save it here, but restore it only in the hibernate case.
    * For ACPI S3 resume, this is loaded via 'early_gdt_desc' in 64-bit
    * mode in "secondary_startup_64". In 32-bit mode it is done via
    * 'pmode_gdt' in wakeup_start.
    */
   ctxt->gdt_desc.size = GDT_SIZE - 1;
-  ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_table(smp_processor_id());
+  ctxt->gdt_desc.address = (unsigned long)get_cpu_gdt_rw(smp_processor_id());
   store_tr(ctxt->tr);
   /* XMM0..XMM15 should be handled by kernel_fpu_begin(). */
   /*
    * segment registers
    */
 #ifdef CONFIG_X86_32
   savesegment(es, ctxt->es);
   savesegment(fs, ctxt->fs);
   savesegment(gs, ctxt->gs);
   savesegment(ss, ctxt->ss);
 #else
   /* CONFIG_X86_64 */
   asm volatile("movw %%ds, %0" : "=m"(ctxt->ds));
   asm volatile("movw %%es, %0" : "=m"(ctxt->es));
   asm volatile("movw %%fs, %0" : "=m"(ctxt->fs));
   asm volatile("movw %%gs, %0" : "=m"(ctxt->gs));
   asm volatile("movw %%ss, %0" : "=m"(ctxt->ss));
   rdmsrl(MSR_FS_BASE, ctxt->fs_base);
   rdmsrl(MSR_GS_BASE, ctxt->gs_base);
   rdmsrl(MSR_KERNEL_GS_BASE, ctxt->gs_kernel_base);
   mtrr_save_fixed_ranges(NULL);
   rdmsrl(MSR_EFER, ctxt->efer);
 #endif
   /*
    * control registers
    */
   ctxt->cr0 = read_cr0();
   ctxt->cr2 = read_cr2();
   ctxt->cr3 = read_cr3();
   ctxt->cr4 = __read_cr4();
 #ifdef CONFIG_X86_64
   ctxt->cr8 = read_cr8();
 #endif
   ctxt->misc_enable_saved = !rdmsrl_safe(MSR_IA32_MISC_ENABLE, &ctxt->misc_enable);
   msr_save_context(ctxt);
 }<sep>@@
expression e;
@@

- get_cpu_gdt_table
+ get_cpu_gdt_rw
    (e)
--- initial
+++ final
@@ -1,23 +1,23 @@
 static void fix_processor_context(void) {
   int cpu = smp_processor_id();
   struct tss_struct *t = &per_cpu(cpu_tss, cpu);
 #ifdef CONFIG_X86_64
-  struct desc_struct *desc = get_cpu_gdt_table(cpu);
+  struct desc_struct *desc = get_cpu_gdt_rw(cpu);
   tss_desc tss;
 #endif
   set_tss_desc(cpu, t); /*
                          * This just modifies memory; should not be
                          * necessary. But... This is necessary, because
                          * 386 hardware has concept of busy TSS or some
                          * similar stupidity.
                          */
 #ifdef CONFIG_X86_64
   memcpy(&tss, &desc[GDT_ENTRY_TSS], sizeof(tss_desc));
   tss.type = 0x9; /* The available 64-bit TSS (see AMD vol 2, pg 91 */
   write_gdt_entry(desc, GDT_ENTRY_TSS, &tss, DESC_TSS);
   syscall_init(); /* This sets MSR_*STAR and related */
 #endif
   load_TR_desc();                  /* This does ltr */
   load_mm_ldt(current->active_mm); /* This does lldt */
   fpu__resume_cpu();
 }<sep>@@
expression e;
@@

- get_cpu_gdt_table
+ get_cpu_gdt_rw
    (e)
--- initial
+++ final
@@ -1,8 +1,8 @@
 void __init efi_call_phys_epilog(pgd_t *save_pgd) {
   struct desc_ptr gdt_descr;
-  gdt_descr.address = (unsigned long)get_cpu_gdt_table(0);
+  gdt_descr.address = (unsigned long)get_cpu_gdt_rw(0);
   gdt_descr.size = GDT_SIZE - 1;
   load_gdt(&gdt_descr);
   load_cr3(save_pgd);
   __flush_tlb_all();
 }<sep>@@
expression e;
@@

- get_cpu_gdt_table
+ get_cpu_gdt_rw
    (e)
--- initial
+++ final
@@ -1,12 +1,12 @@
 static void load_TLS_descriptor(struct thread_struct *t, unsigned int cpu, unsigned int i) {
   struct desc_struct *shadow = &per_cpu(shadow_tls_desc, cpu).desc[i];
   struct desc_struct *gdt;
   xmaddr_t maddr;
   struct multicall_space mc;
   if (desc_equal(shadow, &t->tls_array[i])) return;
   *shadow = t->tls_array[i];
-  gdt = get_cpu_gdt_table(cpu);
+  gdt = get_cpu_gdt_rw(cpu);
   maddr = arbitrary_virt_to_machine(&gdt[GDT_ENTRY_TLS_MIN + i]);
   mc = __xen_mc_entry(0);
   MULTI_update_descriptor(mc.mc, maddr.maddr, t->tls_array[i]);
 }<sep>@@
expression e;
@@

- get_cpu_gdt_table
+ get_cpu_gdt_rw
    (e)