imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,34 +1,34 @@
 static int vega10_start_dpm(struct pp_hwmgr *hwmgr, uint32_t bitmap) {
   struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
   uint32_t i, feature_mask = 0;
   for (i = 0; i < GNLD_DPM_MAX; i++) {
     if (data->smu_features[i].smu_feature_bitmap & bitmap) {
       if (data->smu_features[i].supported) {
         if (!data->smu_features[i].enabled) {
           feature_mask |= data->smu_features[i].smu_feature_bitmap;
           data->smu_features[i].enabled = true;
         }
       }
     }
   }
   if (vega10_enable_smc_features(hwmgr->smumgr, true, feature_mask)) {
     for (i = 0; i < GNLD_DPM_MAX; i++) {
       if (data->smu_features[i].smu_feature_bitmap & feature_mask) data->smu_features[i].enabled = false;
     }
   }
   if (data->smu_features[GNLD_LED_DISPLAY].supported == true) {
     PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_LED_DISPLAY].smu_feature_bitmap), "Attempt to Enable LED DPM feature Failed!", return -EINVAL);
     data->smu_features[GNLD_LED_DISPLAY].enabled = true;
   }
   if (data->vbios_boot_state.bsoc_vddc_lock) {
     smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFloorSocVoltage, 0);
     data->vbios_boot_state.bsoc_vddc_lock = false;
   }
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_Falcon_QuickTransition)) {
+  if (PP_CAP(PHM_PlatformCaps_Falcon_QuickTransition)) {
     if (data->smu_features[GNLD_ACDC].supported) {
       PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_ACDC].smu_feature_bitmap), "Attempt to Enable DS_GFXCLK Feature Failed!", return -1);
       data->smu_features[GNLD_ACDC].enabled = true;
     }
   }
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,13 +1,13 @@
 static int vega10_update_sclk_threshold(struct pp_hwmgr *hwmgr) {
   struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
   int result = 0;
   uint32_t low_sclk_interrupt_threshold = 0;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkThrottleLowNotification) && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) {
+  if (PP_CAP(PHM_PlatformCaps_SclkThrottleLowNotification) && (hwmgr->gfx_arbiter.sclk_threshold != data->low_sclk_interrupt_threshold)) {
     data->low_sclk_interrupt_threshold = hwmgr->gfx_arbiter.sclk_threshold;
     low_sclk_interrupt_threshold = data->low_sclk_interrupt_threshold;
     data->smc_state_table.pp_table.LowGfxclkInterruptThreshold = cpu_to_le32(low_sclk_interrupt_threshold);
     /* This message will also enable SmcToHost Interrupt */
     result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetLowGfxclkInterruptThreshold, (uint32_t)low_sclk_interrupt_threshold);
   }
   return result;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,8 +1,8 @@
 int vega10_disable_power_containment(struct pp_hwmgr *hwmgr) {
   struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
+  if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
     if (data->smu_features[GNLD_PPT].supported) PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, false, data->smu_features[GNLD_PPT].smu_feature_bitmap), "Attempt to disable PPT feature Failed!", data->smu_features[GNLD_PPT].supported = false);
     if (data->smu_features[GNLD_TDC].supported) PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, false, data->smu_features[GNLD_TDC].smu_feature_bitmap), "Attempt to disable PPT feature Failed!", data->smu_features[GNLD_TDC].supported = false);
   }
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,12 +1,12 @@
 static int vega10_disable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) {
   uint32_t data;
   cgs_enter_safe_mode(hwmgr->device, true);
   vega10_didt_set_mask(hwmgr, false);
   cgs_enter_safe_mode(hwmgr->device, false);
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) {
+  if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
     data = 0x00000000;
     cgs_write_register(hwmgr->device, mmGC_DIDT_CTRL0, data);
   }
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM)) vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
+  if (PP_CAP(PHM_PlatformCaps_PSM)) vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,12 +1,12 @@
 static int vega10_disable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) {
   uint32_t data;
   cgs_enter_safe_mode(hwmgr->device, true);
   vega10_didt_set_mask(hwmgr, false);
   cgs_enter_safe_mode(hwmgr->device, false);
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) {
+  if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
     data = 0x00000000;
     cgs_write_register(hwmgr->device, mmGC_EDC_CTRL, data);
   }
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM)) vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
+  if (PP_CAP(PHM_PlatformCaps_PSM)) vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,14 +1,14 @@
 int vega10_enable_power_containment(struct pp_hwmgr *hwmgr) {
   struct vega10_hwmgr *data = (struct vega10_hwmgr *)(hwmgr->backend);
   struct phm_ppt_v2_information *table_info = (struct phm_ppt_v2_information *)(hwmgr->pptable);
   struct phm_tdp_table *tdp_table = table_info->tdp_table;
   uint32_t default_pwr_limit = (uint32_t)(tdp_table->usMaximumPowerDeliveryLimit);
   int result = 0;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
+  if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
     if (data->smu_features[GNLD_PPT].supported) PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_PPT].smu_feature_bitmap), "Attempt to enable PPT feature Failed!", data->smu_features[GNLD_PPT].supported = false);
     if (data->smu_features[GNLD_TDC].supported) PP_ASSERT_WITH_CODE(!vega10_enable_smc_features(hwmgr->smumgr, true, data->smu_features[GNLD_TDC].smu_feature_bitmap), "Attempt to enable PPT feature Failed!", data->smu_features[GNLD_TDC].supported = false);
     result = vega10_set_power_limit(hwmgr, default_pwr_limit);
     PP_ASSERT_WITH_CODE(!result, "Failed to set Default Power Limit in SMC!", return result);
   }
   return result;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,29 +1,29 @@
 static int vega10_enable_psm_gc_didt_config(struct pp_hwmgr *hwmgr) {
   int result;
   uint32_t num_se = 0, count, data;
   struct cgs_system_info sys_info = {0};
   uint32_t reg;
   sys_info.size = sizeof(struct cgs_system_info);
   sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
   if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) num_se = sys_info.value;
   cgs_enter_safe_mode(hwmgr->device, true);
   cgs_lock_grbm_idx(hwmgr->device, true);
   reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);
   for (count = 0; count < num_se; count++) {
     data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
     cgs_write_register(hwmgr->device, reg, data);
     result = vega10_program_didt_config_registers(hwmgr, SEDiDtStallCtrlConfig_vega10, VEGA10_CONFIGREG_DIDT);
     result |= vega10_program_didt_config_registers(hwmgr, SEDiDtStallPatternConfig_vega10, VEGA10_CONFIGREG_DIDT);
     result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl3Config_vega10, VEGA10_CONFIGREG_DIDT);
     result |= vega10_program_didt_config_registers(hwmgr, SEDiDtCtrl0Config_Vega10, VEGA10_CONFIGREG_DIDT);
     if (0 != result) break;
   }
   cgs_write_register(hwmgr->device, reg, 0xE0000000);
   cgs_lock_grbm_idx(hwmgr->device, false);
   vega10_didt_set_mask(hwmgr, true);
   cgs_enter_safe_mode(hwmgr->device, false);
   vega10_program_gc_didt_config_registers(hwmgr, GCDiDtDroopCtrlConfig_vega10);
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10);
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM)) vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
+  if (PP_CAP(PHM_PlatformCaps_GCEDC)) vega10_program_gc_didt_config_registers(hwmgr, GCDiDtCtrl0Config_vega10);
+  if (PP_CAP(PHM_PlatformCaps_PSM)) vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,34 +1,34 @@
 static int vega10_enable_psm_gc_edc_config(struct pp_hwmgr *hwmgr) {
   int result;
   uint32_t num_se = 0;
   uint32_t count, data;
   struct cgs_system_info sys_info = {0};
   uint32_t reg;
   sys_info.size = sizeof(struct cgs_system_info);
   sys_info.info_id = CGS_SYSTEM_INFO_GFX_SE_INFO;
   if (cgs_query_system_info(hwmgr->device, &sys_info) == 0) num_se = sys_info.value;
   cgs_enter_safe_mode(hwmgr->device, true);
   vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMResetConfig_vega10);
   cgs_lock_grbm_idx(hwmgr->device, true);
   reg = soc15_get_register_offset(GC_HWID, 0, mmGRBM_GFX_INDEX_BASE_IDX, mmGRBM_GFX_INDEX);
   for (count = 0; count < num_se; count++) {
     data = GRBM_GFX_INDEX__INSTANCE_BROADCAST_WRITES_MASK | GRBM_GFX_INDEX__SH_BROADCAST_WRITES_MASK | (count << GRBM_GFX_INDEX__SE_INDEX__SHIFT);
     cgs_write_register(hwmgr->device, reg, data);
     result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallPatternConfig_Vega10, VEGA10_CONFIGREG_DIDT);
     result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCStallDelayConfig_Vega10, VEGA10_CONFIGREG_DIDT);
     result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlResetConfig_Vega10, VEGA10_CONFIGREG_DIDT);
     result |= vega10_program_didt_config_registers(hwmgr, PSMSEEDCCtrlConfig_Vega10, VEGA10_CONFIGREG_DIDT);
     if (0 != result) break;
   }
   cgs_write_register(hwmgr->device, reg, 0xE0000000);
   cgs_lock_grbm_idx(hwmgr->device, false);
   vega10_didt_set_mask(hwmgr, true);
   cgs_enter_safe_mode(hwmgr->device, false);
   vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCDroopCtrlConfig_vega10);
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_GCEDC)) {
+  if (PP_CAP(PHM_PlatformCaps_GCEDC)) {
     vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlResetConfig_vega10);
     vega10_program_gc_didt_config_registers(hwmgr, PSMGCEDCCtrlConfig_vega10);
   }
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PSM)) vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
+  if (PP_CAP(PHM_PlatformCaps_PSM)) vega10_program_gc_didt_config_registers(hwmgr, AvfsPSMInitConfig_vega10);
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,8 +1,8 @@
 int vega10_power_control_set_level(struct pp_hwmgr *hwmgr) {
   int adjust_percent, result = 0;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_PowerContainment)) {
+  if (PP_CAP(PHM_PlatformCaps_PowerContainment)) {
     adjust_percent = hwmgr->platform_descriptor.TDPAdjustmentPolarity ? hwmgr->platform_descriptor.TDPAdjustment : (-1 * hwmgr->platform_descriptor.TDPAdjustment);
     result = vega10_set_overdrive_target_percentage(hwmgr, (uint32_t)adjust_percent);
   }
   return result;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,9 +1,9 @@
 int tf_vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) {
   /* If the fantable setup has failed we could have disabled
    * PHM_PlatformCaps_MicrocodeFanControl even after
    * this function was included in the table.
    * Make sure that we still think controlling the fan is OK.
    */
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) { vega10_fan_ctrl_start_smc_fan_control(hwmgr); }
+  if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) { vega10_fan_ctrl_start_smc_fan_control(hwmgr); }
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,17 +1,17 @@
 int vega10_fan_ctrl_get_fan_speed_info(struct pp_hwmgr *hwmgr, struct phm_fan_speed_info *fan_speed_info) {
   if (hwmgr->thermal_controller.fanInfo.bNoFan) return 0;
   fan_speed_info->supports_percent_read = true;
   fan_speed_info->supports_percent_write = true;
   fan_speed_info->min_percent = 0;
   fan_speed_info->max_percent = 100;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_FanSpeedInTableIsRPM) && hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
+  if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM) && hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution) {
     fan_speed_info->supports_rpm_read = true;
     fan_speed_info->supports_rpm_write = true;
     fan_speed_info->min_rpm = hwmgr->thermal_controller.fanInfo.ulMinRPM;
     fan_speed_info->max_rpm = hwmgr->thermal_controller.fanInfo.ulMaxRPM;
   } else {
     fan_speed_info->min_rpm = 0;
     fan_speed_info->max_rpm = 0;
   }
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,9 +1,9 @@
 int vega10_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) {
   int result;
   if (hwmgr->thermal_controller.fanInfo.bNoFan) return 0;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) {
+  if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {
     result = vega10_fan_ctrl_start_smc_fan_control(hwmgr);
   } else
     result = vega10_fan_ctrl_set_default_mode(hwmgr);
   return result;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,18 +1,18 @@
 int vega10_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed) {
   uint32_t duty100;
   uint32_t duty;
   uint64_t tmp64;
   uint32_t reg;
   if (hwmgr->thermal_controller.fanInfo.bNoFan) return 0;
   if (speed > 100) speed = 100;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
+  if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
   reg = soc15_get_register_offset(THM_HWID, 0, mmCG_FDO_CTRL1_BASE_IDX, mmCG_FDO_CTRL1);
   duty100 = (cgs_read_register(hwmgr->device, reg) & CG_FDO_CTRL1__FMAX_DUTY100_MASK) >> CG_FDO_CTRL1__FMAX_DUTY100__SHIFT;
   if (duty100 == 0) return -EINVAL;
   tmp64 = (uint64_t)speed * duty100;
   do_div(tmp64, 100);
   duty = (uint32_t)tmp64;
   reg = soc15_get_register_offset(THM_HWID, 0, mmCG_FDO_CTRL0_BASE_IDX, mmCG_FDO_CTRL0);
   cgs_write_register(hwmgr->device, reg, (cgs_read_register(hwmgr->device, reg) & ~CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK) | (duty << CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT));
   return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,15 +1,15 @@
 int vega10_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) {
   uint32_t tach_period;
   uint32_t crystal_clock_freq;
   int result = 0;
   uint32_t reg;
   if (hwmgr->thermal_controller.fanInfo.bNoFan || (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) return -1;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
+  if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) result = vega10_fan_ctrl_stop_smc_fan_control(hwmgr);
   if (!result) {
     crystal_clock_freq = smu7_get_xclk(hwmgr);
     tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
     reg = soc15_get_register_offset(THM_HWID, 0, mmCG_TACH_STATUS_BASE_IDX, mmCG_TACH_STATUS);
     cgs_write_register(hwmgr->device, reg, (cgs_read_register(hwmgr->device, reg) & ~CG_TACH_STATUS__TACH_PERIOD_MASK) | (tach_period << CG_TACH_STATUS__TACH_PERIOD__SHIFT));
   }
   return vega10_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,10 +1,10 @@
 int smu7_fan_ctrl_reset_fan_speed_to_default(struct pp_hwmgr *hwmgr) {
   int result;
   if (hwmgr->thermal_controller.fanInfo.bNoFan) return 0;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) {
+  if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {
     result = smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
     if (!result) result = smu7_fan_ctrl_start_smc_fan_control(hwmgr);
   } else
     result = smu7_fan_ctrl_set_default_mode(hwmgr);
   return result;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,15 +1,15 @@
 int smu7_fan_ctrl_set_fan_speed_percent(struct pp_hwmgr *hwmgr, uint32_t speed) {
   uint32_t duty100;
   uint32_t duty;
   uint64_t tmp64;
   if (hwmgr->thermal_controller.fanInfo.bNoFan) return 0;
   if (speed > 100) speed = 100;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
+  if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
   duty100 = PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL1, FMAX_DUTY100);
   if (duty100 == 0) return -EINVAL;
   tmp64 = (uint64_t)speed * duty100;
   do_div(tmp64, 100);
   duty = (uint32_t)tmp64;
   PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_FDO_CTRL0, FDO_STATIC_DUTY, duty);
   return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,10 +1,10 @@
 int smu7_fan_ctrl_set_fan_speed_rpm(struct pp_hwmgr *hwmgr, uint32_t speed) {
   uint32_t tach_period;
   uint32_t crystal_clock_freq;
   if (hwmgr->thermal_controller.fanInfo.bNoFan || (hwmgr->thermal_controller.fanInfo.ucTachometerPulsesPerRevolution == 0) || (speed < hwmgr->thermal_controller.fanInfo.ulMinRPM) || (speed > hwmgr->thermal_controller.fanInfo.ulMaxRPM)) return 0;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
+  if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) smu7_fan_ctrl_stop_smc_fan_control(hwmgr);
   crystal_clock_freq = smu7_get_xclk(hwmgr);
   tach_period = 60 * crystal_clock_freq * 10000 / (8 * speed);
   PHM_WRITE_VFPF_INDIRECT_FIELD(hwmgr->device, CGS_IND_REG__SMC, CG_TACH_STATUS, TACH_PERIOD, tach_period);
   return smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC_RPM);
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,17 +1,17 @@
 int smu7_fan_ctrl_start_smc_fan_control(struct pp_hwmgr *hwmgr) {
   int result;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
+  if (PP_CAP(PHM_PlatformCaps_ODFuzzyFanControlSupport)) {
     cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_FUZZY);
     result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
-    if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_FanSpeedInTableIsRPM))
+    if (PP_CAP(PHM_PlatformCaps_FanSpeedInTableIsRPM))
       hwmgr->hwmgr_func->set_max_fan_rpm_output(hwmgr, hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanRPM);
     else
       hwmgr->hwmgr_func->set_max_fan_pwm_output(hwmgr, hwmgr->thermal_controller.advanceFanControlParameters.usMaxFanPWM);
   } else {
     cgs_write_register(hwmgr->device, mmSMC_MSG_ARG_0, FAN_CONTROL_TABLE);
     result = smum_send_msg_to_smc(hwmgr->smumgr, PPSMC_StartFanControl);
   }
   if (!result && hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature) result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_SetFanTemperatureTarget, hwmgr->thermal_controller.advanceFanControlParameters.ucTargetTemperature);
   hwmgr->fan_ctrl_enabled = true;
   return result;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,12 +1,12 @@
 static int tf_smu7_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr, void *input, void *output, void *storage, int result) {
   /* If the fantable setup has failed we could have disabled
    * PHM_PlatformCaps_MicrocodeFanControl even after
    * this function was included in the table.
    * Make sure that we still think controlling the fan is OK.
    */
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_MicrocodeFanControl)) {
+  if (PP_CAP(PHM_PlatformCaps_MicrocodeFanControl)) {
     smu7_fan_ctrl_start_smc_fan_control(hwmgr);
     smu7_fan_ctrl_set_static_mode(hwmgr, FDO_PWM_MODE_STATIC);
   }
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)
--- initial
+++ final
@@ -1,14 +1,14 @@
 int smu7_disable_didt_config(struct pp_hwmgr *hwmgr) {
   int result;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping) || phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping) || phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping) || phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
+  if (PP_CAP(PHM_PlatformCaps_SQRamping) || PP_CAP(PHM_PlatformCaps_DBRamping) || PP_CAP(PHM_PlatformCaps_TDRamping) || PP_CAP(PHM_PlatformCaps_TCPRamping)) {
     cgs_enter_safe_mode(hwmgr->device, true);
     result = smu7_enable_didt(hwmgr, false);
     PP_ASSERT_WITH_CODE((result == 0), "Post DIDT enable clock gating failed.", return result);
     if (hwmgr->chip_id == CHIP_POLARIS11) {
       result = smum_send_msg_to_smc(hwmgr->smumgr, (uint16_t)(PPSMC_MSG_DisableDpmDidt));
       PP_ASSERT_WITH_CODE((0 == result), "Failed to disable DPM DIDT.", return result);
     }
     cgs_enter_safe_mode(hwmgr->device, false);
   }
   return 0;
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)