imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,15 +1,15 @@
 uint32_t ddi_signal_levels(struct intel_dp *intel_dp) {
   struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
   struct drm_i915_private *dev_priv = to_i915(dport->base.base.dev);
   struct intel_encoder *encoder = &dport->base;
   uint8_t train_set = intel_dp->train_set[0];
   int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | DP_TRAIN_PRE_EMPHASIS_MASK);
   enum port port = dport->port;
   uint32_t level;
   level = translate_signal_level(signal_levels);
   if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
     skl_ddi_set_iboost(encoder, level);
-  else if (IS_BROXTON(dev_priv))
+  else if (IS_GEN9_LP(dev_priv))
     bxt_ddi_vswing_sequence(dev_priv, level, port, encoder->type);
   return DDI_BUF_TRANS_SELECT(level);
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,40 +1,40 @@
 static void intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, struct intel_dp *intel_dp) {
   struct drm_i915_private *dev_priv = to_i915(dev);
   u32 pp_on, pp_off, pp_div, port_sel = 0;
   int div = dev_priv->rawclk_freq / 1000;
   struct pps_registers regs;
   enum port port = dp_to_dig_port(intel_dp)->port;
   const struct edp_power_seq *seq = &intel_dp->pps_delays;
   lockdep_assert_held(&dev_priv->pps_mutex);
   intel_pps_get_registers(dev_priv, intel_dp, &regs);
   pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT);
   pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT);
   /* Compute the divisor for the pp clock, simply match the Bspec
    * formula. */
-  if (IS_BROXTON(dev_priv)) {
+  if (IS_GEN9_LP(dev_priv)) {
     pp_div = I915_READ(regs.pp_ctrl);
     pp_div &= ~BXT_POWER_CYCLE_DELAY_MASK;
     pp_div |= (DIV_ROUND_UP((seq->t11_t12 + 1), 1000) << BXT_POWER_CYCLE_DELAY_SHIFT);
   } else {
     pp_div = ((100 * div) / 2 - 1) << PP_REFERENCE_DIVIDER_SHIFT;
     pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) << PANEL_POWER_CYCLE_DELAY_SHIFT);
   }
   /* Haswell doesn't have any port selection bits for the panel
    * power sequencer any more. */
   if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
     port_sel = PANEL_PORT_SELECT_VLV(port);
   } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) {
     if (port == PORT_A)
       port_sel = PANEL_PORT_SELECT_DPA;
     else
       port_sel = PANEL_PORT_SELECT_DPD;
   }
   pp_on |= port_sel;
   I915_WRITE(regs.pp_on, pp_on);
   I915_WRITE(regs.pp_off, pp_off);
-  if (IS_BROXTON(dev_priv))
+  if (IS_GEN9_LP(dev_priv))
     I915_WRITE(regs.pp_ctrl, pp_div);
   else
     I915_WRITE(regs.pp_div, pp_div);
-  DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", I915_READ(regs.pp_on), I915_READ(regs.pp_off), IS_BROXTON(dev_priv) ? (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : I915_READ(regs.pp_div));
+  DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", I915_READ(regs.pp_on), I915_READ(regs.pp_off), IS_GEN9_LP(dev_priv) ? (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK) : I915_READ(regs.pp_div));
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,29 +1,29 @@
 int intel_power_domains_init(struct drm_i915_private *dev_priv) {
   struct i915_power_domains *power_domains = &dev_priv->power_domains;
   i915.disable_power_well = sanitize_disable_power_well_option(dev_priv, i915.disable_power_well);
   dev_priv->csr.allowed_dc_mask = get_allowed_dc_mask(dev_priv, i915.enable_dc);
   BUILD_BUG_ON(POWER_DOMAIN_NUM > 31);
   mutex_init(&power_domains->lock);
   /*
    * The enabling order will be from lower to higher indexed wells,
    * the disabling order is reversed.
    */
   if (IS_HASWELL(dev_priv)) {
     set_power_wells(power_domains, hsw_power_wells);
   } else if (IS_BROADWELL(dev_priv)) {
     set_power_wells(power_domains, bdw_power_wells);
   } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
     set_power_wells(power_domains, skl_power_wells);
-  } else if (IS_BROXTON(dev_priv)) {
+  } else if (IS_GEN9_LP(dev_priv)) {
     set_power_wells(power_domains, bxt_power_wells);
   } else if (IS_GEMINILAKE(dev_priv)) {
     set_power_wells(power_domains, glk_power_wells);
   } else if (IS_CHERRYVIEW(dev_priv)) {
     set_power_wells(power_domains, chv_power_wells);
   } else if (IS_VALLEYVIEW(dev_priv)) {
     set_power_wells(power_domains, vlv_power_wells);
   } else {
     set_power_wells(power_domains, i9xx_always_on_power_well);
   }
   return 0;
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,38 +1,38 @@
 void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) {
   if (IS_SKYLAKE(dev_priv))
     dev_priv->display.init_clock_gating = skylake_init_clock_gating;
   else if (IS_KABYLAKE(dev_priv))
     dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
-  else if (IS_BROXTON(dev_priv))
+  else if (IS_GEN9_LP(dev_priv))
     dev_priv->display.init_clock_gating = bxt_init_clock_gating;
   else if (IS_BROADWELL(dev_priv))
     dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
   else if (IS_CHERRYVIEW(dev_priv))
     dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
   else if (IS_HASWELL(dev_priv))
     dev_priv->display.init_clock_gating = haswell_init_clock_gating;
   else if (IS_IVYBRIDGE(dev_priv))
     dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
   else if (IS_VALLEYVIEW(dev_priv))
     dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
   else if (IS_GEN6(dev_priv))
     dev_priv->display.init_clock_gating = gen6_init_clock_gating;
   else if (IS_GEN5(dev_priv))
     dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
   else if (IS_G4X(dev_priv))
     dev_priv->display.init_clock_gating = g4x_init_clock_gating;
   else if (IS_CRESTLINE(dev_priv))
     dev_priv->display.init_clock_gating = crestline_init_clock_gating;
   else if (IS_BROADWATER(dev_priv))
     dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
   else if (IS_GEN3(dev_priv))
     dev_priv->display.init_clock_gating = gen3_init_clock_gating;
   else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
     dev_priv->display.init_clock_gating = i85x_init_clock_gating;
   else if (IS_GEN2(dev_priv))
     dev_priv->display.init_clock_gating = i830_init_clock_gating;
   else {
     MISSING_CASE(INTEL_DEVID(dev_priv));
     dev_priv->display.init_clock_gating = nop_init_clock_gating;
   }
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,27 +1,27 @@
 static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv) {
   uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
   uint32_t de_pipe_enables;
   u32 de_port_masked = GEN8_AUX_CHANNEL_A;
   u32 de_port_enables;
   u32 de_misc_masked = GEN8_DE_MISC_GSE;
   enum pipe pipe;
   if (INTEL_INFO(dev_priv)->gen >= 9) {
     de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE | GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
     de_port_masked |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C | GEN9_AUX_CHANNEL_D;
-    if (IS_BROXTON(dev_priv)) de_port_masked |= BXT_DE_PORT_GMBUS;
+    if (IS_GEN9_LP(dev_priv)) de_port_masked |= BXT_DE_PORT_GMBUS;
   } else {
     de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE | GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
   }
   de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
   de_port_enables = de_port_masked;
-  if (IS_BROXTON(dev_priv))
+  if (IS_GEN9_LP(dev_priv))
     de_port_enables |= BXT_DE_PORT_HOTPLUG_MASK;
   else if (IS_BROADWELL(dev_priv))
     de_port_enables |= GEN8_PORT_DP_A_HOTPLUG;
   dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
   dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
   dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
   for_each_pipe(dev_priv, pipe) if (intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe))) GEN8_IRQ_INIT_NDX(DE_PIPE, pipe, dev_priv->de_irq_mask[pipe], de_pipe_enables);
   GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_masked, de_port_enables);
   GEN5_IRQ_INIT(GEN8_DE_MISC_, ~de_misc_masked, de_misc_masked);
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,30 +1,30 @@
 static void intel_dsi_port_enable(struct intel_encoder *encoder) {
   struct drm_device *dev = encoder->base.dev;
   struct drm_i915_private *dev_priv = to_i915(dev);
   struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
   struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
   enum port port;
   if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) {
     u32 temp;
     temp = I915_READ(VLV_CHICKEN_3);
     temp &= ~PIXEL_OVERLAP_CNT_MASK | intel_dsi->pixel_overlap << PIXEL_OVERLAP_CNT_SHIFT;
     I915_WRITE(VLV_CHICKEN_3, temp);
   }
   for_each_dsi_port(port, intel_dsi->ports) {
-    i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
+    i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port);
     u32 temp;
     temp = I915_READ(port_ctrl);
     temp &= ~LANE_CONFIGURATION_MASK;
     temp &= ~DUAL_LINK_MODE_MASK;
     if (intel_dsi->ports == (BIT(PORT_A) | BIT(PORT_C))) {
       temp |= (intel_dsi->dual_link - 1) << DUAL_LINK_MODE_SHIFT;
-      if (IS_BROXTON(dev_priv))
+      if (IS_GEN9_LP(dev_priv))
         temp |= LANE_CONFIGURATION_DUAL_LINK_A;
       else
         temp |= intel_crtc->pipe ? LANE_CONFIGURATION_DUAL_LINK_B : LANE_CONFIGURATION_DUAL_LINK_A;
     }
     /* assert ip_tg_enable signal */
     I915_WRITE(port_ctrl, temp | DPI_ENABLE);
     POSTING_READ(port_ctrl);
   }
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,9 +1,9 @@
 void intel_ddi_clock_get(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config) {
   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
   if (INTEL_GEN(dev_priv) <= 8)
     hsw_ddi_clock_get(encoder, pipe_config);
   else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
     skl_ddi_clock_get(encoder, pipe_config);
-  else if (IS_BROXTON(dev_priv))
+  else if (IS_GEN9_LP(dev_priv))
     bxt_ddi_clock_get(encoder, pipe_config);
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,30 +1,30 @@
 static bool intel_dsi_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state) {
   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
   struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, base);
   struct intel_connector *intel_connector = intel_dsi->attached_connector;
   struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc);
   const struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
   struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
   int ret;
   DRM_DEBUG_KMS("\n");
   if (fixed_mode) {
     intel_fixed_panel_mode(fixed_mode, adjusted_mode);
     if (HAS_GMCH_DISPLAY(dev_priv))
       intel_gmch_panel_fitting(crtc, pipe_config, intel_connector->panel.fitting_mode);
     else
       intel_pch_panel_fitting(crtc, pipe_config, intel_connector->panel.fitting_mode);
   }
   /* DSI uses short packets for sync events, so clear mode flags for DSI */
   adjusted_mode->flags = 0;
-  if (IS_BROXTON(dev_priv)) {
+  if (IS_GEN9_LP(dev_priv)) {
     /* Dual link goes to DSI transcoder A. */
     if (intel_dsi->ports == BIT(PORT_C))
       pipe_config->cpu_transcoder = TRANSCODER_DSI_C;
     else
       pipe_config->cpu_transcoder = TRANSCODER_DSI_A;
   }
   ret = intel_compute_dsi_pll(encoder, pipe_config);
   if (ret) return false;
   pipe_config->clock_set = true;
   return true;
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,34 +1,34 @@
 static u8 intel_hdmi_ddc_pin(struct drm_i915_private *dev_priv, enum port port) {
   const struct ddi_vbt_port_info *info = &dev_priv->vbt.ddi_port_info[port];
   u8 ddc_pin;
   if (info->alternate_ddc_pin) {
     DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (VBT)\n", info->alternate_ddc_pin, port_name(port));
     return info->alternate_ddc_pin;
   }
   switch (port) {
   case PORT_B:
-    if (IS_BROXTON(dev_priv))
+    if (IS_GEN9_LP(dev_priv))
       ddc_pin = GMBUS_PIN_1_BXT;
     else
       ddc_pin = GMBUS_PIN_DPB;
     break;
   case PORT_C:
-    if (IS_BROXTON(dev_priv))
+    if (IS_GEN9_LP(dev_priv))
       ddc_pin = GMBUS_PIN_2_BXT;
     else
       ddc_pin = GMBUS_PIN_DPC;
     break;
   case PORT_D:
     if (IS_CHERRYVIEW(dev_priv))
       ddc_pin = GMBUS_PIN_DPD_CHV;
     else
       ddc_pin = GMBUS_PIN_DPD;
     break;
   default:
     MISSING_CASE(port);
     ddc_pin = GMBUS_PIN_DPB;
     break;
   }
   DRM_DEBUG_KMS("Using DDC pin 0x%x for port %c (platform default)\n", ddc_pin, port_name(port));
   return ddc_pin;
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,35 +1,35 @@
 static int gen8_gmch_probe(struct i915_ggtt *ggtt) {
   struct drm_i915_private *dev_priv = ggtt->base.i915;
   struct pci_dev *pdev = dev_priv->drm.pdev;
   unsigned int size;
   u16 snb_gmch_ctl;
   /* TODO: We're not aware of mappable constraints on gen8 yet */
   ggtt->mappable_base = pci_resource_start(pdev, 2);
   ggtt->mappable_end = pci_resource_len(pdev, 2);
   if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(39))) pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(39));
   pci_read_config_word(pdev, SNB_GMCH_CTRL, &snb_gmch_ctl);
   if (INTEL_GEN(dev_priv) >= 9) {
     ggtt->stolen_size = gen9_get_stolen_size(snb_gmch_ctl);
     size = gen8_get_total_gtt_size(snb_gmch_ctl);
   } else if (IS_CHERRYVIEW(dev_priv)) {
     ggtt->stolen_size = chv_get_stolen_size(snb_gmch_ctl);
     size = chv_get_total_gtt_size(snb_gmch_ctl);
   } else {
     ggtt->stolen_size = gen8_get_stolen_size(snb_gmch_ctl);
     size = gen8_get_total_gtt_size(snb_gmch_ctl);
   }
   ggtt->base.total = (size / sizeof(gen8_pte_t)) << PAGE_SHIFT;
-  if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+  if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
     chv_setup_private_ppat(dev_priv);
   else
     bdw_setup_private_ppat(dev_priv);
   ggtt->base.cleanup = gen6_gmch_remove;
   ggtt->base.bind_vma = ggtt_bind_vma;
   ggtt->base.unbind_vma = ggtt_unbind_vma;
   ggtt->base.insert_page = gen8_ggtt_insert_page;
   ggtt->base.clear_range = nop_clear_range;
   if (!USES_FULL_PPGTT(dev_priv) || intel_scanout_needs_vtd_wa(dev_priv)) ggtt->base.clear_range = gen8_ggtt_clear_range;
   ggtt->base.insert_entries = gen8_ggtt_insert_entries;
   if (IS_CHERRYVIEW(dev_priv)) ggtt->base.insert_entries = gen8_ggtt_insert_entries__BKL;
   return ggtt_probe_common(ggtt, size);
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,32 +1,32 @@
 struct intel_shared_dpll *intel_ddi_get_link_dpll(struct intel_dp *intel_dp, int clock) {
   struct intel_connector *connector = intel_dp->attached_connector;
   struct intel_encoder *encoder = connector->encoder;
   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
   struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
   struct intel_shared_dpll *pll = NULL;
   struct intel_shared_dpll_config tmp_pll_config;
   enum intel_dpll_id dpll_id;
-  if (IS_BROXTON(dev_priv)) {
+  if (IS_GEN9_LP(dev_priv)) {
     dpll_id = (enum intel_dpll_id)dig_port->port;
     /*
      * Select the required PLL. This works for platforms where
      * there is no shared DPLL.
      */
     pll = &dev_priv->shared_dplls[dpll_id];
     if (WARN_ON(pll->active_mask)) {
       DRM_ERROR("Shared DPLL in use. active_mask:%x\n", pll->active_mask);
       return NULL;
     }
     tmp_pll_config = pll->config;
     if (!bxt_ddi_dp_set_dpll_hw_state(clock, &pll->config.hw_state)) {
       DRM_ERROR("Could not setup DPLL\n");
       pll->config = tmp_pll_config;
       return NULL;
     }
   } else if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
     pll = skl_find_link_pll(dev_priv, clock);
   } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
     pll = hsw_ddi_dp_get_dpll(encoder, clock);
   }
   return pll;
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,10 +1,10 @@
 static enum drm_mode_status hdmi_port_clock_valid(struct intel_hdmi *hdmi, int clock, bool respect_downstream_limits) {
   struct drm_i915_private *dev_priv = to_i915(intel_hdmi_to_dev(hdmi));
   if (clock < 25000) return MODE_CLOCK_LOW;
   if (clock > hdmi_port_clock_limit(hdmi, respect_downstream_limits)) return MODE_CLOCK_HIGH;
   /* BXT DPLL can't generate 223-240 MHz */
-  if (IS_BROXTON(dev_priv) && clock > 223333 && clock < 240000) return MODE_CLOCK_RANGE;
+  if (IS_GEN9_LP(dev_priv) && clock > 223333 && clock < 240000) return MODE_CLOCK_RANGE;
   /* CHV DPLL can't generate 216-240 MHz */
   if (IS_CHERRYVIEW(dev_priv) && clock > 216000 && clock < 240000) return MODE_CLOCK_RANGE;
   return MODE_OK;
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,41 +1,41 @@
 void i915_gem_restore_gtt_mappings(struct drm_i915_private *dev_priv) {
   struct i915_ggtt *ggtt = &dev_priv->ggtt;
   struct drm_i915_gem_object *obj, *on;
   i915_check_and_clear_faults(dev_priv);
   /* First fill our portion of the GTT with scratch pages */
   ggtt->base.clear_range(&ggtt->base, ggtt->base.start, ggtt->base.total);
   ggtt->base.closed = true; /* skip rewriting PTE on VMA unbind */
   /* clflush objects bound into the GGTT and rebind them. */
   list_for_each_entry_safe(obj, on, &dev_priv->mm.bound_list, global_link) {
     bool ggtt_bound = false;
     struct i915_vma *vma;
     list_for_each_entry(vma, &obj->vma_list, obj_link) {
       if (vma->vm != &ggtt->base) continue;
       if (!i915_vma_unbind(vma)) continue;
       WARN_ON(i915_vma_bind(vma, obj->cache_level, PIN_UPDATE));
       ggtt_bound = true;
     }
     if (ggtt_bound) WARN_ON(i915_gem_object_set_to_gtt_domain(obj, false));
   }
   ggtt->base.closed = false;
   if (INTEL_GEN(dev_priv) >= 8) {
-    if (IS_CHERRYVIEW(dev_priv) || IS_BROXTON(dev_priv))
+    if (IS_CHERRYVIEW(dev_priv) || IS_GEN9_LP(dev_priv))
       chv_setup_private_ppat(dev_priv);
     else
       bdw_setup_private_ppat(dev_priv);
     return;
   }
   if (USES_PPGTT(dev_priv)) {
     struct i915_address_space *vm;
     list_for_each_entry(vm, &dev_priv->vm_list, global_link) {
       /* TODO: Perhaps it shouldn't be gen6 specific */
       struct i915_hw_ppgtt *ppgtt;
       if (i915_is_ggtt(vm))
         ppgtt = dev_priv->mm.aliasing_ppgtt;
       else
         ppgtt = i915_vm_to_ppgtt(vm);
       gen6_write_page_range(dev_priv, &ppgtt->pd, 0, ppgtt->base.total);
     }
   }
   i915_ggtt_flush(dev_priv);
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,28 +1,28 @@
 static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) {
   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
   struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base);
   enum port port;
   DRM_DEBUG_KMS("\n");
   for_each_dsi_port(port, intel_dsi->ports) {
     /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */
-    i915_reg_t port_ctrl = IS_BROXTON(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
+    i915_reg_t port_ctrl = IS_GEN9_LP(dev_priv) ? BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A);
     u32 val;
     I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER);
     usleep_range(2000, 2500);
     I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_EXIT);
     usleep_range(2000, 2500);
     I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | ULPS_STATE_ENTER);
     usleep_range(2000, 2500);
     /* Wait till Clock lanes are in LP-00 state for MIPI Port A
      * only. MIPI Port C has no similar bit for checking
      */
     if (intel_wait_for_register(dev_priv, port_ctrl, AFE_LATCHOUT, 0, 30)) DRM_ERROR("DSI LP not going Low\n");
     /* Disable MIPI PHY transparent latch */
     val = I915_READ(port_ctrl);
     I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD);
     usleep_range(1000, 1500);
     I915_WRITE(MIPI_DEVICE_READY(port), 0x00);
     usleep_range(2000, 2500);
   }
   intel_disable_dsi_pll(encoder);
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,31 +1,31 @@
 static int ggtt_probe_common(struct i915_ggtt *ggtt, u64 size) {
   struct drm_i915_private *dev_priv = ggtt->base.i915;
   struct pci_dev *pdev = dev_priv->drm.pdev;
   phys_addr_t phys_addr;
   int ret;
   /* For Modern GENs the PTEs and register space are split in the BAR */
   phys_addr = pci_resource_start(pdev, 0) + pci_resource_len(pdev, 0) / 2;
   /*
    * On BXT writes larger than 64 bit to the GTT pagetable range will be
    * dropped. For WC mappings in general we have 64 byte burst writes
    * when the WC buffer is flushed, so we can't use it, but have to
    * resort to an uncached mapping. The WC issue is easily caught by the
    * readback check when writing GTT PTE entries.
    */
-  if (IS_BROXTON(dev_priv))
+  if (IS_GEN9_LP(dev_priv))
     ggtt->gsm = ioremap_nocache(phys_addr, size);
   else
     ggtt->gsm = ioremap_wc(phys_addr, size);
   if (!ggtt->gsm) {
     DRM_ERROR("Failed to map the ggtt page table\n");
     return -ENOMEM;
   }
   ret = setup_scratch_page(dev_priv, &ggtt->base.scratch_page, GFP_DMA32);
   if (ret) {
     DRM_ERROR("Scratch setup failed\n");
     /* iounmap will also get called at remove, but meh */
     iounmap(ggtt->gsm);
     return ret;
   }
   return 0;
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,7 +1,7 @@
 void intel_enable_dsi_pll(struct intel_encoder *encoder, const struct intel_crtc_state *config) {
   struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
   if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
     vlv_enable_dsi_pll(encoder, config);
-  else if (IS_BROXTON(dev_priv))
+  else if (IS_GEN9_LP(dev_priv))
     bxt_enable_dsi_pll(encoder, config);
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)