--- initial
+++ final
@@ -1,169 +1,169 @@
 static int nand_davinci_probe(struct platform_device *pdev) {
   struct davinci_nand_pdata *pdata;
   struct davinci_nand_info *info;
   struct resource *res1;
   struct resource *res2;
   void __iomem *vaddr;
   void __iomem *base;
   int ret;
   uint32_t val;
   struct mtd_info *mtd;
   pdata = nand_davinci_get_pdata(pdev);
   if (IS_ERR(pdata)) return PTR_ERR(pdata);
   /* insist on board-specific configuration */
   if (!pdata) return -ENODEV;
   /* which external chipselect will we be managing? */
   if (pdata->core_chipsel < 0 || pdata->core_chipsel > 3) return -ENODEV;
   info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
   if (!info) return -ENOMEM;
   platform_set_drvdata(pdev, info);
   res1 = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   res2 = platform_get_resource(pdev, IORESOURCE_MEM, 1);
   if (!res1 || !res2) {
     dev_err(&pdev->dev, "resource missing\n");
     return -EINVAL;
   }
   vaddr = devm_ioremap_resource(&pdev->dev, res1);
   if (IS_ERR(vaddr)) return PTR_ERR(vaddr);
   /*
    * This registers range is used to setup NAND settings. In case with
    * TI AEMIF driver, the same memory address range is requested already
    * by AEMIF, so we cannot request it twice, just ioremap.
    * The AEMIF and NAND drivers not use the same registers in this range.
    */
   base = devm_ioremap(&pdev->dev, res2->start, resource_size(res2));
   if (!base) {
     dev_err(&pdev->dev, "ioremap failed for resource %pR\n", res2);
     return -EADDRNOTAVAIL;
   }
   info->dev = &pdev->dev;
   info->base = base;
   info->vaddr = vaddr;
   mtd = nand_to_mtd(&info->chip);
   mtd->dev.parent = &pdev->dev;
   nand_set_flash_node(&info->chip, pdev->dev.of_node);
   info->chip.IO_ADDR_R = vaddr;
   info->chip.IO_ADDR_W = vaddr;
   info->chip.chip_delay = 0;
   info->chip.select_chip = nand_davinci_select_chip;
   /* options such as NAND_BBT_USE_FLASH */
   info->chip.bbt_options = pdata->bbt_options;
   /* options such as 16-bit widths */
   info->chip.options = pdata->options;
   info->chip.bbt_td = pdata->bbt_td;
   info->chip.bbt_md = pdata->bbt_md;
   info->timing = pdata->timing;
   info->current_cs = info->vaddr;
   info->core_chipsel = pdata->core_chipsel;
   info->mask_chipsel = pdata->mask_chipsel;
   /* use nandboot-capable ALE/CLE masks by default */
   info->mask_ale = pdata->mask_ale ?: MASK_ALE;
   info->mask_cle = pdata->mask_cle ?: MASK_CLE;
   /* Set address of hardware control function */
   info->chip.cmd_ctrl = nand_davinci_hwcontrol;
   info->chip.dev_ready = nand_davinci_dev_ready;
   /* Speed up buffer I/O */
   info->chip.read_buf = nand_davinci_read_buf;
   info->chip.write_buf = nand_davinci_write_buf;
   /* Use board-specific ECC config */
   info->chip.ecc.mode = pdata->ecc_mode;
   spin_lock_irq(&davinci_nand_lock);
   /* put CSxNAND into NAND mode */
   val = davinci_nand_readl(info, NANDFCR_OFFSET);
   val |= BIT(info->core_chipsel);
   davinci_nand_writel(info, NANDFCR_OFFSET, val);
   spin_unlock_irq(&davinci_nand_lock);
   /* Scan to find existence of the device(s) */
   ret = nand_scan_ident(mtd, pdata->mask_chipsel ? 2 : 1, NULL);
   if (ret < 0) {
     dev_dbg(&pdev->dev, "no NAND chip(s) found\n");
     return ret;
   }
   switch (info->chip.ecc.mode) {
   case NAND_ECC_NONE: pdata->ecc_bits = 0; break;
   case NAND_ECC_SOFT:
     pdata->ecc_bits = 0;
     /*
      * This driver expects Hamming based ECC when ecc_mode is set
      * to NAND_ECC_SOFT. Force ecc.algo to NAND_ECC_HAMMING to
      * avoid adding an extra ->ecc_algo field to
      * davinci_nand_pdata.
      */
     info->chip.ecc.algo = NAND_ECC_HAMMING;
     break;
   case NAND_ECC_HW:
     if (pdata->ecc_bits == 4) {
       /* No sanity checks:  CPUs must support this,
        * and the chips may not use NAND_BUSWIDTH_16.
        */
       /* No sharing 4-bit hardware between chipselects yet */
       spin_lock_irq(&davinci_nand_lock);
       if (ecc4_busy)
         ret = -EBUSY;
       else
         ecc4_busy = true;
       spin_unlock_irq(&davinci_nand_lock);
       if (ret == -EBUSY) return ret;
       info->chip.ecc.calculate = nand_davinci_calculate_4bit;
       info->chip.ecc.correct = nand_davinci_correct_4bit;
       info->chip.ecc.hwctl = nand_davinci_hwctl_4bit;
       info->chip.ecc.bytes = 10;
       info->chip.ecc.options = NAND_ECC_GENERIC_ERASED_CHECK;
       info->chip.ecc.algo = NAND_ECC_BCH;
     } else {
       /* 1bit ecc hamming */
       info->chip.ecc.calculate = nand_davinci_calculate_1bit;
       info->chip.ecc.correct = nand_davinci_correct_1bit;
       info->chip.ecc.hwctl = nand_davinci_hwctl_1bit;
       info->chip.ecc.bytes = 3;
       info->chip.ecc.algo = NAND_ECC_HAMMING;
     }
     info->chip.ecc.size = 512;
     info->chip.ecc.strength = pdata->ecc_bits;
     break;
   default: return -EINVAL;
   }
   /* Update ECC layout if needed ... for 1-bit HW ECC, the default
    * is OK, but it allocates 6 bytes when only 3 are needed (for
    * each 512 bytes).  For the 4-bit HW ECC, that default is not
    * usable:  10 bytes are needed, not 6.
    */
   if (pdata->ecc_bits == 4) {
     int chunks = mtd->writesize / 512;
     if (!chunks || mtd->oobsize < 16) {
       dev_dbg(&pdev->dev, "too small\n");
       ret = -EINVAL;
       goto err;
     }
     /* For small page chips, preserve the manufacturer's
      * badblock marking data ... and make sure a flash BBT
      * table marker fits in the free bytes.
      */
     if (chunks == 1) {
       mtd_set_ooblayout(mtd, &hwecc4_small_ooblayout_ops);
     } else if (chunks == 4 || chunks == 8) {
       mtd_set_ooblayout(mtd, &nand_ooblayout_lp_ops);
       info->chip.ecc.mode = NAND_ECC_HW_OOB_FIRST;
     } else {
       ret = -EIO;
       goto err;
     }
   }
   ret = nand_scan_tail(mtd);
   if (ret < 0) goto err;
   if (pdata->parts)
-    ret = mtd_device_parse_register(mtd, NULL, NULL, pdata->parts, pdata->nr_parts);
+    ret = mtd_device_register(mtd, pdata->parts, pdata->nr_parts);
   else
     ret = mtd_device_register(mtd, NULL, 0);
   if (ret < 0) goto err_cleanup_nand;
   val = davinci_nand_readl(info, NRCSR_OFFSET);
   dev_info(&pdev->dev, "controller rev. %d.%d\n", (val >> 8) & 0xff, val & 0xff);
   return 0;
 err_cleanup_nand:
   nand_cleanup(&info->chip);
 err:
   spin_lock_irq(&davinci_nand_lock);
   if (info->chip.ecc.mode == NAND_ECC_HW_SYNDROME) ecc4_busy = false;
   spin_unlock_irq(&davinci_nand_lock);
   return ret;
 }<sep>@@
expression e1,e2,e3;
@@
-       mtd_device_parse_register
+       mtd_device_register
         (e1,
-                                      NULL, NULL,
                                       e2,e3)