--- initial
+++ final
@@ -1,113 +1,113 @@
 static void dwc2_hc_chhltd_intr_dma(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan, int chnum, struct dwc2_qtd *qtd) {
   u32 hcintmsk;
   int out_nak_enh = 0;
   if (dbg_hc(chan)) dev_vdbg(hsotg->dev, "--Host Channel %d Interrupt: DMA Channel Halted--\n", chnum);
   /*
    * For core with OUT NAK enhancement, the flow for high-speed
    * CONTROL/BULK OUT is handled a little differently
    */
   if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_2_71a) {
     if (chan->speed == USB_SPEED_HIGH && !chan->ep_is_in && (chan->ep_type == USB_ENDPOINT_XFER_CONTROL || chan->ep_type == USB_ENDPOINT_XFER_BULK)) { out_nak_enh = 1; }
   }
   if (chan->halt_status == DWC2_HC_XFER_URB_DEQUEUE || (chan->halt_status == DWC2_HC_XFER_AHB_ERR && !hsotg->params.dma_desc_enable)) {
     if (hsotg->params.dma_desc_enable)
       dwc2_hcd_complete_xfer_ddma(hsotg, chan, chnum, chan->halt_status);
     else
       /*
        * Just release the channel. A dequeue can happen on a
        * transfer timeout. In the case of an AHB Error, the
        * channel was forced to halt because there's no way to
        * gracefully recover.
        */
       dwc2_release_channel(hsotg, chan, qtd, chan->halt_status);
     return;
   }
-  hcintmsk = dwc2_readl(hsotg->regs + HCINTMSK(chnum));
+  hcintmsk = dwc2_readl(hsotg, HCINTMSK(chnum));
   if (chan->hcint & HCINTMSK_XFERCOMPL) {
     /*
      * Todo: This is here because of a possible hardware bug. Spec
      * says that on SPLIT-ISOC OUT transfers in DMA mode that a HALT
      * interrupt w/ACK bit set should occur, but I only see the
      * XFERCOMP bit, even with it masked out. This is a workaround
      * for that behavior. Should fix this when hardware is fixed.
      */
     if (chan->ep_type == USB_ENDPOINT_XFER_ISOC && !chan->ep_is_in) dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
     dwc2_hc_xfercomp_intr(hsotg, chan, chnum, qtd);
   } else if (chan->hcint & HCINTMSK_STALL) {
     dwc2_hc_stall_intr(hsotg, chan, chnum, qtd);
   } else if ((chan->hcint & HCINTMSK_XACTERR) && !hsotg->params.dma_desc_enable) {
     if (out_nak_enh) {
       if (chan->hcint & (HCINTMSK_NYET | HCINTMSK_NAK | HCINTMSK_ACK)) {
         dev_vdbg(hsotg->dev, "XactErr with NYET/NAK/ACK\n");
         qtd->error_count = 0;
       } else {
         dev_vdbg(hsotg->dev, "XactErr without NYET/NAK/ACK\n");
       }
     }
     /*
      * Must handle xacterr before nak or ack. Could get a xacterr
      * at the same time as either of these on a BULK/CONTROL OUT
      * that started with a PING. The xacterr takes precedence.
      */
     dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
   } else if ((chan->hcint & HCINTMSK_XCS_XACT) && hsotg->params.dma_desc_enable) {
     dwc2_hc_xacterr_intr(hsotg, chan, chnum, qtd);
   } else if ((chan->hcint & HCINTMSK_AHBERR) && hsotg->params.dma_desc_enable) {
     dwc2_hc_ahberr_intr(hsotg, chan, chnum, qtd);
   } else if (chan->hcint & HCINTMSK_BBLERR) {
     dwc2_hc_babble_intr(hsotg, chan, chnum, qtd);
   } else if (chan->hcint & HCINTMSK_FRMOVRUN) {
     dwc2_hc_frmovrun_intr(hsotg, chan, chnum, qtd);
   } else if (!out_nak_enh) {
     if (chan->hcint & HCINTMSK_NYET) {
       /*
        * Must handle nyet before nak or ack. Could get a nyet
        * at the same time as either of those on a BULK/CONTROL
        * OUT that started with a PING. The nyet takes
        * precedence.
        */
       dwc2_hc_nyet_intr(hsotg, chan, chnum, qtd);
     } else if ((chan->hcint & HCINTMSK_NAK) && !(hcintmsk & HCINTMSK_NAK)) {
       /*
        * If nak is not masked, it's because a non-split IN
        * transfer is in an error state. In that case, the nak
        * is handled by the nak interrupt handler, not here.
        * Handle nak here for BULK/CONTROL OUT transfers, which
        * halt on a NAK to allow rewinding the buffer pointer.
        */
       dwc2_hc_nak_intr(hsotg, chan, chnum, qtd);
     } else if ((chan->hcint & HCINTMSK_ACK) && !(hcintmsk & HCINTMSK_ACK)) {
       /*
        * If ack is not masked, it's because a non-split IN
        * transfer is in an error state. In that case, the ack
        * is handled by the ack interrupt handler, not here.
        * Handle ack here for split transfers. Start splits
        * halt on ACK.
        */
       dwc2_hc_ack_intr(hsotg, chan, chnum, qtd);
     } else {
       if (chan->ep_type == USB_ENDPOINT_XFER_INT || chan->ep_type == USB_ENDPOINT_XFER_ISOC) {
         /*
          * A periodic transfer halted with no other
          * channel interrupts set. Assume it was halted
          * by the core because it could not be completed
          * in its scheduled (micro)frame.
          */
         dev_dbg(hsotg->dev, "%s: Halt channel %d (assume incomplete periodic transfer)\n", __func__, chnum);
         dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_PERIODIC_INCOMPLETE);
       } else {
         dev_err(hsotg->dev, "%s: Channel %d - ChHltd set, but reason is unknown\n", __func__, chnum);
-        dev_err(hsotg->dev, "hcint 0x%08x, intsts 0x%08x\n", chan->hcint, dwc2_readl(hsotg->regs + GINTSTS));
+        dev_err(hsotg->dev, "hcint 0x%08x, intsts 0x%08x\n", chan->hcint, dwc2_readl(hsotg, GINTSTS));
         goto error;
       }
     }
   } else {
     dev_info(hsotg->dev, "NYET/NAK/ACK/other in non-error case, 0x%08x\n", chan->hcint);
   error:
     /* Failthrough: use 3-strikes rule */
     qtd->error_count++;
     dwc2_update_urb_state_abn(hsotg, chan, chnum, qtd->urb, qtd, DWC2_HC_XFER_XACT_ERR);
     dwc2_hcd_save_data_toggle(hsotg, chan, chnum, qtd);
     dwc2_halt_channel(hsotg, chan, qtd, DWC2_HC_XFER_XACT_ERR);
   }
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)