--- initial
+++ final
@@ -1,112 +1,112 @@
 static int lpc32xx_nand_probe(struct platform_device *pdev) {
   struct lpc32xx_nand_host *host;
   struct mtd_info *mtd;
   struct nand_chip *nand_chip;
   struct resource *rc;
   int res;
   /* Allocate memory for the device structure (and zero it) */
   host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
   if (!host) return -ENOMEM;
   host->pdev = pdev;
   rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   host->io_base = devm_ioremap_resource(&pdev->dev, rc);
   if (IS_ERR(host->io_base)) return PTR_ERR(host->io_base);
   host->io_base_phy = rc->start;
   nand_chip = &host->nand_chip;
   mtd = nand_to_mtd(nand_chip);
   if (pdev->dev.of_node) host->ncfg = lpc32xx_parse_dt(&pdev->dev);
   if (!host->ncfg) {
     dev_err(&pdev->dev, "Missing or bad NAND config from device tree\n");
     return -ENOENT;
   }
   if (host->ncfg->wp_gpio == -EPROBE_DEFER) return -EPROBE_DEFER;
   if (gpio_is_valid(host->ncfg->wp_gpio) && gpio_request(host->ncfg->wp_gpio, "NAND WP")) {
     dev_err(&pdev->dev, "GPIO not available\n");
     return -EBUSY;
   }
   lpc32xx_wp_disable(host);
   host->pdata = dev_get_platdata(&pdev->dev);
   /* link the private data structures */
   nand_set_controller_data(nand_chip, host);
   nand_set_flash_node(nand_chip, pdev->dev.of_node);
   mtd->dev.parent = &pdev->dev;
   /* Get NAND clock */
   host->clk = clk_get(&pdev->dev, NULL);
   if (IS_ERR(host->clk)) {
     dev_err(&pdev->dev, "Clock initialization failure\n");
     res = -ENOENT;
     goto free_gpio;
   }
   res = clk_prepare_enable(host->clk);
   if (res) goto put_clk;
   nand_chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
   nand_chip->legacy.dev_ready = lpc32xx_nand_device_ready;
-  nand_chip->chip_delay = 25; /* us */
+  nand_chip->legacy.chip_delay = 25; /* us */
   nand_chip->legacy.IO_ADDR_R = MLC_DATA(host->io_base);
   nand_chip->legacy.IO_ADDR_W = MLC_DATA(host->io_base);
   /* Init NAND controller */
   lpc32xx_nand_setup(host);
   platform_set_drvdata(pdev, host);
   /* Initialize function pointers */
   nand_chip->ecc.hwctl = lpc32xx_ecc_enable;
   nand_chip->ecc.read_page_raw = lpc32xx_read_page;
   nand_chip->ecc.read_page = lpc32xx_read_page;
   nand_chip->ecc.write_page_raw = lpc32xx_write_page_lowlevel;
   nand_chip->ecc.write_page = lpc32xx_write_page_lowlevel;
   nand_chip->ecc.write_oob = lpc32xx_write_oob;
   nand_chip->ecc.read_oob = lpc32xx_read_oob;
   nand_chip->ecc.strength = 4;
   nand_chip->ecc.bytes = 10;
   nand_chip->legacy.waitfunc = lpc32xx_waitfunc;
   nand_chip->options = NAND_NO_SUBPAGE_WRITE;
   nand_chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB;
   nand_chip->bbt_td = &lpc32xx_nand_bbt;
   nand_chip->bbt_md = &lpc32xx_nand_bbt_mirror;
   if (use_dma) {
     res = lpc32xx_dma_setup(host);
     if (res) {
       res = -EIO;
       goto unprepare_clk;
     }
   }
   /* initially clear interrupt status */
   readb(MLC_IRQ_SR(host->io_base));
   init_completion(&host->comp_nand);
   init_completion(&host->comp_controller);
   host->irq = platform_get_irq(pdev, 0);
   if (host->irq < 0) {
     dev_err(&pdev->dev, "failed to get platform irq\n");
     res = -EINVAL;
     goto release_dma_chan;
   }
   if (request_irq(host->irq, (irq_handler_t)&lpc3xxx_nand_irq, IRQF_TRIGGER_HIGH, DRV_NAME, host)) {
     dev_err(&pdev->dev, "Error requesting NAND IRQ\n");
     res = -ENXIO;
     goto release_dma_chan;
   }
   /*
    * Scan to find existence of the device and get the type of NAND device:
    * SMALL block or LARGE block.
    */
   nand_chip->dummy_controller.ops = &lpc32xx_nand_controller_ops;
   res = nand_scan(nand_chip, 1);
   if (res) goto free_irq;
   mtd->name = DRV_NAME;
   res = mtd_device_register(mtd, host->ncfg->parts, host->ncfg->num_parts);
   if (res) goto cleanup_nand;
   return 0;
 cleanup_nand:
   nand_cleanup(nand_chip);
 free_irq:
   free_irq(host->irq, host);
 release_dma_chan:
   if (use_dma) dma_release_channel(host->dma_chan);
 unprepare_clk:
   clk_disable_unprepare(host->clk);
 put_clk:
   clk_put(host->clk);
 free_gpio:
   lpc32xx_wp_enable(host);
   gpio_free(host->ncfg->wp_gpio);
   return res;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay