imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,21 +1,21 @@
 static struct drm_i915_gem_object *fake_dma_object(struct drm_i915_private *i915, u64 size) {
   struct drm_i915_gem_object *obj;
   GEM_BUG_ON(!size);
   GEM_BUG_ON(!IS_ALIGNED(size, I915_GTT_PAGE_SIZE));
   if (overflows_type(size, obj->base.size)) return ERR_PTR(-E2BIG);
   obj = i915_gem_object_alloc(i915);
   if (!obj) goto err;
   drm_gem_private_object_init(&i915->drm, &obj->base, size);
   i915_gem_object_init(obj, &fake_ops);
-  obj->base.write_domain = I915_GEM_DOMAIN_CPU;
-  obj->base.read_domains = I915_GEM_DOMAIN_CPU;
+  obj->write_domain = I915_GEM_DOMAIN_CPU;
+  obj->read_domains = I915_GEM_DOMAIN_CPU;
   obj->cache_level = I915_CACHE_NONE;
   /* Preallocate the "backing storage" */
   if (i915_gem_object_pin_pages(obj)) goto err_obj;
   i915_gem_object_unpin_pages(obj);
   return obj;
 err_obj:
   i915_gem_object_put(obj);
 err:
   return ERR_PTR(-ENOMEM);
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,30 +1,30 @@
 int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, unsigned int *needs_clflush) {
   int ret;
   lockdep_assert_held(&obj->base.dev->struct_mutex);
   *needs_clflush = 0;
   if (!i915_gem_object_has_struct_page(obj)) return -ENODEV;
   ret = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED, MAX_SCHEDULE_TIMEOUT, NULL);
   if (ret) return ret;
   ret = i915_gem_object_pin_pages(obj);
   if (ret) return ret;
   if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_READ || !static_cpu_has(X86_FEATURE_CLFLUSH)) {
     ret = i915_gem_object_set_to_cpu_domain(obj, false);
     if (ret)
       goto err_unpin;
     else
       goto out;
   }
   flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
   /* If we're not in the cpu read domain, set ourself into the gtt
    * read domain and manually flush cachelines (if required). This
    * optimizes for the case when the gpu will dirty the data
    * anyway again before the next pread happens.
    */
-  if (!obj->cache_dirty && !(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) *needs_clflush = CLFLUSH_BEFORE;
+  if (!obj->cache_dirty && !(obj->read_domains & I915_GEM_DOMAIN_CPU)) *needs_clflush = CLFLUSH_BEFORE;
 out:
   /* return with the pages pinned */
   return 0;
 err_unpin:
   i915_gem_object_unpin_pages(obj);
   return ret;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains
--- initial
+++ final
@@ -1,39 +1,39 @@
 int i915_gem_obj_prepare_shmem_write(struct drm_i915_gem_object *obj, unsigned int *needs_clflush) {
   int ret;
   lockdep_assert_held(&obj->base.dev->struct_mutex);
   *needs_clflush = 0;
   if (!i915_gem_object_has_struct_page(obj)) return -ENODEV;
   ret = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED | I915_WAIT_ALL, MAX_SCHEDULE_TIMEOUT, NULL);
   if (ret) return ret;
   ret = i915_gem_object_pin_pages(obj);
   if (ret) return ret;
   if (obj->cache_coherent & I915_BO_CACHE_COHERENT_FOR_WRITE || !static_cpu_has(X86_FEATURE_CLFLUSH)) {
     ret = i915_gem_object_set_to_cpu_domain(obj, true);
     if (ret)
       goto err_unpin;
     else
       goto out;
   }
   flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
   /* If we're not in the cpu write domain, set ourself into the
    * gtt write domain and manually flush cachelines (as required).
    * This optimizes for the case when the gpu will use the data
    * right away and we therefore have to clflush anyway.
    */
   if (!obj->cache_dirty) {
     *needs_clflush |= CLFLUSH_AFTER;
     /*
      * Same trick applies to invalidate partially written
      * cachelines read before writing.
      */
-    if (!(obj->base.read_domains & I915_GEM_DOMAIN_CPU)) *needs_clflush |= CLFLUSH_BEFORE;
+    if (!(obj->read_domains & I915_GEM_DOMAIN_CPU)) *needs_clflush |= CLFLUSH_BEFORE;
   }
 out:
   intel_fb_obj_invalidate(obj, ORIGIN_CPU);
   obj->mm.dirty = true;
   /* return with the pages pinned */
   return 0;
 err_unpin:
   i915_gem_object_unpin_pages(obj);
   return ret;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains
--- initial
+++ final
@@ -1,52 +1,52 @@
 struct drm_i915_gem_object *i915_gem_object_create(struct drm_i915_private *dev_priv, u64 size) {
   struct drm_i915_gem_object *obj;
   struct address_space *mapping;
   unsigned int cache_level;
   gfp_t mask;
   int ret;
   /* There is a prevalence of the assumption that we fit the object's
    * page count inside a 32bit _signed_ variable. Let's document this and
    * catch if we ever need to fix it. In the meantime, if you do spot
    * such a local variable, please consider fixing!
    */
   if (size >> PAGE_SHIFT > INT_MAX) return ERR_PTR(-E2BIG);
   if (overflows_type(size, obj->base.size)) return ERR_PTR(-E2BIG);
   obj = i915_gem_object_alloc(dev_priv);
   if (obj == NULL) return ERR_PTR(-ENOMEM);
   ret = i915_gem_object_create_shmem(&dev_priv->drm, &obj->base, size);
   if (ret) goto fail;
   mask = GFP_HIGHUSER | __GFP_RECLAIMABLE;
   if (IS_I965GM(dev_priv) || IS_I965G(dev_priv)) {
     /* 965gm cannot relocate objects above 4GiB. */
     mask &= ~__GFP_HIGHMEM;
     mask |= __GFP_DMA32;
   }
   mapping = obj->base.filp->f_mapping;
   mapping_set_gfp_mask(mapping, mask);
   GEM_BUG_ON(!(mapping_gfp_mask(mapping) & __GFP_RECLAIM));
   i915_gem_object_init(obj, &i915_gem_object_ops);
-  obj->base.write_domain = I915_GEM_DOMAIN_CPU;
-  obj->base.read_domains = I915_GEM_DOMAIN_CPU;
+  obj->write_domain = I915_GEM_DOMAIN_CPU;
+  obj->read_domains = I915_GEM_DOMAIN_CPU;
   if (HAS_LLC(dev_priv))
     /* On some devices, we can have the GPU use the LLC (the CPU
      * cache) for about a 10% performance improvement
      * compared to uncached.  Graphics requests other than
      * display scanout are coherent with the CPU in
      * accessing this cache.  This means in this mode we
      * don't need to clflush on the CPU side, and on the
      * GPU side we only need to flush internal caches to
      * get data visible to the CPU.
      *
      * However, we maintain the display planes as UC, and so
      * need to rebind when first used as such.
      */
     cache_level = I915_CACHE_LLC;
   else
     cache_level = I915_CACHE_NONE;
   i915_gem_object_set_cache_coherency(obj, cache_level);
   trace_i915_gem_object_create(obj);
   return obj;
 fail:
   i915_gem_object_free(obj);
   return ERR_PTR(ret);
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,30 +1,30 @@
 struct drm_i915_gem_object *i915_gem_object_create_from_data(struct drm_i915_private *dev_priv, const void *data, size_t size) {
   struct drm_i915_gem_object *obj;
   struct file *file;
   size_t offset;
   int err;
   obj = i915_gem_object_create(dev_priv, round_up(size, PAGE_SIZE));
   if (IS_ERR(obj)) return obj;
-  GEM_BUG_ON(obj->base.write_domain != I915_GEM_DOMAIN_CPU);
+  GEM_BUG_ON(obj->write_domain != I915_GEM_DOMAIN_CPU);
   file = obj->base.filp;
   offset = 0;
   do {
     unsigned int len = min_t(typeof(size), size, PAGE_SIZE);
     struct page *page;
     void *pgdata, *vaddr;
     err = pagecache_write_begin(file, file->f_mapping, offset, len, 0, &page, &pgdata);
     if (err < 0) goto fail;
     vaddr = kmap(page);
     memcpy(vaddr, data, len);
     kunmap(page);
     err = pagecache_write_end(file, file->f_mapping, offset, len, len, page, pgdata);
     if (err < 0) goto fail;
     size -= len;
     data += len;
     offset += len;
   } while (size);
   return obj;
 fail:
   i915_gem_object_put(obj);
   return ERR_PTR(err);
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,59 +1,59 @@
 struct i915_vma *i915_gem_object_pin_to_display_plane(struct drm_i915_gem_object *obj, u32 alignment, const struct i915_ggtt_view *view) {
   struct i915_vma *vma;
   int ret;
   lockdep_assert_held(&obj->base.dev->struct_mutex);
   /* Mark the global pin early so that we account for the
    * display coherency whilst setting up the cache domains.
    */
   obj->pin_global++;
   /* The display engine is not coherent with the LLC cache on gen6.  As
    * a result, we make sure that the pinning that is about to occur is
    * done with uncached PTEs. This is lowest common denominator for all
    * chipsets.
    *
    * However for gen6+, we could do better by using the GFDT bit instead
    * of uncaching, which would allow us to flush all the LLC-cached data
    * with that bit in the PTE to main memory with just one PIPE_CONTROL.
    */
   ret = i915_gem_object_set_cache_level(obj, HAS_WT(to_i915(obj->base.dev)) ? I915_CACHE_WT : I915_CACHE_NONE);
   if (ret) {
     vma = ERR_PTR(ret);
     goto err_unpin_global;
   }
   /* As the user may map the buffer once pinned in the display plane
    * (e.g. libkms for the bootup splash), we have to ensure that we
    * always use map_and_fenceable for all scanout buffers. However,
    * it may simply be too big to fit into mappable, in which case
    * put it anyway and hope that userspace can cope (but always first
    * try to preserve the existing ABI).
    */
   vma = ERR_PTR(-ENOSPC);
   if (!view || view->type == I915_GGTT_VIEW_NORMAL) vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, PIN_MAPPABLE | PIN_NONBLOCK);
   if (IS_ERR(vma)) {
     struct drm_i915_private *i915 = to_i915(obj->base.dev);
     unsigned int flags;
     /* Valleyview is definitely limited to scanning out the first
      * 512MiB. Lets presume this behaviour was inherited from the
      * g4x display engine and that all earlier gen are similarly
      * limited. Testing suggests that it is a little more
      * complicated than this. For example, Cherryview appears quite
      * happy to scanout from anywhere within its global aperture.
      */
     flags = 0;
     if (HAS_GMCH_DISPLAY(i915)) flags = PIN_MAPPABLE;
     vma = i915_gem_object_ggtt_pin(obj, view, 0, alignment, flags);
   }
   if (IS_ERR(vma)) goto err_unpin_global;
   vma->display_alignment = max_t(u64, vma->display_alignment, alignment);
   /* Treat this as an end-of-frame, like intel_user_framebuffer_dirty() */
   __i915_gem_object_flush_for_display(obj);
   intel_fb_obj_flush(obj, ORIGIN_DIRTYFB);
   /* It should now be out of any other write domains, and we can update
    * the domain values for our changes.
    */
-  obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
+  obj->read_domains |= I915_GEM_DOMAIN_GTT;
   return vma;
 err_unpin_global:
   obj->pin_global--;
   return vma;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains
--- initial
+++ final
@@ -1,21 +1,21 @@
 int i915_gem_object_set_to_cpu_domain(struct drm_i915_gem_object *obj, bool write) {
   int ret;
   lockdep_assert_held(&obj->base.dev->struct_mutex);
   ret = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED | (write ? I915_WAIT_ALL : 0), MAX_SCHEDULE_TIMEOUT, NULL);
   if (ret) return ret;
   flush_write_domain(obj, ~I915_GEM_DOMAIN_CPU);
   /* Flush the CPU cache if it's still invalid. */
-  if ((obj->base.read_domains & I915_GEM_DOMAIN_CPU) == 0) {
+  if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) {
     i915_gem_clflush_object(obj, I915_CLFLUSH_SYNC);
-    obj->base.read_domains |= I915_GEM_DOMAIN_CPU;
+    obj->read_domains |= I915_GEM_DOMAIN_CPU;
   }
   /* It should now be out of any other write domains, and we can update
    * the domain values for our changes.
    */
-  GEM_BUG_ON(obj->base.write_domain & ~I915_GEM_DOMAIN_CPU);
+  GEM_BUG_ON(obj->write_domain & ~I915_GEM_DOMAIN_CPU);
   /* If we're writing through the CPU, then the GPU read domains will
    * need to be invalidated at next use.
    */
   if (write) __start_cpu_write(obj);
   return 0;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,35 +1,35 @@
 int i915_gem_object_set_to_gtt_domain(struct drm_i915_gem_object *obj, bool write) {
   int ret;
   lockdep_assert_held(&obj->base.dev->struct_mutex);
   ret = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED | (write ? I915_WAIT_ALL : 0), MAX_SCHEDULE_TIMEOUT, NULL);
   if (ret) return ret;
-  if (obj->base.write_domain == I915_GEM_DOMAIN_GTT) return 0;
+  if (obj->write_domain == I915_GEM_DOMAIN_GTT) return 0;
   /* Flush and acquire obj->pages so that we are coherent through
    * direct access in memory with previous cached writes through
    * shmemfs and that our cache domain tracking remains valid.
    * For example, if the obj->filp was moved to swap without us
    * being notified and releasing the pages, we would mistakenly
    * continue to assume that the obj remained out of the CPU cached
    * domain.
    */
   ret = i915_gem_object_pin_pages(obj);
   if (ret) return ret;
   flush_write_domain(obj, ~I915_GEM_DOMAIN_GTT);
   /* Serialise direct access to this object with the barriers for
    * coherent writes from the GPU, by effectively invalidating the
    * GTT domain upon first access.
    */
-  if ((obj->base.read_domains & I915_GEM_DOMAIN_GTT) == 0) mb();
+  if ((obj->read_domains & I915_GEM_DOMAIN_GTT) == 0) mb();
   /* It should now be out of any other write domains, and we can update
    * the domain values for our changes.
    */
-  GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
-  obj->base.read_domains |= I915_GEM_DOMAIN_GTT;
+  GEM_BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0);
+  obj->read_domains |= I915_GEM_DOMAIN_GTT;
   if (write) {
-    obj->base.read_domains = I915_GEM_DOMAIN_GTT;
-    obj->base.write_domain = I915_GEM_DOMAIN_GTT;
+    obj->read_domains = I915_GEM_DOMAIN_GTT;
+    obj->write_domain = I915_GEM_DOMAIN_GTT;
     obj->mm.dirty = true;
   }
   i915_gem_object_unpin_pages(obj);
   return 0;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,35 +1,35 @@
 int i915_gem_object_set_to_wc_domain(struct drm_i915_gem_object *obj, bool write) {
   int ret;
   lockdep_assert_held(&obj->base.dev->struct_mutex);
   ret = i915_gem_object_wait(obj, I915_WAIT_INTERRUPTIBLE | I915_WAIT_LOCKED | (write ? I915_WAIT_ALL : 0), MAX_SCHEDULE_TIMEOUT, NULL);
   if (ret) return ret;
-  if (obj->base.write_domain == I915_GEM_DOMAIN_WC) return 0;
+  if (obj->write_domain == I915_GEM_DOMAIN_WC) return 0;
   /* Flush and acquire obj->pages so that we are coherent through
    * direct access in memory with previous cached writes through
    * shmemfs and that our cache domain tracking remains valid.
    * For example, if the obj->filp was moved to swap without us
    * being notified and releasing the pages, we would mistakenly
    * continue to assume that the obj remained out of the CPU cached
    * domain.
    */
   ret = i915_gem_object_pin_pages(obj);
   if (ret) return ret;
   flush_write_domain(obj, ~I915_GEM_DOMAIN_WC);
   /* Serialise direct access to this object with the barriers for
    * coherent writes from the GPU, by effectively invalidating the
    * WC domain upon first access.
    */
-  if ((obj->base.read_domains & I915_GEM_DOMAIN_WC) == 0) mb();
+  if ((obj->read_domains & I915_GEM_DOMAIN_WC) == 0) mb();
   /* It should now be out of any other write domains, and we can update
    * the domain values for our changes.
    */
-  GEM_BUG_ON((obj->base.write_domain & ~I915_GEM_DOMAIN_WC) != 0);
-  obj->base.read_domains |= I915_GEM_DOMAIN_WC;
+  GEM_BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_WC) != 0);
+  obj->read_domains |= I915_GEM_DOMAIN_WC;
   if (write) {
-    obj->base.read_domains = I915_GEM_DOMAIN_WC;
-    obj->base.write_domain = I915_GEM_DOMAIN_WC;
+    obj->read_domains = I915_GEM_DOMAIN_WC;
+    obj->write_domain = I915_GEM_DOMAIN_WC;
     obj->mm.dirty = true;
   }
   i915_gem_object_unpin_pages(obj);
   return 0;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,16 +1,16 @@
 struct drm_i915_gem_object *i915_gem_object_create_internal(struct drm_i915_private *i915, phys_addr_t size) {
   struct drm_i915_gem_object *obj;
   unsigned int cache_level;
   GEM_BUG_ON(!size);
   GEM_BUG_ON(!IS_ALIGNED(size, PAGE_SIZE));
   if (overflows_type(size, obj->base.size)) return ERR_PTR(-E2BIG);
   obj = i915_gem_object_alloc(i915);
   if (!obj) return ERR_PTR(-ENOMEM);
   drm_gem_private_object_init(&i915->drm, &obj->base, size);
   i915_gem_object_init(obj, &i915_gem_object_internal_ops);
-  obj->base.read_domains = I915_GEM_DOMAIN_CPU;
-  obj->base.write_domain = I915_GEM_DOMAIN_CPU;
+  obj->read_domains = I915_GEM_DOMAIN_CPU;
+  obj->write_domain = I915_GEM_DOMAIN_CPU;
   cache_level = HAS_LLC(i915) ? I915_CACHE_LLC : I915_CACHE_NONE;
   i915_gem_object_set_cache_coherency(obj, cache_level);
   return obj;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,17 +1,17 @@
 static struct drm_i915_gem_object *_i915_gem_object_create_stolen(struct drm_i915_private *dev_priv, struct drm_mm_node *stolen) {
   struct drm_i915_gem_object *obj;
   unsigned int cache_level;
   obj = i915_gem_object_alloc(dev_priv);
   if (obj == NULL) return NULL;
   drm_gem_private_object_init(&dev_priv->drm, &obj->base, stolen->size);
   i915_gem_object_init(obj, &i915_gem_object_stolen_ops);
   obj->stolen = stolen;
-  obj->base.read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT;
+  obj->read_domains = I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT;
   cache_level = HAS_LLC(dev_priv) ? I915_CACHE_LLC : I915_CACHE_NONE;
   i915_gem_object_set_cache_coherency(obj, cache_level);
   if (i915_gem_object_pin_pages(obj)) goto cleanup;
   return obj;
 cleanup:
   i915_gem_object_free(obj);
   return NULL;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains
--- initial
+++ final
@@ -1,43 +1,43 @@
 int i915_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *file) {
   struct drm_i915_private *dev_priv = to_i915(dev);
   struct drm_i915_gem_userptr *args = data;
   struct drm_i915_gem_object *obj;
   int ret;
   u32 handle;
   if (!HAS_LLC(dev_priv) && !HAS_SNOOP(dev_priv)) {
     /* We cannot support coherent userptr objects on hw without
      * LLC and broken snooping.
      */
     return -ENODEV;
   }
   if (args->flags & ~(I915_USERPTR_READ_ONLY | I915_USERPTR_UNSYNCHRONIZED)) return -EINVAL;
   if (offset_in_page(args->user_ptr | args->user_size)) return -EINVAL;
   if (!access_ok(args->flags & I915_USERPTR_READ_ONLY ? VERIFY_READ : VERIFY_WRITE, (char __user *)(unsigned long)args->user_ptr, args->user_size)) return -EFAULT;
   if (args->flags & I915_USERPTR_READ_ONLY) {
     /* On almost all of the current hw, we cannot tell the GPU that a
      * page is readonly, so this is just a placeholder in the uAPI.
      */
     return -ENODEV;
   }
   obj = i915_gem_object_alloc(dev_priv);
   if (obj == NULL) return -ENOMEM;
   drm_gem_private_object_init(dev, &obj->base, args->user_size);
   i915_gem_object_init(obj, &i915_gem_userptr_ops);
-  obj->base.read_domains = I915_GEM_DOMAIN_CPU;
-  obj->base.write_domain = I915_GEM_DOMAIN_CPU;
+  obj->read_domains = I915_GEM_DOMAIN_CPU;
+  obj->write_domain = I915_GEM_DOMAIN_CPU;
   i915_gem_object_set_cache_coherency(obj, I915_CACHE_LLC);
   obj->userptr.ptr = args->user_ptr;
   obj->userptr.read_only = !!(args->flags & I915_USERPTR_READ_ONLY);
   /* And keep a pointer to the current->mm for resolving the user pages
    * at binding. This means that we need to hook into the mmu_notifier
    * in order to detect if the mmu is destroyed.
    */
   ret = i915_gem_userptr_init__mm_struct(obj);
   if (ret == 0) ret = i915_gem_userptr_init__mmu_notifier(obj, args->flags);
   if (ret == 0) ret = drm_gem_handle_create(file, &obj->base, &handle);
   /* drop reference from allocate - handle holds it now */
   i915_gem_object_put(obj);
   if (ret) return ret;
   args->handle = handle;
   return 0;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain
--- initial
+++ final
@@ -1,19 +1,19 @@
 static void capture_bo(struct drm_i915_error_buffer *err, struct i915_vma *vma) {
   struct drm_i915_gem_object *obj = vma->obj;
   int i;
   err->size = obj->base.size;
   err->name = obj->base.name;
   for (i = 0; i < I915_NUM_ENGINES; i++)
     err->rseqno[i] = __active_get_seqno(&vma->last_read[i]);
   err->wseqno = __active_get_seqno(&obj->frontbuffer_write);
   err->engine = __active_get_engine_id(&obj->frontbuffer_write);
   err->gtt_offset = vma->node.start;
-  err->read_domains = obj->base.read_domains;
-  err->write_domain = obj->base.write_domain;
+  err->read_domains = obj->read_domains;
+  err->write_domain = obj->write_domain;
   err->fence_reg = vma->fence ? vma->fence->id : -1;
   err->tiling = i915_gem_object_get_tiling(obj);
   err->dirty = obj->mm.dirty;
   err->purgeable = obj->mm.madv != I915_MADV_WILLNEED;
   err->userptr = obj->userptr.mm != NULL;
   err->cache_level = obj->cache_level;
 }<sep>@@
struct drm_i915_gem_object *obj;
@@
- obj->base.read_domains
+ obj->read_domains

@@
struct drm_i915_gem_object *obj;
@@
- obj->base.write_domain
+ obj->write_domain