--- initial
+++ final
@@ -1,77 +1,77 @@
 int amdgpu_vm_init(struct amdgpu_device *adev, struct amdgpu_vm *vm, int vm_context, unsigned int pasid) {
   struct amdgpu_bo_param bp;
   struct amdgpu_bo *root;
   const unsigned align = min(AMDGPU_VM_PTB_ALIGN_SIZE, AMDGPU_VM_PTE_COUNT(adev) * 8);
   unsigned ring_instance;
   struct amdgpu_ring *ring;
   struct drm_sched_rq *rq;
   unsigned long size;
   uint64_t flags;
   int r, i;
   vm->va = RB_ROOT_CACHED;
   for (i = 0; i < AMDGPU_MAX_VMHUBS; i++)
     vm->reserved_vmid[i] = NULL;
   spin_lock_init(&vm->status_lock);
   INIT_LIST_HEAD(&vm->evicted);
   INIT_LIST_HEAD(&vm->relocated);
   INIT_LIST_HEAD(&vm->moved);
   INIT_LIST_HEAD(&vm->freed);
   /* create scheduler entity for page table updates */
   ring_instance = atomic_inc_return(&adev->vm_manager.vm_pte_next_ring);
   ring_instance %= adev->vm_manager.vm_pte_num_rings;
   ring = adev->vm_manager.vm_pte_rings[ring_instance];
   rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-  r = drm_sched_entity_init(&ring->sched, &vm->entity, rq, amdgpu_sched_jobs, NULL);
+  r = drm_sched_entity_init(&ring->sched, &vm->entity, rq, NULL);
   if (r) return r;
   vm->pte_support_ats = false;
   if (vm_context == AMDGPU_VM_CONTEXT_COMPUTE) {
     vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & AMDGPU_VM_USE_CPU_FOR_COMPUTE);
     if (adev->asic_type == CHIP_RAVEN) vm->pte_support_ats = true;
   } else {
     vm->use_cpu_for_update = !!(adev->vm_manager.vm_update_mode & AMDGPU_VM_USE_CPU_FOR_GFX);
   }
   DRM_DEBUG_DRIVER("VM update mode is %s\n", vm->use_cpu_for_update ? "CPU" : "SDMA");
   WARN_ONCE((vm->use_cpu_for_update & !amdgpu_vm_is_large_bar(adev)), "CPU update of VM recommended only for large BAR system\n");
   vm->last_update = NULL;
   flags = AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
   if (vm->use_cpu_for_update)
     flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
   else
     flags |= AMDGPU_GEM_CREATE_SHADOW;
   size = amdgpu_vm_bo_size(adev, adev->vm_manager.root_level);
   memset(&bp, 0, sizeof(bp));
   bp.size = size;
   bp.byte_align = align;
   bp.domain = AMDGPU_GEM_DOMAIN_VRAM;
   bp.flags = flags;
   bp.type = ttm_bo_type_kernel;
   bp.resv = NULL;
   r = amdgpu_bo_create(adev, &bp, &root);
   if (r) goto error_free_sched_entity;
   r = amdgpu_bo_reserve(root, true);
   if (r) goto error_free_root;
   r = amdgpu_vm_clear_bo(adev, vm, root, adev->vm_manager.root_level, vm->pte_support_ats);
   if (r) goto error_unreserve;
   amdgpu_vm_bo_base_init(&vm->root.base, vm, root);
   amdgpu_bo_unreserve(vm->root.base.bo);
   if (pasid) {
     unsigned long flags;
     spin_lock_irqsave(&adev->vm_manager.pasid_lock, flags);
     r = idr_alloc(&adev->vm_manager.pasid_idr, vm, pasid, pasid + 1, GFP_ATOMIC);
     spin_unlock_irqrestore(&adev->vm_manager.pasid_lock, flags);
     if (r < 0) goto error_free_root;
     vm->pasid = pasid;
   }
   INIT_KFIFO(vm->faults);
   vm->fault_credit = 16;
   return 0;
 error_unreserve:
   amdgpu_bo_unreserve(vm->root.base.bo);
 error_free_root:
   amdgpu_bo_unref(&vm->root.base.bo->shadow);
   amdgpu_bo_unref(&vm->root.base.bo);
   vm->root.base.bo = NULL;
 error_free_sched_entity:
   drm_sched_entity_fini(&ring->sched, &vm->entity);
   return r;
 }<sep>@@
expression e1,e2,e3,e4,d;
@@

 	drm_sched_entity_init(e1,e2,e3,
- 				  d,
 				  e4)