imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,16 +1,16 @@
 static void simple_thread_func(int cnt) {
   int array[6];
   int len = cnt % 5;
   int i;
   set_current_state(TASK_INTERRUPTIBLE);
   schedule_timeout(HZ);
   for (i = 0; i < len; i++)
     array[i] = i + 1;
   array[i] = 0;
   /* Silly tracepoints */
-  trace_foo_bar("hello", cnt, array, random_strings[len], tsk_cpus_allowed(current));
+  trace_foo_bar("hello", cnt, array, random_strings[len], &current->cpus_allowed);
   trace_foo_with_template_simple("HELLO", cnt);
   trace_foo_bar_with_cond("Some times print", cnt);
   trace_foo_with_template_cond("prints other times", cnt);
   trace_foo_with_template_print("I have to be different", cnt);
 }<sep>@@
expression current;
@@
-       tsk_cpus_allowed(current)
+       &current->cpus_allowed
--- initial
+++ final
@@ -1,25 +1,25 @@
 static int amdgpu_cgs_add_irq_source(struct cgs_device *cgs_device, unsigned src_id, unsigned num_types, cgs_irq_source_set_func_t set, cgs_irq_handler_func_t handler, void *private_data) {
   CGS_FUNC_ADEV;
   int ret = 0;
   struct cgs_irq_params *irq_params;
   struct amdgpu_irq_src *source = kzalloc(sizeof(struct amdgpu_irq_src), GFP_KERNEL);
   if (!source) return -ENOMEM;
   irq_params = kzalloc(sizeof(struct cgs_irq_params), GFP_KERNEL);
   if (!irq_params) {
     kfree(source);
     return -ENOMEM;
   }
   source->num_types = num_types;
   source->funcs = &cgs_irq_funcs;
   irq_params->src_id = src_id;
   irq_params->set = set;
   irq_params->handler = handler;
   irq_params->private_data = private_data;
   source->data = (void *)irq_params;
-  ret = amdgpu_irq_add_id(adev, src_id, source);
+  ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, src_id, source);
   if (ret) {
     kfree(irq_params);
     kfree(source);
   }
   return ret;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,34 +1,34 @@
 static int ci_dpm_sw_init(void *handle) {
   int ret;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-  ret = amdgpu_irq_add_id(adev, 230, &adev->pm.dpm.thermal.irq);
+  ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 230, &adev->pm.dpm.thermal.irq);
   if (ret) return ret;
-  ret = amdgpu_irq_add_id(adev, 231, &adev->pm.dpm.thermal.irq);
+  ret = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 231, &adev->pm.dpm.thermal.irq);
   if (ret) return ret;
   /* default to balanced state */
   adev->pm.dpm.state = POWER_STATE_TYPE_BALANCED;
   adev->pm.dpm.user_state = POWER_STATE_TYPE_BALANCED;
   adev->pm.dpm.forced_level = AMD_DPM_FORCED_LEVEL_AUTO;
   adev->pm.default_sclk = adev->clock.default_sclk;
   adev->pm.default_mclk = adev->clock.default_mclk;
   adev->pm.current_sclk = adev->clock.default_sclk;
   adev->pm.current_mclk = adev->clock.default_mclk;
   adev->pm.int_thermal_type = THERMAL_TYPE_NONE;
   ret = ci_dpm_init_microcode(adev);
   if (ret) return ret;
   if (amdgpu_dpm == 0) return 0;
   INIT_WORK(&adev->pm.dpm.thermal.work, amdgpu_dpm_thermal_work_handler);
   mutex_lock(&adev->pm.mutex);
   ret = ci_dpm_init(adev);
   if (ret) goto dpm_failed;
   adev->pm.dpm.current_ps = adev->pm.dpm.requested_ps = adev->pm.dpm.boot_ps;
   if (amdgpu_dpm == 1) amdgpu_pm_print_power_states(adev);
   mutex_unlock(&adev->pm.mutex);
   DRM_INFO("amdgpu: dpm initialized\n");
   return 0;
 dpm_failed:
   ci_dpm_fini(adev);
   mutex_unlock(&adev->pm.mutex);
   DRM_ERROR("amdgpu: dpm initialization failed\n");
   return ret;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,27 +1,27 @@
 static int cik_sdma_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   int r, i;
   r = cik_sdma_init_microcode(adev);
   if (r) {
     DRM_ERROR("Failed to load sdma firmware!\n");
     return r;
   }
   /* SDMA trap event */
-  r = amdgpu_irq_add_id(adev, 224, &adev->sdma.trap_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 224, &adev->sdma.trap_irq);
   if (r) return r;
   /* SDMA Privileged inst */
-  r = amdgpu_irq_add_id(adev, 241, &adev->sdma.illegal_inst_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 241, &adev->sdma.illegal_inst_irq);
   if (r) return r;
   /* SDMA Privileged inst */
-  r = amdgpu_irq_add_id(adev, 247, &adev->sdma.illegal_inst_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 247, &adev->sdma.illegal_inst_irq);
   if (r) return r;
   for (i = 0; i < adev->sdma.num_instances; i++) {
     ring = &adev->sdma.instance[i].ring;
     ring->ring_obj = NULL;
     sprintf(ring->name, "sdma%d", i);
     r = amdgpu_ring_init(adev, ring, 1024, &adev->sdma.trap_irq, (i == 0) ? AMDGPU_SDMA_IRQ_TRAP0 : AMDGPU_SDMA_IRQ_TRAP1);
     if (r) return r;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,43 +1,43 @@
 static int dce_v10_0_sw_init(void *handle) {
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
-    r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
+    r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
     if (r) return r;
   }
   for (i = 8; i < 20; i += 2) {
-    r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
+    r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
     if (r) return r;
   }
   /* HPD hotplug */
-  r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
   if (r) return r;
   adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
   adev->ddev->mode_config.async_page_flip = true;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   adev->ddev->mode_config.preferred_depth = 24;
   adev->ddev->mode_config.prefer_shadow = 1;
   adev->ddev->mode_config.fb_base = adev->mc.aper_base;
   r = amdgpu_modeset_create_props(adev);
   if (r) return r;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   /* allocate crtcs */
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
     r = dce_v10_0_crtc_init(adev, i);
     if (r) return r;
   }
   if (amdgpu_atombios_get_connector_info_from_object_table(adev))
     amdgpu_print_display_setup(adev->ddev);
   else
     return -EINVAL;
   /* setup afmt */
   r = dce_v10_0_afmt_init(adev);
   if (r) return r;
   r = dce_v10_0_audio_init(adev);
   if (r) return r;
   drm_kms_helper_poll_init(adev->ddev);
   adev->mode_info.mode_config_initialized = true;
   return 0;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,43 +1,43 @@
 static int dce_v11_0_sw_init(void *handle) {
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
-    r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
+    r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
     if (r) return r;
   }
   for (i = 8; i < 20; i += 2) {
-    r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
+    r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
     if (r) return r;
   }
   /* HPD hotplug */
-  r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
   if (r) return r;
   adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
   adev->ddev->mode_config.async_page_flip = true;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   adev->ddev->mode_config.preferred_depth = 24;
   adev->ddev->mode_config.prefer_shadow = 1;
   adev->ddev->mode_config.fb_base = adev->mc.aper_base;
   r = amdgpu_modeset_create_props(adev);
   if (r) return r;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   /* allocate crtcs */
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
     r = dce_v11_0_crtc_init(adev, i);
     if (r) return r;
   }
   if (amdgpu_atombios_get_connector_info_from_object_table(adev))
     amdgpu_print_display_setup(adev->ddev);
   else
     return -EINVAL;
   /* setup afmt */
   r = dce_v11_0_afmt_init(adev);
   if (r) return r;
   r = dce_v11_0_audio_init(adev);
   if (r) return r;
   drm_kms_helper_poll_init(adev->ddev);
   adev->mode_info.mode_config_initialized = true;
   return 0;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,45 +1,45 @@
 static int dce_v6_0_sw_init(void *handle) {
   int r, i;
   bool ret;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
-    r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
+    r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
     if (r) return r;
   }
   for (i = 8; i < 20; i += 2) {
-    r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
+    r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
     if (r) return r;
   }
   /* HPD hotplug */
-  r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
   if (r) return r;
   adev->mode_info.mode_config_initialized = true;
   adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
   adev->ddev->mode_config.async_page_flip = true;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   adev->ddev->mode_config.preferred_depth = 24;
   adev->ddev->mode_config.prefer_shadow = 1;
   adev->ddev->mode_config.fb_base = adev->mc.aper_base;
   r = amdgpu_modeset_create_props(adev);
   if (r) return r;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   /* allocate crtcs */
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
     r = dce_v6_0_crtc_init(adev, i);
     if (r) return r;
   }
   ret = amdgpu_atombios_get_connector_info_from_object_table(adev);
   if (ret)
     amdgpu_print_display_setup(adev->ddev);
   else
     return -EINVAL;
   /* setup afmt */
   r = dce_v6_0_afmt_init(adev);
   if (r) return r;
   r = dce_v6_0_audio_init(adev);
   if (r) return r;
   drm_kms_helper_poll_init(adev->ddev);
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,43 +1,43 @@
 static int dce_v8_0_sw_init(void *handle) {
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
-    r = amdgpu_irq_add_id(adev, i + 1, &adev->crtc_irq);
+    r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 1, &adev->crtc_irq);
     if (r) return r;
   }
   for (i = 8; i < 20; i += 2) {
-    r = amdgpu_irq_add_id(adev, i, &adev->pageflip_irq);
+    r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i, &adev->pageflip_irq);
     if (r) return r;
   }
   /* HPD hotplug */
-  r = amdgpu_irq_add_id(adev, 42, &adev->hpd_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 42, &adev->hpd_irq);
   if (r) return r;
   adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
   adev->ddev->mode_config.async_page_flip = true;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   adev->ddev->mode_config.preferred_depth = 24;
   adev->ddev->mode_config.prefer_shadow = 1;
   adev->ddev->mode_config.fb_base = adev->mc.aper_base;
   r = amdgpu_modeset_create_props(adev);
   if (r) return r;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   /* allocate crtcs */
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
     r = dce_v8_0_crtc_init(adev, i);
     if (r) return r;
   }
   if (amdgpu_atombios_get_connector_info_from_object_table(adev))
     amdgpu_print_display_setup(adev->ddev);
   else
     return -EINVAL;
   /* setup afmt */
   r = dce_v8_0_afmt_init(adev);
   if (r) return r;
   r = dce_v8_0_audio_init(adev);
   if (r) return r;
   drm_kms_helper_poll_init(adev->ddev);
   adev->mode_info.mode_config_initialized = true;
   return 0;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,27 +1,27 @@
 static int dce_virtual_sw_init(void *handle) {
   int r, i;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-  r = amdgpu_irq_add_id(adev, 229, &adev->crtc_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 229, &adev->crtc_irq);
   if (r) return r;
   adev->ddev->max_vblank_count = 0;
   adev->ddev->mode_config.funcs = &amdgpu_mode_funcs;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   adev->ddev->mode_config.preferred_depth = 24;
   adev->ddev->mode_config.prefer_shadow = 1;
   adev->ddev->mode_config.fb_base = adev->mc.aper_base;
   r = amdgpu_modeset_create_props(adev);
   if (r) return r;
   adev->ddev->mode_config.max_width = 16384;
   adev->ddev->mode_config.max_height = 16384;
   /* allocate crtcs, encoders, connectors */
   for (i = 0; i < adev->mode_info.num_crtc; i++) {
     r = dce_virtual_crtc_init(adev, i);
     if (r) return r;
     r = dce_virtual_connector_encoder_init(adev, i);
     if (r) return r;
   }
   drm_kms_helper_poll_init(adev->ddev);
   adev->mode_info.mode_config_initialized = true;
   return 0;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,48 +1,48 @@
 static int gfx_v6_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   int i, r;
-  r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
   if (r) return r;
-  r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
   if (r) return r;
-  r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
   if (r) return r;
   gfx_v6_0_scratch_init(adev);
   r = gfx_v6_0_init_microcode(adev);
   if (r) {
     DRM_ERROR("Failed to load gfx firmware!\n");
     return r;
   }
   r = gfx_v6_0_rlc_init(adev);
   if (r) {
     DRM_ERROR("Failed to init rlc BOs!\n");
     return r;
   }
   for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
     ring = &adev->gfx.gfx_ring[i];
     ring->ring_obj = NULL;
     sprintf(ring->name, "gfx");
     r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
     if (r) return r;
   }
   for (i = 0; i < adev->gfx.num_compute_rings; i++) {
     unsigned irq_type;
     if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
       DRM_ERROR("Too many (%d) compute rings!\n", i);
       break;
     }
     ring = &adev->gfx.compute_ring[i];
     ring->ring_obj = NULL;
     ring->use_doorbell = false;
     ring->doorbell_index = 0;
     ring->me = 1;
     ring->pipe = i;
     ring->queue = i;
     sprintf(ring->name, "comp %d.%d.%d", ring->me, ring->pipe, ring->queue);
     irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
     r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type);
     if (r) return r;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,69 +1,69 @@
 static int gfx_v7_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   int i, r;
   /* EOP Event */
-  r = amdgpu_irq_add_id(adev, 181, &adev->gfx.eop_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
   if (r) return r;
   /* Privileged reg */
-  r = amdgpu_irq_add_id(adev, 184, &adev->gfx.priv_reg_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
   if (r) return r;
   /* Privileged inst */
-  r = amdgpu_irq_add_id(adev, 185, &adev->gfx.priv_inst_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
   if (r) return r;
   gfx_v7_0_scratch_init(adev);
   r = gfx_v7_0_init_microcode(adev);
   if (r) {
     DRM_ERROR("Failed to load gfx firmware!\n");
     return r;
   }
   r = gfx_v7_0_rlc_init(adev);
   if (r) {
     DRM_ERROR("Failed to init rlc BOs!\n");
     return r;
   }
   /* allocate mec buffers */
   r = gfx_v7_0_mec_init(adev);
   if (r) {
     DRM_ERROR("Failed to init MEC BOs!\n");
     return r;
   }
   for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
     ring = &adev->gfx.gfx_ring[i];
     ring->ring_obj = NULL;
     sprintf(ring->name, "gfx");
     r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
     if (r) return r;
   }
   /* set up the compute queues */
   for (i = 0; i < adev->gfx.num_compute_rings; i++) {
     unsigned irq_type;
     /* max 32 queues per MEC */
     if ((i >= 32) || (i >= AMDGPU_MAX_COMPUTE_RINGS)) {
       DRM_ERROR("Too many (%d) compute rings!\n", i);
       break;
     }
     ring = &adev->gfx.compute_ring[i];
     ring->ring_obj = NULL;
     ring->use_doorbell = true;
     ring->doorbell_index = AMDGPU_DOORBELL_MEC_RING0 + i;
     ring->me = 1; /* first MEC */
     ring->pipe = i / 8;
     ring->queue = i % 8;
     sprintf(ring->name, "comp_%d.%d.%d", ring->me, ring->pipe, ring->queue);
     irq_type = AMDGPU_CP_IRQ_COMPUTE_MEC1_PIPE0_EOP + ring->pipe;
     /* type-2 packets are deprecated on MEC, use type-3 instead */
     r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, irq_type);
     if (r) return r;
   }
   /* reserve GDS, GWS and OA resource for gfx */
   r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, &adev->gds.gds_gfx_bo, NULL, NULL);
   if (r) return r;
   r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS, &adev->gds.gws_gfx_bo, NULL, NULL);
   if (r) return r;
   r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA, &adev->gds.oa_gfx_bo, NULL, NULL);
   if (r) return r;
   adev->gfx.ce_ram_size = 0x8000;
   gfx_v7_0_gpu_early_init(adev);
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,44 +1,44 @@
 static int gmc_v6_0_sw_init(void *handle) {
   int r;
   int dma_bits;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
-  r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
   if (r) return r;
-  r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
   if (r) return r;
   adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
   adev->mc.mc_mask = 0xffffffffffULL;
   adev->need_dma32 = false;
   dma_bits = adev->need_dma32 ? 32 : 40;
   r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
   if (r) {
     adev->need_dma32 = true;
     dma_bits = 32;
     dev_warn(adev->dev, "amdgpu: No suitable DMA available.\n");
   }
   r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
   if (r) {
     pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
     dev_warn(adev->dev, "amdgpu: No coherent DMA available.\n");
   }
   r = gmc_v6_0_init_microcode(adev);
   if (r) {
     dev_err(adev->dev, "Failed to load mc firmware!\n");
     return r;
   }
   r = gmc_v6_0_mc_init(adev);
   if (r) return r;
   r = amdgpu_bo_init(adev);
   if (r) return r;
   r = gmc_v6_0_gart_init(adev);
   if (r) return r;
   if (!adev->vm_manager.enabled) {
     r = gmc_v6_0_vm_init(adev);
     if (r) {
       dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
       return r;
     }
     adev->vm_manager.enabled = true;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)
--- initial
+++ final
@@ -1,65 +1,65 @@
 static int gmc_v7_0_sw_init(void *handle) {
   int r;
   int dma_bits;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   if (adev->flags & AMD_IS_APU) {
     adev->mc.vram_type = AMDGPU_VRAM_TYPE_UNKNOWN;
   } else {
     u32 tmp = RREG32(mmMC_SEQ_MISC0);
     tmp &= MC_SEQ_MISC0__MT__MASK;
     adev->mc.vram_type = gmc_v7_0_convert_vram_type(tmp);
   }
-  r = amdgpu_irq_add_id(adev, 146, &adev->mc.vm_fault);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 146, &adev->mc.vm_fault);
   if (r) return r;
-  r = amdgpu_irq_add_id(adev, 147, &adev->mc.vm_fault);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 147, &adev->mc.vm_fault);
   if (r) return r;
   /* Adjust VM size here.
    * Currently set to 4GB ((1 << 20) 4k pages).
    * Max GPUVM size for cayman and SI is 40 bits.
    */
   adev->vm_manager.max_pfn = amdgpu_vm_size << 18;
   /* Set the internal MC address mask
    * This is the max address of the GPU's
    * internal address space.
    */
   adev->mc.mc_mask = 0xffffffffffULL; /* 40 bit MC */
   /* set DMA mask + need_dma32 flags.
    * PCIE - can handle 40-bits.
    * IGP - can handle 40-bits
    * PCI - dma32 for legacy pci gart, 40 bits on newer asics
    */
   adev->need_dma32 = false;
   dma_bits = adev->need_dma32 ? 32 : 40;
   r = pci_set_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
   if (r) {
     adev->need_dma32 = true;
     dma_bits = 32;
     pr_warn("amdgpu: No suitable DMA available\n");
   }
   r = pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(dma_bits));
   if (r) {
     pci_set_consistent_dma_mask(adev->pdev, DMA_BIT_MASK(32));
     pr_warn("amdgpu: No coherent DMA available\n");
   }
   r = gmc_v7_0_init_microcode(adev);
   if (r) {
     DRM_ERROR("Failed to load mc firmware!\n");
     return r;
   }
   r = gmc_v7_0_mc_init(adev);
   if (r) return r;
   /* Memory manager */
   r = amdgpu_bo_init(adev);
   if (r) return r;
   r = gmc_v7_0_gart_init(adev);
   if (r) return r;
   if (!adev->vm_manager.enabled) {
     r = gmc_v7_0_vm_init(adev);
     if (r) {
       dev_err(adev->dev, "vm manager initialization failed (%d).\n", r);
       return r;
     }
     adev->vm_manager.enabled = true;
   }
   return r;
 }<sep>@@
expression e1,e2,e3;
@@
 
-       amdgpu_irq_add_id(e1, e2, e3)
+       amdgpu_irq_add_id(e1, AMDGPU_IH_CLIENTID_LEGACY, e2, e3)