--- initial
+++ final
@@ -1,92 +1,92 @@
 int amdgpu_ib_schedule(struct amdgpu_ring *ring, unsigned num_ibs, struct amdgpu_ib *ibs, struct amdgpu_job *job, struct dma_fence **f) {
   struct amdgpu_device *adev = ring->adev;
   struct amdgpu_ib *ib = &ibs[0];
   struct dma_fence *tmp = NULL;
   bool skip_preamble, need_ctx_switch;
   unsigned patch_offset = ~0;
   struct amdgpu_vm *vm;
   uint64_t fence_ctx;
   uint32_t status = 0, alloc_size;
   unsigned i;
   int r = 0;
   bool need_pipe_sync = false;
   if (num_ibs == 0) return -EINVAL;
   /* ring tests don't use a job */
   if (job) {
     vm = job->vm;
     fence_ctx = job->fence_ctx;
   } else {
     vm = NULL;
     fence_ctx = 0;
   }
   if (!ring->ready) {
     dev_err(adev->dev, "couldn't schedule ib on ring <%s>\n", ring->name);
     return -EINVAL;
   }
-  if (vm && !job->vm_id) {
+  if (vm && !job->vmid) {
     dev_err(adev->dev, "VM IB without ID\n");
     return -EINVAL;
   }
   alloc_size = ring->funcs->emit_frame_size + num_ibs * ring->funcs->emit_ib_size;
   r = amdgpu_ring_alloc(ring, alloc_size);
   if (r) {
     dev_err(adev->dev, "scheduling IB failed (%d).\n", r);
     return r;
   }
   if (ring->funcs->emit_pipeline_sync && job && ((tmp = amdgpu_sync_get_fence(&job->sched_sync, NULL)) || amdgpu_vm_need_pipeline_sync(ring, job))) {
     need_pipe_sync = true;
     dma_fence_put(tmp);
   }
   if (ring->funcs->insert_start) ring->funcs->insert_start(ring);
   if (job) {
     r = amdgpu_vm_flush(ring, job, need_pipe_sync);
     if (r) {
       amdgpu_ring_undo(ring);
       return r;
     }
   }
   if (ring->funcs->init_cond_exec) patch_offset = amdgpu_ring_init_cond_exec(ring);
   if (ring->funcs->emit_hdp_flush
 #ifdef CONFIG_X86_64
       && !(adev->flags & AMD_IS_APU)
 #endif
   )
     amdgpu_ring_emit_hdp_flush(ring);
   skip_preamble = ring->current_ctx == fence_ctx;
   need_ctx_switch = ring->current_ctx != fence_ctx;
   if (job && ring->funcs->emit_cntxcntl) {
     if (need_ctx_switch) status |= AMDGPU_HAVE_CTX_SWITCH;
     status |= job->preamble_status;
     amdgpu_ring_emit_cntxcntl(ring, status);
   }
   for (i = 0; i < num_ibs; ++i) {
     ib = &ibs[i];
     /* drop preamble IBs if we don't have a context switch */
     if ((ib->flags & AMDGPU_IB_FLAG_PREAMBLE) && skip_preamble && !(status & AMDGPU_PREAMBLE_IB_PRESENT_FIRST) && !amdgpu_sriov_vf(adev)) /* for SRIOV preemption, Preamble CE ib must be inserted anyway */
       continue;
-    amdgpu_ring_emit_ib(ring, ib, job ? job->vm_id : 0, need_ctx_switch);
+    amdgpu_ring_emit_ib(ring, ib, job ? job->vmid : 0, need_ctx_switch);
     need_ctx_switch = false;
   }
   if (ring->funcs->emit_tmz) amdgpu_ring_emit_tmz(ring, false);
   if (ring->funcs->emit_hdp_invalidate
 #ifdef CONFIG_X86_64
       && !(adev->flags & AMD_IS_APU)
 #endif
   )
     amdgpu_ring_emit_hdp_invalidate(ring);
   r = amdgpu_fence_emit(ring, f);
   if (r) {
     dev_err(adev->dev, "failed to emit fence (%d)\n", r);
-    if (job && job->vm_id) amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vm_id);
+    if (job && job->vmid) amdgpu_vmid_reset(adev, ring->funcs->vmhub, job->vmid);
     amdgpu_ring_undo(ring);
     return r;
   }
   if (ring->funcs->insert_end) ring->funcs->insert_end(ring);
   /* wrap the last IB with fence */
   if (job && job->uf_addr) { amdgpu_ring_emit_fence(ring, job->uf_addr, job->uf_sequence, AMDGPU_FENCE_FLAG_64BIT); }
   if (patch_offset != ~0 && ring->funcs->patch_cond_exec) amdgpu_ring_patch_cond_exec(ring, patch_offset);
   ring->current_ctx = fence_ctx;
   if (vm && ring->funcs->emit_switch_buffer) amdgpu_ring_emit_switch_buffer(ring);
   amdgpu_ring_commit(ring);
   return 0;
 }<sep>@@
struct amdgpu_job x;
@@

 x.
-   vm_id
+   vmid