imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,21 +1,21 @@
 static void vi_init_golden_registers(struct amdgpu_device *adev) {
   /* Some of the registers might be dependent on GRBM_GFX_INDEX */
   mutex_lock(&adev->grbm_idx_mutex);
   if (amdgpu_sriov_vf(adev)) {
     xgpu_vi_init_golden_registers(adev);
     mutex_unlock(&adev->grbm_idx_mutex);
     return;
   }
   switch (adev->asic_type) {
-  case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, ARRAY_SIZE(iceland_mgcg_cgcg_init)); break;
-  case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, ARRAY_SIZE(fiji_mgcg_cgcg_init)); break;
-  case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, ARRAY_SIZE(tonga_mgcg_cgcg_init)); break;
-  case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, ARRAY_SIZE(cz_mgcg_cgcg_init)); break;
-  case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, ARRAY_SIZE(stoney_mgcg_cgcg_init)); break;
+  case CHIP_TOPAZ: amdgpu_device_program_register_sequence(adev, iceland_mgcg_cgcg_init, ARRAY_SIZE(iceland_mgcg_cgcg_init)); break;
+  case CHIP_FIJI: amdgpu_device_program_register_sequence(adev, fiji_mgcg_cgcg_init, ARRAY_SIZE(fiji_mgcg_cgcg_init)); break;
+  case CHIP_TONGA: amdgpu_device_program_register_sequence(adev, tonga_mgcg_cgcg_init, ARRAY_SIZE(tonga_mgcg_cgcg_init)); break;
+  case CHIP_CARRIZO: amdgpu_device_program_register_sequence(adev, cz_mgcg_cgcg_init, ARRAY_SIZE(cz_mgcg_cgcg_init)); break;
+  case CHIP_STONEY: amdgpu_device_program_register_sequence(adev, stoney_mgcg_cgcg_init, ARRAY_SIZE(stoney_mgcg_cgcg_init)); break;
   case CHIP_POLARIS11:
   case CHIP_POLARIS10:
   case CHIP_POLARIS12:
   default: break;
   }
   mutex_unlock(&adev->grbm_idx_mutex);
 }<sep>@@
expression e1,e2,e3;
@@
- amdgpu_program_register_sequence
+ amdgpu_device_program_register_sequence
  (e1,e2,e3)
--- initial
+++ final
@@ -1,13 +1,13 @@
 static void dce_v10_0_init_golden_registers(struct amdgpu_device *adev) {
   switch (adev->asic_type) {
   case CHIP_FIJI:
-    amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+    amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, ARRAY_SIZE(fiji_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, ARRAY_SIZE(golden_settings_fiji_a10));
     break;
   case CHIP_TONGA:
-    amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+    amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, ARRAY_SIZE(tonga_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, ARRAY_SIZE(golden_settings_tonga_a11));
     break;
   default: break;
   }
 }<sep>@@
expression e1,e2,e3;
type T;
@@
                amdgpu_program_register_sequence(e1,e2,
-                                                (const T)ARRAY_SIZE(e3));
+                                                ARRAY_SIZE(e3));
--- initial
+++ final
@@ -1,13 +1,13 @@
 static void dce_v11_0_init_golden_registers(struct amdgpu_device *adev) {
   switch (adev->asic_type) {
   case CHIP_CARRIZO:
-    amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, cz_golden_settings_a11, (const u32)ARRAY_SIZE(cz_golden_settings_a11));
+    amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, ARRAY_SIZE(cz_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, cz_golden_settings_a11, ARRAY_SIZE(cz_golden_settings_a11));
     break;
-  case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, (const u32)ARRAY_SIZE(stoney_golden_settings_a11)); break;
+  case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, ARRAY_SIZE(stoney_golden_settings_a11)); break;
   case CHIP_POLARIS11:
-  case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, polaris11_golden_settings_a11, (const u32)ARRAY_SIZE(polaris11_golden_settings_a11)); break;
-  case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, polaris10_golden_settings_a11, (const u32)ARRAY_SIZE(polaris10_golden_settings_a11)); break;
+  case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, polaris11_golden_settings_a11, ARRAY_SIZE(polaris11_golden_settings_a11)); break;
+  case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, polaris10_golden_settings_a11, ARRAY_SIZE(polaris10_golden_settings_a11)); break;
   default: break;
   }
 }<sep>@@
expression e1,e2,e3;
type T;
@@
                amdgpu_program_register_sequence(e1,e2,
-                                                (const T)ARRAY_SIZE(e3));
+                                                ARRAY_SIZE(e3));
--- initial
+++ final
@@ -1,14 +1,14 @@
 static void gfx_v9_0_init_golden_registers(struct amdgpu_device *adev) {
   switch (adev->asic_type) {
   case CHIP_VEGA10:
-    amdgpu_program_register_sequence(adev, golden_settings_gc_9_0, (const u32)ARRAY_SIZE(golden_settings_gc_9_0));
-    amdgpu_program_register_sequence(adev, golden_settings_gc_9_0_vg10, (const u32)ARRAY_SIZE(golden_settings_gc_9_0_vg10));
+    amdgpu_program_register_sequence(adev, golden_settings_gc_9_0, ARRAY_SIZE(golden_settings_gc_9_0));
+    amdgpu_program_register_sequence(adev, golden_settings_gc_9_0_vg10, ARRAY_SIZE(golden_settings_gc_9_0_vg10));
     break;
   case CHIP_RAVEN:
-    amdgpu_program_register_sequence(adev, golden_settings_gc_9_1, (const u32)ARRAY_SIZE(golden_settings_gc_9_1));
-    amdgpu_program_register_sequence(adev, golden_settings_gc_9_1_rv1, (const u32)ARRAY_SIZE(golden_settings_gc_9_1_rv1));
+    amdgpu_program_register_sequence(adev, golden_settings_gc_9_1, ARRAY_SIZE(golden_settings_gc_9_1));
+    amdgpu_program_register_sequence(adev, golden_settings_gc_9_1_rv1, ARRAY_SIZE(golden_settings_gc_9_1_rv1));
     break;
   default: break;
   }
-  amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common, (const u32)ARRAY_SIZE(golden_settings_gc_9_x_common));
+  amdgpu_program_register_sequence(adev, golden_settings_gc_9_x_common, ARRAY_SIZE(golden_settings_gc_9_x_common));
 }<sep>@@
expression e1,e2,e3;
type T;
@@
                amdgpu_program_register_sequence(e1,e2,
-                                                (const T)ARRAY_SIZE(e3));
+                                                ARRAY_SIZE(e3));
--- initial
+++ final
@@ -1,9 +1,9 @@
 static void gmc_v7_0_init_golden_registers(struct amdgpu_device *adev) {
   switch (adev->asic_type) {
   case CHIP_TOPAZ:
-    amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, golden_settings_iceland_a11, (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
+    amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, ARRAY_SIZE(iceland_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, golden_settings_iceland_a11, ARRAY_SIZE(golden_settings_iceland_a11));
     break;
   default: break;
   }
 }<sep>@@
expression e1,e2,e3;
type T;
@@
                amdgpu_program_register_sequence(e1,e2,
-                                                (const T)ARRAY_SIZE(e3));
+                                                ARRAY_SIZE(e3));
--- initial
+++ final
@@ -1,21 +1,21 @@
 static void gmc_v8_0_init_golden_registers(struct amdgpu_device *adev) {
   switch (adev->asic_type) {
   case CHIP_FIJI:
-    amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+    amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, ARRAY_SIZE(fiji_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, ARRAY_SIZE(golden_settings_fiji_a10));
     break;
   case CHIP_TONGA:
-    amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+    amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, ARRAY_SIZE(tonga_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, ARRAY_SIZE(golden_settings_tonga_a11));
     break;
   case CHIP_POLARIS11:
-  case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, golden_settings_polaris11_a11, (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); break;
-  case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, golden_settings_polaris10_a11, (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); break;
-  case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); break;
+  case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, golden_settings_polaris11_a11, ARRAY_SIZE(golden_settings_polaris11_a11)); break;
+  case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, golden_settings_polaris10_a11, ARRAY_SIZE(golden_settings_polaris10_a11)); break;
+  case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, ARRAY_SIZE(cz_mgcg_cgcg_init)); break;
   case CHIP_STONEY:
-    amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, golden_settings_stoney_common, (const u32)ARRAY_SIZE(golden_settings_stoney_common));
+    amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, ARRAY_SIZE(stoney_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, golden_settings_stoney_common, ARRAY_SIZE(golden_settings_stoney_common));
     break;
   default: break;
   }
 }<sep>@@
expression e1,e2,e3;
type T;
@@
                amdgpu_program_register_sequence(e1,e2,
-                                                (const T)ARRAY_SIZE(e3));
+                                                ARRAY_SIZE(e3));
--- initial
+++ final
@@ -1,41 +1,41 @@
 static int gmc_v9_0_gart_enable(struct amdgpu_device *adev) {
   int r;
   bool value;
   u32 tmp;
-  amdgpu_program_register_sequence(adev, golden_settings_vega10_hdp, (const u32)ARRAY_SIZE(golden_settings_vega10_hdp));
+  amdgpu_program_register_sequence(adev, golden_settings_vega10_hdp, ARRAY_SIZE(golden_settings_vega10_hdp));
   if (adev->gart.robj == NULL) {
     dev_err(adev->dev, "No VRAM object for PCIE GART.\n");
     return -EINVAL;
   }
   r = amdgpu_gart_table_vram_pin(adev);
   if (r) return r;
   switch (adev->asic_type) {
   case CHIP_RAVEN:
     mmhub_v1_0_initialize_power_gating(adev);
     mmhub_v1_0_update_power_gating(adev, true);
     break;
   default: break;
   }
   r = gfxhub_v1_0_gart_enable(adev);
   if (r) return r;
   r = mmhub_v1_0_gart_enable(adev);
   if (r) return r;
   WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1);
   tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL);
   WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp);
   /* After HDP is initialized, flush HDP.*/
   if (adev->flags & AMD_IS_APU)
     nbio_v7_0_hdp_flush(adev);
   else
     nbio_v6_1_hdp_flush(adev);
   if (amdgpu_vm_fault_stop == AMDGPU_VM_FAULT_STOP_ALWAYS)
     value = false;
   else
     value = true;
   gfxhub_v1_0_set_fault_enable_default(adev, value);
   mmhub_v1_0_set_fault_enable_default(adev, value);
   gmc_v9_0_gart_flush_gpu_tlb(adev, 0);
   DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", (unsigned)(adev->mc.gart_size >> 20), (unsigned long long)adev->gart.table_addr);
   adev->gart.ready = true;
   return 0;
 }<sep>@@
expression e1,e2,e3;
type T;
@@
                amdgpu_program_register_sequence(e1,e2,
-                                                (const T)ARRAY_SIZE(e3));
+                                                ARRAY_SIZE(e3));
--- initial
+++ final
@@ -1,10 +1,10 @@
 static void gmc_v9_0_init_golden_registers(struct amdgpu_device *adev) {
   switch (adev->asic_type) {
   case CHIP_VEGA10:
-    amdgpu_program_register_sequence(adev, golden_settings_mmhub_1_0_0, (const u32)ARRAY_SIZE(golden_settings_mmhub_1_0_0));
-    amdgpu_program_register_sequence(adev, golden_settings_athub_1_0_0, (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0));
+    amdgpu_program_register_sequence(adev, golden_settings_mmhub_1_0_0, ARRAY_SIZE(golden_settings_mmhub_1_0_0));
+    amdgpu_program_register_sequence(adev, golden_settings_athub_1_0_0, ARRAY_SIZE(golden_settings_athub_1_0_0));
     break;
-  case CHIP_RAVEN: amdgpu_program_register_sequence(adev, golden_settings_athub_1_0_0, (const u32)ARRAY_SIZE(golden_settings_athub_1_0_0)); break;
+  case CHIP_RAVEN: amdgpu_program_register_sequence(adev, golden_settings_athub_1_0_0, ARRAY_SIZE(golden_settings_athub_1_0_0)); break;
   default: break;
   }
 }<sep>@@
expression e1,e2,e3;
type T;
@@
                amdgpu_program_register_sequence(e1,e2,
-                                                (const T)ARRAY_SIZE(e3));
+                                                ARRAY_SIZE(e3));
--- initial
+++ final
@@ -1,15 +1,15 @@
 void xgpu_vi_init_golden_registers(struct amdgpu_device *adev) {
   switch (adev->asic_type) {
   case CHIP_FIJI:
-    amdgpu_program_register_sequence(adev, xgpu_fiji_mgcg_cgcg_init, (const u32)ARRAY_SIZE(xgpu_fiji_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, xgpu_fiji_golden_settings_a10, (const u32)ARRAY_SIZE(xgpu_fiji_golden_settings_a10));
-    amdgpu_program_register_sequence(adev, xgpu_fiji_golden_common_all, (const u32)ARRAY_SIZE(xgpu_fiji_golden_common_all));
+    amdgpu_program_register_sequence(adev, xgpu_fiji_mgcg_cgcg_init, ARRAY_SIZE(xgpu_fiji_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, xgpu_fiji_golden_settings_a10, ARRAY_SIZE(xgpu_fiji_golden_settings_a10));
+    amdgpu_program_register_sequence(adev, xgpu_fiji_golden_common_all, ARRAY_SIZE(xgpu_fiji_golden_common_all));
     break;
   case CHIP_TONGA:
-    amdgpu_program_register_sequence(adev, xgpu_tonga_mgcg_cgcg_init, (const u32)ARRAY_SIZE(xgpu_tonga_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, xgpu_tonga_golden_settings_a11, (const u32)ARRAY_SIZE(xgpu_tonga_golden_settings_a11));
-    amdgpu_program_register_sequence(adev, xgpu_tonga_golden_common_all, (const u32)ARRAY_SIZE(xgpu_tonga_golden_common_all));
+    amdgpu_program_register_sequence(adev, xgpu_tonga_mgcg_cgcg_init, ARRAY_SIZE(xgpu_tonga_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, xgpu_tonga_golden_settings_a11, ARRAY_SIZE(xgpu_tonga_golden_settings_a11));
+    amdgpu_program_register_sequence(adev, xgpu_tonga_golden_common_all, ARRAY_SIZE(xgpu_tonga_golden_common_all));
     break;
   default: BUG_ON("Doesn't support chip type.\n"); break;
   }
 }<sep>@@
expression e1,e2,e3;
type T;
@@
                amdgpu_program_register_sequence(e1,e2,
-                                                (const T)ARRAY_SIZE(e3));
+                                                ARRAY_SIZE(e3));
--- initial
+++ final
@@ -1,9 +1,9 @@
 static void sdma_v2_4_init_golden_registers(struct amdgpu_device *adev) {
   switch (adev->asic_type) {
   case CHIP_TOPAZ:
-    amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, golden_settings_iceland_a11, (const u32)ARRAY_SIZE(golden_settings_iceland_a11));
+    amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, ARRAY_SIZE(iceland_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, golden_settings_iceland_a11, ARRAY_SIZE(golden_settings_iceland_a11));
     break;
   default: break;
   }
 }<sep>@@
expression e1,e2,e3;
type T;
@@
                amdgpu_program_register_sequence(e1,e2,
-                                                (const T)ARRAY_SIZE(e3));
+                                                ARRAY_SIZE(e3));
--- initial
+++ final
@@ -1,24 +1,24 @@
 static void sdma_v3_0_init_golden_registers(struct amdgpu_device *adev) {
   switch (adev->asic_type) {
   case CHIP_FIJI:
-    amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, (const u32)ARRAY_SIZE(golden_settings_fiji_a10));
+    amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, ARRAY_SIZE(fiji_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, golden_settings_fiji_a10, ARRAY_SIZE(golden_settings_fiji_a10));
     break;
   case CHIP_TONGA:
-    amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, (const u32)ARRAY_SIZE(golden_settings_tonga_a11));
+    amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, ARRAY_SIZE(tonga_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, golden_settings_tonga_a11, ARRAY_SIZE(golden_settings_tonga_a11));
     break;
   case CHIP_POLARIS11:
-  case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, golden_settings_polaris11_a11, (const u32)ARRAY_SIZE(golden_settings_polaris11_a11)); break;
-  case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, golden_settings_polaris10_a11, (const u32)ARRAY_SIZE(golden_settings_polaris10_a11)); break;
+  case CHIP_POLARIS12: amdgpu_program_register_sequence(adev, golden_settings_polaris11_a11, ARRAY_SIZE(golden_settings_polaris11_a11)); break;
+  case CHIP_POLARIS10: amdgpu_program_register_sequence(adev, golden_settings_polaris10_a11, ARRAY_SIZE(golden_settings_polaris10_a11)); break;
   case CHIP_CARRIZO:
-    amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, cz_golden_settings_a11, (const u32)ARRAY_SIZE(cz_golden_settings_a11));
+    amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, ARRAY_SIZE(cz_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, cz_golden_settings_a11, ARRAY_SIZE(cz_golden_settings_a11));
     break;
   case CHIP_STONEY:
-    amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init));
-    amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, (const u32)ARRAY_SIZE(stoney_golden_settings_a11));
+    amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, ARRAY_SIZE(stoney_mgcg_cgcg_init));
+    amdgpu_program_register_sequence(adev, stoney_golden_settings_a11, ARRAY_SIZE(stoney_golden_settings_a11));
     break;
   default: break;
   }
 }<sep>@@
expression e1,e2,e3;
type T;
@@
                amdgpu_program_register_sequence(e1,e2,
-                                                (const T)ARRAY_SIZE(e3));
+                                                ARRAY_SIZE(e3));
--- initial
+++ final
@@ -1,13 +1,13 @@
 static void sdma_v4_0_init_golden_registers(struct amdgpu_device *adev) {
   switch (adev->asic_type) {
   case CHIP_VEGA10:
-    amdgpu_program_register_sequence(adev, golden_settings_sdma_4, (const u32)ARRAY_SIZE(golden_settings_sdma_4));
-    amdgpu_program_register_sequence(adev, golden_settings_sdma_vg10, (const u32)ARRAY_SIZE(golden_settings_sdma_vg10));
+    amdgpu_program_register_sequence(adev, golden_settings_sdma_4, ARRAY_SIZE(golden_settings_sdma_4));
+    amdgpu_program_register_sequence(adev, golden_settings_sdma_vg10, ARRAY_SIZE(golden_settings_sdma_vg10));
     break;
   case CHIP_RAVEN:
-    amdgpu_program_register_sequence(adev, golden_settings_sdma_4_1, (const u32)ARRAY_SIZE(golden_settings_sdma_4_1));
-    amdgpu_program_register_sequence(adev, golden_settings_sdma_rv1, (const u32)ARRAY_SIZE(golden_settings_sdma_rv1));
+    amdgpu_program_register_sequence(adev, golden_settings_sdma_4_1, ARRAY_SIZE(golden_settings_sdma_4_1));
+    amdgpu_program_register_sequence(adev, golden_settings_sdma_rv1, ARRAY_SIZE(golden_settings_sdma_rv1));
     break;
   default: break;
   }
 }<sep>@@
expression e1,e2,e3;
type T;
@@
                amdgpu_program_register_sequence(e1,e2,
-                                                (const T)ARRAY_SIZE(e3));
+                                                ARRAY_SIZE(e3));
--- initial
+++ final
@@ -1,10 +1,10 @@
 static void soc15_init_golden_registers(struct amdgpu_device *adev) {
   /* Some of the registers might be dependent on GRBM_GFX_INDEX */
   mutex_lock(&adev->grbm_idx_mutex);
   switch (adev->asic_type) {
-  case CHIP_VEGA10: amdgpu_program_register_sequence(adev, vega10_golden_init, (const u32)ARRAY_SIZE(vega10_golden_init)); break;
-  case CHIP_RAVEN: amdgpu_program_register_sequence(adev, raven_golden_init, (const u32)ARRAY_SIZE(raven_golden_init)); break;
+  case CHIP_VEGA10: amdgpu_program_register_sequence(adev, vega10_golden_init, ARRAY_SIZE(vega10_golden_init)); break;
+  case CHIP_RAVEN: amdgpu_program_register_sequence(adev, raven_golden_init, ARRAY_SIZE(raven_golden_init)); break;
   default: break;
   }
   mutex_unlock(&adev->grbm_idx_mutex);
 }<sep>@@
expression e1,e2,e3;
type T;
@@
                amdgpu_program_register_sequence(e1,e2,
-                                                (const T)ARRAY_SIZE(e3));
+                                                ARRAY_SIZE(e3));
--- initial
+++ final
@@ -1,21 +1,21 @@
 static void vi_init_golden_registers(struct amdgpu_device *adev) {
   /* Some of the registers might be dependent on GRBM_GFX_INDEX */
   mutex_lock(&adev->grbm_idx_mutex);
   if (amdgpu_sriov_vf(adev)) {
     xgpu_vi_init_golden_registers(adev);
     mutex_unlock(&adev->grbm_idx_mutex);
     return;
   }
   switch (adev->asic_type) {
-  case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, (const u32)ARRAY_SIZE(iceland_mgcg_cgcg_init)); break;
-  case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, (const u32)ARRAY_SIZE(fiji_mgcg_cgcg_init)); break;
-  case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, (const u32)ARRAY_SIZE(tonga_mgcg_cgcg_init)); break;
-  case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, (const u32)ARRAY_SIZE(cz_mgcg_cgcg_init)); break;
-  case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, (const u32)ARRAY_SIZE(stoney_mgcg_cgcg_init)); break;
+  case CHIP_TOPAZ: amdgpu_program_register_sequence(adev, iceland_mgcg_cgcg_init, ARRAY_SIZE(iceland_mgcg_cgcg_init)); break;
+  case CHIP_FIJI: amdgpu_program_register_sequence(adev, fiji_mgcg_cgcg_init, ARRAY_SIZE(fiji_mgcg_cgcg_init)); break;
+  case CHIP_TONGA: amdgpu_program_register_sequence(adev, tonga_mgcg_cgcg_init, ARRAY_SIZE(tonga_mgcg_cgcg_init)); break;
+  case CHIP_CARRIZO: amdgpu_program_register_sequence(adev, cz_mgcg_cgcg_init, ARRAY_SIZE(cz_mgcg_cgcg_init)); break;
+  case CHIP_STONEY: amdgpu_program_register_sequence(adev, stoney_mgcg_cgcg_init, ARRAY_SIZE(stoney_mgcg_cgcg_init)); break;
   case CHIP_POLARIS11:
   case CHIP_POLARIS10:
   case CHIP_POLARIS12:
   default: break;
   }
   mutex_unlock(&adev->grbm_idx_mutex);
 }<sep>@@
expression e1,e2,e3;
type T;
@@
                amdgpu_program_register_sequence(e1,e2,
-                                                (const T)ARRAY_SIZE(e3));
+                                                ARRAY_SIZE(e3));