--- initial
+++ final
@@ -1,89 +1,89 @@
 static int imx_ahci_probe(struct platform_device *pdev) {
   struct device *dev = &pdev->dev;
   const struct of_device_id *of_id;
   struct ahci_host_priv *hpriv;
   struct imx_ahci_priv *imxpriv;
   unsigned int reg_val;
   int ret;
   of_id = of_match_device(imx_ahci_of_match, dev);
   if (!of_id) return -EINVAL;
   imxpriv = devm_kzalloc(dev, sizeof(*imxpriv), GFP_KERNEL);
   if (!imxpriv) return -ENOMEM;
   imxpriv->ahci_pdev = pdev;
   imxpriv->no_device = false;
   imxpriv->first_time = true;
   imxpriv->type = (enum ahci_imx_type)of_id->data;
   imxpriv->sata_clk = devm_clk_get(dev, "sata");
   if (IS_ERR(imxpriv->sata_clk)) {
     dev_err(dev, "can't get sata clock.\n");
     return PTR_ERR(imxpriv->sata_clk);
   }
   imxpriv->sata_ref_clk = devm_clk_get(dev, "sata_ref");
   if (IS_ERR(imxpriv->sata_ref_clk)) {
     dev_err(dev, "can't get sata_ref clock.\n");
     return PTR_ERR(imxpriv->sata_ref_clk);
   }
   imxpriv->ahb_clk = devm_clk_get(dev, "ahb");
   if (IS_ERR(imxpriv->ahb_clk)) {
     dev_err(dev, "can't get ahb clock.\n");
     return PTR_ERR(imxpriv->ahb_clk);
   }
   if (imxpriv->type == AHCI_IMX6Q || imxpriv->type == AHCI_IMX6QP) {
     u32 reg_value;
     imxpriv->gpr = syscon_regmap_lookup_by_compatible("fsl,imx6q-iomuxc-gpr");
     if (IS_ERR(imxpriv->gpr)) {
       dev_err(dev, "failed to find fsl,imx6q-iomux-gpr regmap\n");
       return PTR_ERR(imxpriv->gpr);
     }
     reg_value = imx_ahci_parse_props(dev, gpr13_props, ARRAY_SIZE(gpr13_props));
     imxpriv->phy_params = IMX6Q_GPR13_SATA_RX_LOS_LVL_SATA2M | IMX6Q_GPR13_SATA_RX_DPLL_MODE_2P_4F | IMX6Q_GPR13_SATA_SPD_MODE_3P0G | reg_value;
   } else if (imxpriv->type == AHCI_IMX8QM) {
     ret = imx8_sata_probe(dev, imxpriv);
     if (ret) return ret;
   }
-  hpriv = ahci_platform_get_resources(pdev);
+  hpriv = ahci_platform_get_resources(pdev, 0);
   if (IS_ERR(hpriv)) return PTR_ERR(hpriv);
   hpriv->plat_data = imxpriv;
   ret = clk_prepare_enable(imxpriv->sata_clk);
   if (ret) return ret;
   if (imxpriv->type == AHCI_IMX53 && IS_ENABLED(CONFIG_HWMON)) {
     /* Add the temperature monitor */
     struct device *hwmon_dev;
     hwmon_dev = devm_hwmon_device_register_with_groups(dev, "sata_ahci", hpriv, fsl_sata_ahci_groups);
     if (IS_ERR(hwmon_dev)) {
       ret = PTR_ERR(hwmon_dev);
       goto disable_clk;
     }
     devm_thermal_zone_of_sensor_register(hwmon_dev, 0, hwmon_dev, &fsl_sata_ahci_of_thermal_ops);
     dev_info(dev, "%s: sensor 'sata_ahci'\n", dev_name(hwmon_dev));
   }
   ret = imx_sata_enable(hpriv);
   if (ret) goto disable_clk;
   /*
    * Configure the HWINIT bits of the HOST_CAP and HOST_PORTS_IMPL,
    * and IP vendor specific register IMX_TIMER1MS.
    * Configure CAP_SSS (support stagered spin up).
    * Implement the port0.
    * Get the ahb clock rate, and configure the TIMER1MS register.
    */
   reg_val = readl(hpriv->mmio + HOST_CAP);
   if (!(reg_val & HOST_CAP_SSS)) {
     reg_val |= HOST_CAP_SSS;
     writel(reg_val, hpriv->mmio + HOST_CAP);
   }
   reg_val = readl(hpriv->mmio + HOST_PORTS_IMPL);
   if (!(reg_val & 0x1)) {
     reg_val |= 0x1;
     writel(reg_val, hpriv->mmio + HOST_PORTS_IMPL);
   }
   reg_val = clk_get_rate(imxpriv->ahb_clk) / 1000;
   writel(reg_val, hpriv->mmio + IMX_TIMER1MS);
   ret = ahci_platform_init_host(pdev, hpriv, &ahci_imx_port_info, &ahci_platform_sht);
   if (ret) goto disable_sata;
   return 0;
 disable_sata:
   imx_sata_disable(hpriv);
 disable_clk:
   clk_disable_unprepare(imxpriv->sata_clk);
   return ret;
 }<sep>@@
expression pdev;
@@
ahci_platform_get_resources(pdev
+  , 0
   )