--- initial
+++ final
@@ -1,127 +1,127 @@
 static void intel_dsi_prepare(struct intel_encoder *intel_encoder, struct intel_crtc_state *pipe_config) {
   struct drm_encoder *encoder = &intel_encoder->base;
   struct drm_device *dev = encoder->dev;
   struct drm_i915_private *dev_priv = to_i915(dev);
   struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
   struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder);
   const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
   enum port port;
   unsigned int bpp = mipi_dsi_pixel_format_to_bpp(intel_dsi->pixel_format);
   u32 val, tmp;
   u16 mode_hdisplay;
   DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe));
   mode_hdisplay = adjusted_mode->crtc_hdisplay;
   if (intel_dsi->dual_link) {
     mode_hdisplay /= 2;
     if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) mode_hdisplay += intel_dsi->pixel_overlap;
   }
   for_each_dsi_port(port, intel_dsi->ports) {
     if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
       /*
        * escape clock divider, 20MHz, shared for A and C.
        * device ready must be off when doing this! txclkesc?
        */
       tmp = I915_READ(MIPI_CTRL(PORT_A));
       tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK;
       I915_WRITE(MIPI_CTRL(PORT_A), tmp | ESCAPE_CLOCK_DIVIDER_1);
       /* read request priority is per pipe */
       tmp = I915_READ(MIPI_CTRL(port));
       tmp &= ~READ_REQUEST_PRIORITY_MASK;
       I915_WRITE(MIPI_CTRL(port), tmp | READ_REQUEST_PRIORITY_HIGH);
-    } else if (IS_BROXTON(dev_priv)) {
+    } else if (IS_GEN9_LP(dev_priv)) {
       enum pipe pipe = intel_crtc->pipe;
       tmp = I915_READ(MIPI_CTRL(port));
       tmp &= ~BXT_PIPE_SELECT_MASK;
       tmp |= BXT_PIPE_SELECT(pipe);
       I915_WRITE(MIPI_CTRL(port), tmp);
     }
     /* XXX: why here, why like this? handling in irq handler?! */
     I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff);
     I915_WRITE(MIPI_INTR_EN(port), 0xffffffff);
     I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg);
     I915_WRITE(MIPI_DPI_RESOLUTION(port), adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT);
   }
   set_dsi_timings(encoder, adjusted_mode);
   val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT;
   if (is_cmd_mode(intel_dsi)) {
     val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT;
     val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */
   } else {
     val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT;
     val |= pixel_format_to_reg(intel_dsi->pixel_format);
   }
   tmp = 0;
   if (intel_dsi->eotp_pkt == 0) tmp |= EOT_DISABLE;
   if (intel_dsi->clock_stop) tmp |= CLOCKSTOP;
-  if (IS_BROXTON(dev_priv)) {
+  if (IS_GEN9_LP(dev_priv)) {
     tmp |= BXT_DPHY_DEFEATURE_EN;
     if (!is_cmd_mode(intel_dsi)) tmp |= BXT_DEFEATURE_DPI_FIFO_CTR;
   }
   for_each_dsi_port(port, intel_dsi->ports) {
     I915_WRITE(MIPI_DSI_FUNC_PRG(port), val);
     /* timeouts for recovery. one frame IIUC. if counter expires,
      * EOT and stop state. */
     /*
      * In burst mode, value greater than one DPI line Time in byte
      * clock (txbyteclkhs) To timeout this timer 1+ of the above
      * said value is recommended.
      *
      * In non-burst mode, Value greater than one DPI frame time in
      * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
      * said value is recommended.
      *
      * In DBI only mode, value greater than one DBI frame time in
      * byte clock(txbyteclkhs) To timeout this timer 1+ of the above
      * said value is recommended.
      */
     if (is_vid_mode(intel_dsi) && intel_dsi->video_mode_format == VIDEO_MODE_BURST) {
       I915_WRITE(MIPI_HS_TX_TIMEOUT(port), txbyteclkhs(adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
     } else {
       I915_WRITE(MIPI_HS_TX_TIMEOUT(port), txbyteclkhs(adjusted_mode->crtc_vtotal * adjusted_mode->crtc_htotal, bpp, intel_dsi->lane_count, intel_dsi->burst_mode_ratio) + 1);
     }
     I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout);
     I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), intel_dsi->turn_arnd_val);
     I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), intel_dsi->rst_timer_val);
     /* dphy stuff */
     /* in terms of low power clock */
     I915_WRITE(MIPI_INIT_COUNT(port), txclkesc(intel_dsi->escape_clk_div, 100));
-    if (IS_BROXTON(dev_priv) && (!intel_dsi->dual_link)) {
+    if (IS_GEN9_LP(dev_priv) && (!intel_dsi->dual_link)) {
       /*
        * BXT spec says write MIPI_INIT_COUNT for
        * both the ports, even if only one is
        * getting used. So write the other port
        * if not in dual link mode.
        */
       I915_WRITE(MIPI_INIT_COUNT(port == PORT_A ? PORT_C : PORT_A), intel_dsi->init_count);
     }
     /* recovery disables */
     I915_WRITE(MIPI_EOT_DISABLE(port), tmp);
     /* in terms of low power clock */
     I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count);
     /* in terms of txbyteclkhs. actual high to low switch +
      * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK.
      *
      * XXX: write MIPI_STOP_STATE_STALL?
      */
     I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), intel_dsi->hs_to_lp_count);
     /* XXX: low power clock equivalence in terms of byte clock.
      * the number of byte clocks occupied in one low power clock.
      * based on txbyteclkhs and txclkesc.
      * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL
      * ) / 105.???
      */
     I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk);
     /* the bw essential for transmitting 16 long packets containing
      * 252 bytes meant for dcs write memory command is programmed in
      * this register in terms of byte clocks. based on dsi transfer
      * rate and the number of lanes configured the time taken to
      * transmit 16 long packets in a dsi stream varies. */
     I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer);
     I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT);
     if (is_vid_mode(intel_dsi))
       /* Some panels might have resolution which is not a
        * multiple of 64 like 1366 x 768. Enable RANDOM
        * resolution support for such panels by default */
       I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), intel_dsi->video_frmt_cfg_bits | intel_dsi->video_mode_format | IP_TG_CONFIG | RANDOM_DPI_DISPLAY_RESOLUTION);
   }
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)