imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,68 +1,68 @@
 static int sun4i_tv_bind(struct device *dev, struct device *master, void *data) {
   struct platform_device *pdev = to_platform_device(dev);
   struct drm_device *drm = data;
   struct sun4i_drv *drv = drm->dev_private;
   struct sun4i_tv *tv;
   struct resource *res;
   void __iomem *regs;
   int ret;
   tv = devm_kzalloc(dev, sizeof(*tv), GFP_KERNEL);
   if (!tv) return -ENOMEM;
   tv->drv = drv;
   dev_set_drvdata(dev, tv);
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   regs = devm_ioremap_resource(dev, res);
   if (IS_ERR(regs)) {
     dev_err(dev, "Couldn't map the TV encoder registers\n");
     return PTR_ERR(regs);
   }
   tv->regs = devm_regmap_init_mmio(dev, regs, &sun4i_tv_regmap_config);
   if (IS_ERR(tv->regs)) {
     dev_err(dev, "Couldn't create the TV encoder regmap\n");
     return PTR_ERR(tv->regs);
   }
   tv->reset = devm_reset_control_get(dev, NULL);
   if (IS_ERR(tv->reset)) {
     dev_err(dev, "Couldn't get our reset line\n");
     return PTR_ERR(tv->reset);
   }
   ret = reset_control_deassert(tv->reset);
   if (ret) {
     dev_err(dev, "Couldn't deassert our reset line\n");
     return ret;
   }
   tv->clk = devm_clk_get(dev, NULL);
   if (IS_ERR(tv->clk)) {
     dev_err(dev, "Couldn't get the TV encoder clock\n");
     ret = PTR_ERR(tv->clk);
     goto err_assert_reset;
   }
   clk_prepare_enable(tv->clk);
   drm_encoder_helper_add(&tv->encoder, &sun4i_tv_helper_funcs);
   ret = drm_encoder_init(drm, &tv->encoder, &sun4i_tv_funcs, DRM_MODE_ENCODER_TVDAC, NULL);
   if (ret) {
     dev_err(dev, "Couldn't initialise the TV encoder\n");
     goto err_disable_clk;
   }
   tv->encoder.possible_crtcs = drm_of_find_possible_crtcs(drm, dev->of_node);
   if (!tv->encoder.possible_crtcs) {
     ret = -EPROBE_DEFER;
     goto err_disable_clk;
   }
   drm_connector_helper_add(&tv->connector, &sun4i_tv_comp_connector_helper_funcs);
   ret = drm_connector_init(drm, &tv->connector, &sun4i_tv_comp_connector_funcs, DRM_MODE_CONNECTOR_Composite);
   if (ret) {
     dev_err(dev, "Couldn't initialise the Composite connector\n");
     goto err_cleanup_connector;
   }
   tv->connector.interlace_allowed = true;
-  drm_mode_connector_attach_encoder(&tv->connector, &tv->encoder);
+  drm_connector_attach_encoder(&tv->connector, &tv->encoder);
   return 0;
 err_cleanup_connector:
   drm_encoder_cleanup(&tv->encoder);
 err_disable_clk:
   clk_disable_unprepare(tv->clk);
 err_assert_reset:
   reset_control_assert(tv->reset);
   return ret;
 }<sep>@@
expression e1,e2;
@@
-        drm_mode_connector_attach_encoder
+        drm_connector_attach_encoder
		(e1,e2)
--- initial
+++ final
@@ -1,36 +1,36 @@
 int arcpgu_drm_sim_init(struct drm_device *drm, struct device_node *np) {
   struct arcpgu_drm_connector *arcpgu_connector;
   struct drm_encoder *encoder;
   struct drm_connector *connector;
   int ret;
   encoder = devm_kzalloc(drm->dev, sizeof(*encoder), GFP_KERNEL);
   if (encoder == NULL) return -ENOMEM;
   encoder->possible_crtcs = 1;
   encoder->possible_clones = 0;
   ret = drm_encoder_init(drm, encoder, &arcpgu_drm_encoder_funcs, DRM_MODE_ENCODER_VIRTUAL, NULL);
   if (ret) return ret;
   arcpgu_connector = devm_kzalloc(drm->dev, sizeof(*arcpgu_connector), GFP_KERNEL);
   if (!arcpgu_connector) {
     ret = -ENOMEM;
     goto error_encoder_cleanup;
   }
   connector = &arcpgu_connector->connector;
   drm_connector_helper_add(connector, &arcpgu_drm_connector_helper_funcs);
   ret = drm_connector_init(drm, connector, &arcpgu_drm_connector_funcs, DRM_MODE_CONNECTOR_VIRTUAL);
   if (ret < 0) {
     dev_err(drm->dev, "failed to initialize drm connector\n");
     goto error_encoder_cleanup;
   }
-  ret = drm_mode_connector_attach_encoder(connector, encoder);
+  ret = drm_connector_attach_encoder(connector, encoder);
   if (ret < 0) {
     dev_err(drm->dev, "could not attach connector to encoder\n");
     drm_connector_unregister(connector);
     goto error_connector_cleanup;
   }
   return 0;
 error_connector_cleanup:
   drm_connector_cleanup(connector);
 error_encoder_cleanup:
   drm_encoder_cleanup(encoder);
   return ret;
 }<sep>@@
expression e1,e2;
@@
-        drm_mode_connector_attach_encoder
+        drm_connector_attach_encoder
		(e1,e2)
--- initial
+++ final
@@ -1,60 +1,60 @@
 struct mdfld_dsi_encoder *mdfld_dsi_dpi_init(struct drm_device *dev, struct mdfld_dsi_connector *dsi_connector, const struct panel_funcs *p_funcs) {
   struct mdfld_dsi_dpi_output *dpi_output = NULL;
   struct mdfld_dsi_config *dsi_config;
   struct drm_connector *connector = NULL;
   struct drm_encoder *encoder = NULL;
   int pipe;
   u32 data;
   int ret;
   pipe = dsi_connector->pipe;
   if (mdfld_get_panel_type(dev, pipe) != TC35876X) {
     dsi_config = mdfld_dsi_get_config(dsi_connector);
     /* panel hard-reset */
     if (p_funcs->reset) {
       ret = p_funcs->reset(pipe);
       if (ret) {
         DRM_ERROR("Panel %d hard-reset failed\n", pipe);
         return NULL;
       }
     }
     /* panel drvIC init */
     if (p_funcs->drv_ic_init) p_funcs->drv_ic_init(dsi_config, pipe);
     /* panel power mode detect */
     ret = mdfld_dsi_get_power_mode(dsi_config, &data, false);
     if (ret) {
       DRM_ERROR("Panel %d get power mode failed\n", pipe);
       dsi_connector->status = connector_status_disconnected;
     } else {
       DRM_INFO("pipe %d power mode 0x%x\n", pipe, data);
       dsi_connector->status = connector_status_connected;
     }
   }
   dpi_output = kzalloc(sizeof(struct mdfld_dsi_dpi_output), GFP_KERNEL);
   if (!dpi_output) {
     DRM_ERROR("No memory\n");
     return NULL;
   }
   dpi_output->panel_on = 0;
   dpi_output->dev = dev;
   if (mdfld_get_panel_type(dev, pipe) != TC35876X) dpi_output->p_funcs = p_funcs;
   dpi_output->first_boot = 1;
   /*get fixed mode*/
   dsi_config = mdfld_dsi_get_config(dsi_connector);
   /*create drm encoder object*/
   connector = &dsi_connector->base.base;
   encoder = &dpi_output->base.base.base;
   drm_encoder_init(dev, encoder, p_funcs->encoder_funcs, DRM_MODE_ENCODER_LVDS, NULL);
   drm_encoder_helper_add(encoder, p_funcs->encoder_helper_funcs);
   /*attach to given connector*/
-  drm_mode_connector_attach_encoder(connector, encoder);
+  drm_connector_attach_encoder(connector, encoder);
   /*set possible crtcs and clones*/
   if (dsi_connector->pipe) {
     encoder->possible_crtcs = (1 << 2);
     encoder->possible_clones = (1 << 1);
   } else {
     encoder->possible_crtcs = (1 << 0);
     encoder->possible_clones = (1 << 0);
   }
   dsi_connector->base.encoder = &dpi_output->base.base;
   return &dpi_output->base;
 }<sep>@@
expression e1,e2;
@@
-        drm_mode_connector_attach_encoder
+        drm_connector_attach_encoder
		(e1,e2)
--- initial
+++ final
@@ -1,22 +1,22 @@
 struct drm_connector *msm_hdmi_connector_init(struct hdmi *hdmi) {
   struct drm_connector *connector = NULL;
   struct hdmi_connector *hdmi_connector;
   int ret;
   hdmi_connector = kzalloc(sizeof(*hdmi_connector), GFP_KERNEL);
   if (!hdmi_connector) return ERR_PTR(-ENOMEM);
   hdmi_connector->hdmi = hdmi;
   INIT_WORK(&hdmi_connector->hpd_work, msm_hdmi_hotplug_work);
   connector = &hdmi_connector->base;
   drm_connector_init(hdmi->dev, connector, &hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
   drm_connector_helper_add(connector, &msm_hdmi_connector_helper_funcs);
   connector->polled = DRM_CONNECTOR_POLL_CONNECT | DRM_CONNECTOR_POLL_DISCONNECT;
   connector->interlace_allowed = 0;
   connector->doublescan_allowed = 0;
   ret = hpd_enable(hdmi_connector);
   if (ret) {
     dev_err(&hdmi->pdev->dev, "failed to enable HPD: %d\n", ret);
     return ERR_PTR(ret);
   }
-  drm_mode_connector_attach_encoder(connector, hdmi->encoder);
+  drm_connector_attach_encoder(connector, hdmi->encoder);
   return connector;
 }<sep>@@
expression e1,e2;
@@
-        drm_mode_connector_attach_encoder
+        drm_connector_attach_encoder
		(e1,e2)
--- initial
+++ final
@@ -1,13 +1,13 @@
 static int imx_tve_register(struct drm_device *drm, struct imx_tve *tve) {
   int encoder_type;
   int ret;
   encoder_type = tve->mode == TVE_MODE_VGA ? DRM_MODE_ENCODER_DAC : DRM_MODE_ENCODER_TVDAC;
   ret = imx_drm_encoder_parse_of(drm, &tve->encoder, tve->dev->of_node);
   if (ret) return ret;
   drm_encoder_helper_add(&tve->encoder, &imx_tve_encoder_helper_funcs);
   drm_encoder_init(drm, &tve->encoder, &imx_tve_encoder_funcs, encoder_type, NULL);
   drm_connector_helper_add(&tve->connector, &imx_tve_connector_helper_funcs);
   drm_connector_init(drm, &tve->connector, &imx_tve_connector_funcs, DRM_MODE_CONNECTOR_VGA);
-  drm_mode_connector_attach_encoder(&tve->connector, &tve->encoder);
+  drm_connector_attach_encoder(&tve->connector, &tve->encoder);
   return 0;
 }<sep>@@
expression e1,e2;
@@
-        drm_mode_connector_attach_encoder
+        drm_connector_attach_encoder
		(e1,e2)
--- initial
+++ final
@@ -1,6 +1,6 @@
 static void dcn10_disable_plane(struct dc *dc, struct pipe_ctx *pipe_ctx) {
   if (!pipe_ctx->plane_res.hubp || pipe_ctx->plane_res.hubp->power_gated) return;
   plane_atomic_disable(dc, pipe_ctx);
   apply_DEGVIDCN10_253_wa(dc);
-  dm_logger_write(dc->ctx->logger, LOG_DC, "Power down front end %d\n", pipe_ctx->pipe_idx);
+  DC_LOG_DC(dc->ctx->logger, "Power down front end %d\n", pipe_ctx->pipe_idx);
 }<sep>@@
expression e1;
@@

- dm_logger_write(e1,LOG_DC,
+ DC_LOG_DC(e1,
	...)
--- initial
+++ final
@@ -1,39 +1,39 @@
 static bool read_command(struct aux_engine *engine, struct i2caux_transaction_request *request, bool middle_of_transaction) {
   struct read_command_context ctx;
   ctx.buffer = request->payload.data;
   ctx.current_read_length = request->payload.length;
   ctx.offset = 0;
   ctx.timed_out_retry_aux = 0;
   ctx.invalid_reply_retry_aux = 0;
   ctx.defer_retry_aux = 0;
   ctx.defer_retry_i2c = 0;
   ctx.invalid_reply_retry_aux_on_ack = 0;
   ctx.transaction_complete = false;
   ctx.operation_succeeded = true;
   if (request->payload.address_space == I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) {
     ctx.request.type = AUX_TRANSACTION_TYPE_DP;
     ctx.request.action = I2CAUX_TRANSACTION_ACTION_DP_READ;
     ctx.request.address = request->payload.address;
   } else if (request->payload.address_space == I2CAUX_TRANSACTION_ADDRESS_SPACE_I2C) {
     ctx.request.type = AUX_TRANSACTION_TYPE_I2C;
     ctx.request.action = middle_of_transaction ? I2CAUX_TRANSACTION_ACTION_I2C_READ_MOT : I2CAUX_TRANSACTION_ACTION_I2C_READ;
     ctx.request.address = request->payload.address >> 1;
   } else {
     /* in DAL2, there was no return in such case */
     BREAK_TO_DEBUGGER();
     return false;
   }
   ctx.request.delay = 0;
   do {
     memset(ctx.buffer + ctx.offset, 0, ctx.current_read_length);
     ctx.request.data = ctx.buffer + ctx.offset;
     ctx.request.length = ctx.current_read_length;
     process_read_request(engine, &ctx);
     request->status = ctx.status;
     if (ctx.operation_succeeded && !ctx.transaction_complete)
       if (ctx.request.type == AUX_TRANSACTION_TYPE_I2C) msleep(engine->delay);
   } while (ctx.operation_succeeded && !ctx.transaction_complete);
-  if (request->payload.address_space == I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) { dm_logger_write(engine->base.ctx->logger, LOG_I2C_AUX, "READ: addr:0x%x  value:0x%x Result:%d", request->payload.address, request->payload.data[0], ctx.operation_succeeded); }
+  if (request->payload.address_space == I2CAUX_TRANSACTION_ADDRESS_SPACE_DPCD) { DC_LOG_I2C_AUX(engine->base.ctx->logger, "READ: addr:0x%x  value:0x%x Result:%d", request->payload.address, request->payload.data[0], ctx.operation_succeeded); }
   request->payload.length = ctx.reply.length;
   return ctx.operation_succeeded;
 }<sep>@@
expression e1;
@@

- dm_logger_write(e1,LOG_I2C_AUX,
+ DC_LOG_I2C_AUX(e1,
	...)
--- initial
+++ final
@@ -1,43 +1,43 @@
 static bool hpd_rx_irq_check_link_loss_status(struct dc_link *link, union hpd_irq_data *hpd_irq_dpcd_data) {
   uint8_t irq_reg_rx_power_state = 0;
   enum dc_status dpcd_result = DC_ERROR_UNEXPECTED;
   union lane_status lane_status;
   uint32_t lane;
   bool sink_status_changed;
   bool return_code;
   sink_status_changed = false;
   return_code = false;
   if (link->cur_link_settings.lane_count == 0) return return_code;
   /*1. Check that Link Status changed, before re-training.*/
   /*parse lane status*/
   for (lane = 0; lane < link->cur_link_settings.lane_count; lane++) {
     /* check status of lanes 0,1
      * changed DpcdAddress_Lane01Status (0x202)
      */
     lane_status.raw = get_nibble_at_index(&hpd_irq_dpcd_data->bytes.lane01_status.raw, lane);
     if (!lane_status.bits.CHANNEL_EQ_DONE_0 || !lane_status.bits.CR_DONE_0 || !lane_status.bits.SYMBOL_LOCKED_0) {
       /* if one of the channel equalization, clock
        * recovery or symbol lock is dropped
        * consider it as (link has been
        * dropped) dp sink status has changed
        */
       sink_status_changed = true;
       break;
     }
   }
   /* Check interlane align.*/
   if (sink_status_changed || !hpd_irq_dpcd_data->bytes.lane_status_updated.bits.INTERLANE_ALIGN_DONE) {
-    dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ, "%s: Link Status changed.\n", __func__);
+    DC_LOG_HW_HPD_IRQ(link->ctx->logger, "%s: Link Status changed.\n", __func__);
     return_code = true;
     /*2. Check that we can handle interrupt: Not in FS DOS,
      *  Not in "Display Timeout" state, Link is trained.
      */
     dpcd_result = core_link_read_dpcd(link, DP_SET_POWER, &irq_reg_rx_power_state, sizeof(irq_reg_rx_power_state));
     if (dpcd_result != DC_OK) {
-      dm_logger_write(link->ctx->logger, LOG_HW_HPD_IRQ, "%s: DPCD read failed to obtain power state.\n", __func__);
+      DC_LOG_HW_HPD_IRQ(link->ctx->logger, "%s: DPCD read failed to obtain power state.\n", __func__);
     } else {
       if (irq_reg_rx_power_state != DP_SET_POWER_D0) return_code = false;
     }
   }
   return return_code;
 }<sep>@@
expression e1;
@@

- dm_logger_write(e1,LOG_HW_HPD_IRQ,
+ DC_LOG_HW_HPD_IRQ(e1,
	...)
--- initial
+++ final
@@ -1,15 +1,15 @@
 static void dpcd_set_link_settings(struct dc_link *link, const struct link_training_settings *lt_settings) {
   uint8_t rate = (uint8_t)(lt_settings->link_settings.link_rate);
   union down_spread_ctrl downspread = {{0}};
   union lane_count_set lane_count_set = {{0}};
   uint8_t link_set_buffer[2];
   downspread.raw = (uint8_t)(lt_settings->link_settings.link_spread);
   lane_count_set.bits.LANE_COUNT_SET = lt_settings->link_settings.lane_count;
   lane_count_set.bits.ENHANCED_FRAMING = 1;
   lane_count_set.bits.POST_LT_ADJ_REQ_GRANTED = link->dpcd_caps.max_ln_count.bits.POST_LT_ADJ_REQ_SUPPORTED;
   link_set_buffer[0] = rate;
   link_set_buffer[1] = lane_count_set.raw;
   core_link_write_dpcd(link, DP_LINK_BW_SET, link_set_buffer, 2);
   core_link_write_dpcd(link, DP_DOWNSPREAD_CTRL, &downspread.raw, sizeof(downspread));
-  dm_logger_write(link->ctx->logger, LOG_HW_LINK_TRAINING, "%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n", __func__, DP_LINK_BW_SET, lt_settings->link_settings.link_rate, DP_LANE_COUNT_SET, lt_settings->link_settings.lane_count, DP_DOWNSPREAD_CTRL, lt_settings->link_settings.link_spread);
+  DC_LOG_HW_LINK_TRAINING(link->ctx->logger, "%s\n %x rate = %x\n %x lane = %x\n %x spread = %x\n", __func__, DP_LINK_BW_SET, lt_settings->link_settings.link_rate, DP_LANE_COUNT_SET, lt_settings->link_settings.lane_count, DP_DOWNSPREAD_CTRL, lt_settings->link_settings.link_spread);
 }<sep>@@
expression e1;
@@

- dm_logger_write(e1,LOG_HW_LINK_TRAINING,
+ DC_LOG_HW_LINK_TRAINING(e1,
	...)
--- initial
+++ final
@@ -1,47 +1,47 @@
 static enum bp_result set_pixel_clock_v7(struct bios_parser *bp, struct bp_pixel_clock_parameters *bp_params) {
   enum bp_result result = BP_RESULT_FAILURE;
   struct set_pixel_clock_parameter_v1_7 clk;
   uint8_t controller_id;
   uint32_t pll_id;
   memset(&clk, 0, sizeof(clk));
   if (bp->cmd_helper->clock_source_id_to_atom(bp_params->pll_id, &pll_id) && bp->cmd_helper->controller_id_to_atom(bp_params->controller_id, &controller_id)) {
     /* Note: VBIOS still wants to use ucCRTC name which is now
      * 1 byte in ULONG
      *typedef struct _CRTC_PIXEL_CLOCK_FREQ
      *{
      * target the pixel clock to drive the CRTC timing.
      * ULONG ulPixelClock:24;
      * 0 means disable PPLL/DCPLL. Expanded to 24 bits comparing to
      * previous version.
      * ATOM_CRTC1~6, indicate the CRTC controller to
      * ULONG ucCRTC:8;
      * drive the pixel clock. not used for DCPLL case.
      *}CRTC_PIXEL_CLOCK_FREQ;
      *union
      *{
      * pixel clock and CRTC id frequency
      * CRTC_PIXEL_CLOCK_FREQ ulCrtcPclkFreq;
      * ULONG ulDispEngClkFreq; dispclk frequency
      *};
      */
     clk.crtc_id = controller_id;
     clk.pll_id = (uint8_t)pll_id;
     clk.encoderobjid = bp->cmd_helper->encoder_id_to_atom(dal_graphics_object_id_get_encoder_id(bp_params->encoder_object_id));
     clk.encoder_mode = (uint8_t)bp->cmd_helper->encoder_mode_bp_to_atom(bp_params->signal_type, false);
     /* We need to convert from KHz units into 10KHz units */
     clk.pixclk_100hz = cpu_to_le32(bp_params->target_pixel_clock * 10);
     clk.deep_color_ratio = (uint8_t)bp->cmd_helper->transmitter_color_depth_to_atom(bp_params->color_depth);
-    dm_logger_write(bp->base.ctx->logger, LOG_BIOS,
-                    "%s:program display clock = %d"
-                    "colorDepth = %d\n",
-                    __func__, bp_params->target_pixel_clock, bp_params->color_depth);
+    DC_LOG_BIOS(bp->base.ctx->logger,
+                "%s:program display clock = %d"
+                "colorDepth = %d\n",
+                __func__, bp_params->target_pixel_clock, bp_params->color_depth);
     if (bp_params->flags.FORCE_PROGRAMMING_OF_PLL) clk.miscinfo |= PIXEL_CLOCK_V7_MISC_FORCE_PROG_PPLL;
     if (bp_params->flags.PROGRAM_PHY_PLL_ONLY) clk.miscinfo |= PIXEL_CLOCK_V7_MISC_PROG_PHYPLL;
     if (bp_params->flags.SUPPORT_YUV_420) clk.miscinfo |= PIXEL_CLOCK_V7_MISC_YUV420_MODE;
     if (bp_params->flags.SET_XTALIN_REF_SRC) clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_XTALIN;
     if (bp_params->flags.SET_GENLOCK_REF_DIV_SRC) clk.miscinfo |= PIXEL_CLOCK_V7_MISC_REF_DIV_SRC_GENLK;
     if (bp_params->signal_type == SIGNAL_TYPE_DVI_DUAL_LINK) clk.miscinfo |= PIXEL_CLOCK_V7_MISC_DVI_DUALLINK_EN;
     if (EXEC_BIOS_CMD_TABLE(setpixelclock, clk)) result = BP_RESULT_OK;
   }
   return result;
 }<sep>@@
expression e1;
@@

- dm_logger_write(e1,LOG_BIOS,
+ DC_LOG_BIOS(e1,
	...)
--- initial
+++ final
@@ -1,46 +1,46 @@
 static void dce110_se_setup_hdmi_audio(struct stream_encoder *enc, const struct audio_crtc_info *crtc_info) {
   struct dce110_stream_encoder *enc110 = DCE110STRENC_FROM_STRENC(enc);
   struct audio_clock_info audio_clock_info = {0};
   uint32_t max_packets_per_line;
   /* For now still do calculation, although this field is ignored when
   above HDMI_PACKET_GEN_VERSION set to 1 */
   max_packets_per_line = calc_max_audio_packets_per_line(crtc_info);
   /* HDMI_AUDIO_PACKET_CONTROL */
   REG_UPDATE_2(HDMI_AUDIO_PACKET_CONTROL, HDMI_AUDIO_PACKETS_PER_LINE, max_packets_per_line, HDMI_AUDIO_DELAY_EN, 1);
   /* AFMT_AUDIO_PACKET_CONTROL */
   REG_UPDATE(AFMT_AUDIO_PACKET_CONTROL, AFMT_60958_CS_UPDATE, 1);
   /* AFMT_AUDIO_PACKET_CONTROL2 */
   REG_UPDATE_2(AFMT_AUDIO_PACKET_CONTROL2, AFMT_AUDIO_LAYOUT_OVRD, 0, AFMT_60958_OSF_OVRD, 0);
   /* HDMI_ACR_PACKET_CONTROL */
   REG_UPDATE_3(HDMI_ACR_PACKET_CONTROL, HDMI_ACR_AUTO_SEND, 1, HDMI_ACR_SOURCE, 0, HDMI_ACR_AUDIO_PRIORITY, 0);
   /* Program audio clock sample/regeneration parameters */
   get_audio_clock_info(crtc_info->color_depth, crtc_info->requested_pixel_clock, crtc_info->calculated_pixel_clock, &audio_clock_info);
-  dm_logger_write(enc->ctx->logger, LOG_HW_AUDIO,
+  DC_LOG_HW_AUDIO(enc->ctx->logger,
                   "\n%s:Input::requested_pixel_clock = %d"
                   "calculated_pixel_clock = %d \n",
                   __func__, crtc_info->requested_pixel_clock, crtc_info->calculated_pixel_clock);
   /* HDMI_ACR_32_0__HDMI_ACR_CTS_32_MASK */
   REG_UPDATE(HDMI_ACR_32_0, HDMI_ACR_CTS_32, audio_clock_info.cts_32khz);
   /* HDMI_ACR_32_1__HDMI_ACR_N_32_MASK */
   REG_UPDATE(HDMI_ACR_32_1, HDMI_ACR_N_32, audio_clock_info.n_32khz);
   /* HDMI_ACR_44_0__HDMI_ACR_CTS_44_MASK */
   REG_UPDATE(HDMI_ACR_44_0, HDMI_ACR_CTS_44, audio_clock_info.cts_44khz);
   /* HDMI_ACR_44_1__HDMI_ACR_N_44_MASK */
   REG_UPDATE(HDMI_ACR_44_1, HDMI_ACR_N_44, audio_clock_info.n_44khz);
   /* HDMI_ACR_48_0__HDMI_ACR_CTS_48_MASK */
   REG_UPDATE(HDMI_ACR_48_0, HDMI_ACR_CTS_48, audio_clock_info.cts_48khz);
   /* HDMI_ACR_48_1__HDMI_ACR_N_48_MASK */
   REG_UPDATE(HDMI_ACR_48_1, HDMI_ACR_N_48, audio_clock_info.n_48khz);
   /* Video driver cannot know in advance which sample rate will
      be used by HD Audio driver
      HDMI_ACR_PACKET_CONTROL__HDMI_ACR_N_MULTIPLE field is
      programmed below in interruppt callback */
   /* AFMT_60958_0__AFMT_60958_CS_CHANNEL_NUMBER_L_MASK &
   AFMT_60958_0__AFMT_60958_CS_CLOCK_ACCURACY_MASK */
   REG_UPDATE_2(AFMT_60958_0, AFMT_60958_CS_CHANNEL_NUMBER_L, 1, AFMT_60958_CS_CLOCK_ACCURACY, 0);
   /* AFMT_60958_1 AFMT_60958_CS_CHALNNEL_NUMBER_R */
   REG_UPDATE(AFMT_60958_1, AFMT_60958_CS_CHANNEL_NUMBER_R, 2);
   /*AFMT_60958_2 now keep this settings until
    *  Programming guide comes out*/
   REG_UPDATE_6(AFMT_60958_2, AFMT_60958_CS_CHANNEL_NUMBER_2, 3, AFMT_60958_CS_CHANNEL_NUMBER_3, 4, AFMT_60958_CS_CHANNEL_NUMBER_4, 5, AFMT_60958_CS_CHANNEL_NUMBER_5, 6, AFMT_60958_CS_CHANNEL_NUMBER_6, 7, AFMT_60958_CS_CHANNEL_NUMBER_7, 8);
 }<sep>@@
expression e1;
@@

- dm_logger_write(e1,LOG_HW_AUDIO,
+ DC_LOG_HW_AUDIO(e1,
	...)
--- initial
+++ final
@@ -1,10 +1,10 @@
 static bool dce_abm_set_backlight_level(struct abm *abm, unsigned int backlight_level, unsigned int frame_ramp, unsigned int controller_id, bool use_smooth_brightness) {
   struct dce_abm *abm_dce = TO_DCE_ABM(abm);
-  dm_logger_write(abm->ctx->logger, LOG_BACKLIGHT, "New Backlight level: %d (0x%X)\n", backlight_level, backlight_level);
+  DC_LOG_BACKLIGHT(abm->ctx->logger, "New Backlight level: %d (0x%X)\n", backlight_level, backlight_level);
   /* If DMCU is in reset state, DMCU is uninitialized */
   if (use_smooth_brightness)
     dmcu_set_backlight_level(abm_dce, backlight_level, frame_ramp, controller_id);
   else
     driver_set_backlight_level(abm_dce, backlight_level);
   return true;
 }<sep>@@
expression e1;
@@

- dm_logger_write(e1,LOG_BACKLIGHT,
+ DC_LOG_BACKLIGHT(e1,
	...)
--- initial
+++ final
@@ -1,24 +1,24 @@
 void hwss_edp_power_control(struct dc_link *link, bool power_up) {
   struct dc_context *ctx = link->ctx;
   struct dce_hwseq *hwseq = ctx->dc->hwseq;
   struct bp_transmitter_control cntl = {0};
   enum bp_result bp_result;
   if (dal_graphics_object_id_get_connector_id(link->link_enc->connector) != CONNECTOR_ID_EDP) {
     BREAK_TO_DEBUGGER();
     return;
   }
   if (power_up != is_panel_powered_on(hwseq)) {
     /* Send VBIOS command to prompt eDP panel power */
-    dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, "%s: Panel Power action: %s\n", __func__, (power_up ? "On" : "Off"));
+    DC_LOG_HW_RESUME_S3(ctx->logger, "%s: Panel Power action: %s\n", __func__, (power_up ? "On" : "Off"));
     cntl.action = power_up ? TRANSMITTER_CONTROL_POWER_ON : TRANSMITTER_CONTROL_POWER_OFF;
     cntl.transmitter = link->link_enc->transmitter;
     cntl.connector_obj_id = link->link_enc->connector;
     cntl.coherent = false;
     cntl.lanes_number = LANE_COUNT_FOUR;
     cntl.hpd_sel = link->link_enc->hpd_source;
     bp_result = link_transmitter_control(ctx->dc_bios, &cntl);
-    if (bp_result != BP_RESULT_OK) dm_logger_write(ctx->logger, LOG_ERROR, "%s: Panel Power bp_result: %d\n", __func__, bp_result);
+    if (bp_result != BP_RESULT_OK) DC_LOG_ERROR(ctx->logger, "%s: Panel Power bp_result: %d\n", __func__, bp_result);
   } else {
-    dm_logger_write(ctx->logger, LOG_HW_RESUME_S3, "%s: Skipping Panel Power action: %s\n", __func__, (power_up ? "On" : "Off"));
+    DC_LOG_HW_RESUME_S3(ctx->logger, "%s: Skipping Panel Power action: %s\n", __func__, (power_up ? "On" : "Off"));
   }
 }<sep>@@
expression e1;
@@

- dm_logger_write(e1,LOG_HW_RESUME_S3,
+ DC_LOG_HW_RESUME_S3(e1,
	...)

@@
expression e1;
@@

- dm_logger_write(e1,LOG_ERROR,
+ DC_LOG_ERROR(e1,
	...)