--- initial
+++ final
@@ -1,88 +1,88 @@
 static void au1550_command(struct nand_chip *this, unsigned command, int column, int page_addr) {
   struct mtd_info *mtd = nand_to_mtd(this);
   struct au1550nd_ctx *ctx = container_of(this, struct au1550nd_ctx, chip);
   int ce_override = 0, i;
   unsigned long flags = 0;
   /* Begin command latch cycle */
   au1550_hwcontrol(mtd, NAND_CTL_SETCLE);
   /*
    * Write out the command to the device.
    */
   if (command == NAND_CMD_SEQIN) {
     int readcmd;
     if (column >= mtd->writesize) {
       /* OOB area */
       column -= mtd->writesize;
       readcmd = NAND_CMD_READOOB;
     } else if (column < 256) {
       /* First 256 bytes --> READ0 */
       readcmd = NAND_CMD_READ0;
     } else {
       column -= 256;
       readcmd = NAND_CMD_READ1;
     }
     ctx->write_byte(this, readcmd);
   }
   ctx->write_byte(this, command);
   /* Set ALE and clear CLE to start address cycle */
   au1550_hwcontrol(mtd, NAND_CTL_CLRCLE);
   if (column != -1 || page_addr != -1) {
     au1550_hwcontrol(mtd, NAND_CTL_SETALE);
     /* Serially input address */
     if (column != -1) {
       /* Adjust columns for 16 bit buswidth */
       if (this->options & NAND_BUSWIDTH_16 && !nand_opcode_8bits(command)) column >>= 1;
       ctx->write_byte(this, column);
     }
     if (page_addr != -1) {
       ctx->write_byte(this, (u8)(page_addr & 0xff));
       if (command == NAND_CMD_READ0 || command == NAND_CMD_READ1 || command == NAND_CMD_READOOB) {
         /*
          * NAND controller will release -CE after
          * the last address byte is written, so we'll
          * have to forcibly assert it. No interrupts
          * are allowed while we do this as we don't
          * want the NOR flash or PCMCIA drivers to
          * steal our precious bytes of data...
          */
         ce_override = 1;
         local_irq_save(flags);
         au1550_hwcontrol(mtd, NAND_CTL_SETNCE);
       }
       ctx->write_byte(this, (u8)(page_addr >> 8));
       if (this->options & NAND_ROW_ADDR_3) ctx->write_byte(this, ((page_addr >> 16) & 0x0f));
     }
     /* Latch in address */
     au1550_hwcontrol(mtd, NAND_CTL_CLRALE);
   }
   /*
    * Program and erase have their own busy handlers.
    * Status and sequential in need no delay.
    */
   switch (command) {
   case NAND_CMD_PAGEPROG:
   case NAND_CMD_ERASE1:
   case NAND_CMD_ERASE2:
   case NAND_CMD_SEQIN:
   case NAND_CMD_STATUS: return;
   case NAND_CMD_RESET: break;
   case NAND_CMD_READ0:
   case NAND_CMD_READ1:
   case NAND_CMD_READOOB:
     /* Check if we're really driving -CE low (just in case) */
     if (unlikely(!ce_override)) break;
     /* Apply a short delay always to ensure that we do wait tWB. */
     ndelay(100);
     /* Wait for a chip to become ready... */
-    for (i = this->chip_delay; !this->legacy.dev_ready(this) && i > 0; --i)
+    for (i = this->legacy.chip_delay; !this->legacy.dev_ready(this) && i > 0; --i)
       udelay(1);
     /* Release -CE and re-enable interrupts. */
     au1550_hwcontrol(mtd, NAND_CTL_CLRNCE);
     local_irq_restore(flags);
     return;
   }
   /* Apply this short delay always to ensure that we do wait tWB. */
   ndelay(100);
   while (!this->legacy.dev_ready(this))
     ;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay