--- initial
+++ final
@@ -1,81 +1,81 @@
 static void nv_load_state_ext(struct drm_device *dev, int head, struct nv04_mode_state *state) {
   struct nouveau_drm *drm = nouveau_drm(dev);
-  struct nvif_object *device = &drm->device.object;
+  struct nvif_object *device = &drm->client.device.object;
   struct nv04_crtc_reg *regp = &state->crtc_reg[head];
   uint32_t reg900;
   int i;
-  if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
+  if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
     if (nv_two_heads(dev))
       /* setting ENGINE_CTRL (EC) *must* come before
        * CIO_CRE_LCD, as writing CRE_LCD sets bits 16 & 17 in
        * EC that should not be overwritten by writing stale EC
        */
       NVWriteCRTC(dev, head, NV_PCRTC_ENGINE_CTRL, regp->crtc_eng_ctrl);
     nvif_wr32(device, NV_PVIDEO_STOP, 1);
     nvif_wr32(device, NV_PVIDEO_INTR_EN, 0);
     nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(0), 0);
     nvif_wr32(device, NV_PVIDEO_OFFSET_BUFF(1), 0);
-    nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->device.info.ram_size - 1);
-    nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->device.info.ram_size - 1);
-    nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->device.info.ram_size - 1);
-    nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->device.info.ram_size - 1);
+    nvif_wr32(device, NV_PVIDEO_LIMIT(0), drm->client.device.info.ram_size - 1);
+    nvif_wr32(device, NV_PVIDEO_LIMIT(1), drm->client.device.info.ram_size - 1);
+    nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(0), drm->client.device.info.ram_size - 1);
+    nvif_wr32(device, NV_PVIDEO_UVPLANE_LIMIT(1), drm->client.device.info.ram_size - 1);
     nvif_wr32(device, NV_PBUS_POWERCTRL_2, 0);
     NVWriteCRTC(dev, head, NV_PCRTC_CURSOR_CONFIG, regp->cursor_cfg);
     NVWriteCRTC(dev, head, NV_PCRTC_830, regp->crtc_830);
     NVWriteCRTC(dev, head, NV_PCRTC_834, regp->crtc_834);
-    if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
-    if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) {
+    if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) NVWriteCRTC(dev, head, NV_PCRTC_GPIO_EXT, regp->gpio_ext);
+    if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) {
       NVWriteCRTC(dev, head, NV_PCRTC_850, regp->crtc_850);
       reg900 = NVReadRAMDAC(dev, head, NV_PRAMDAC_900);
       if (regp->crtc_cfg == NV10_PCRTC_CONFIG_START_ADDRESS_HSYNC)
         NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 | 0x10000);
       else
         NVWriteRAMDAC(dev, head, NV_PRAMDAC_900, reg900 & ~0x10000);
     }
   }
   NVWriteCRTC(dev, head, NV_PCRTC_CONFIG, regp->crtc_cfg);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC0_INDEX);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_RPC1_INDEX);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_LSR_INDEX);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_PIXEL_INDEX);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_LCD__INDEX);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_HEB__INDEX);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_ENH_INDEX);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_FF_INDEX);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_FFLWM__INDEX);
-  if (drm->device.info.family >= NV_DEVICE_INFO_V0_KELVIN) wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
-  if (drm->device.info.family >= NV_DEVICE_INFO_V0_RANKINE) wr_cio_state(dev, head, regp, 0x9f);
+  if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_KELVIN) wr_cio_state(dev, head, regp, NV_CIO_CRE_47);
+  if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_RANKINE) wr_cio_state(dev, head, regp, 0x9f);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_49);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR0_INDEX);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR1_INDEX);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_HCUR_ADDR2_INDEX);
-  if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) nv_fix_nv40_hw_cursor(dev, head);
+  if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) nv_fix_nv40_hw_cursor(dev, head);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_ILACE__INDEX);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH3__INDEX);
   wr_cio_state(dev, head, regp, NV_CIO_CRE_SCRATCH4__INDEX);
-  if (drm->device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
+  if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_CELSIUS) {
     wr_cio_state(dev, head, regp, NV_CIO_CRE_EBR_INDEX);
     wr_cio_state(dev, head, regp, NV_CIO_CRE_CSB);
     wr_cio_state(dev, head, regp, NV_CIO_CRE_4B);
     wr_cio_state(dev, head, regp, NV_CIO_CRE_TVOUT_LATENCY);
   }
   /* NV11 and NV20 stop at 0x52. */
   if (nv_gf4_disp_arch(dev)) {
-    if (drm->device.info.family < NV_DEVICE_INFO_V0_KELVIN) {
+    if (drm->client.device.info.family < NV_DEVICE_INFO_V0_KELVIN) {
       /* Not waiting for vertical retrace before modifying
          CRE_53/CRE_54 causes lockups. */
-      nvif_msec(&drm->device, 650, if ((nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) break;);
-      nvif_msec(&drm->device, 650, if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) break;);
+      nvif_msec(&drm->client.device, 650, if ((nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) break;);
+      nvif_msec(&drm->client.device, 650, if (!(nvif_rd32(device, NV_PRMCIO_INP0__COLOR) & 8)) break;);
     }
     wr_cio_state(dev, head, regp, NV_CIO_CRE_42);
     wr_cio_state(dev, head, regp, NV_CIO_CRE_53);
     wr_cio_state(dev, head, regp, NV_CIO_CRE_54);
     for (i = 0; i < 0x10; i++)
       NVWriteVgaCrtc5758(dev, head, i, regp->CR58[i]);
     wr_cio_state(dev, head, regp, NV_CIO_CRE_59);
     wr_cio_state(dev, head, regp, NV_CIO_CRE_5B);
     wr_cio_state(dev, head, regp, NV_CIO_CRE_85);
     wr_cio_state(dev, head, regp, NV_CIO_CRE_86);
   }
   NVWriteCRTC(dev, head, NV_PCRTC_START, regp->fb_start);
 }<sep>@@
struct nouveau_drm *drm;
@@
- drm->device
+ drm->client.device