imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,32 +1,32 @@
 static int nuc900_nand_probe(struct platform_device *pdev) {
   struct nuc900_nand *nuc900_nand;
   struct nand_chip *chip;
   struct mtd_info *mtd;
   struct resource *res;
   nuc900_nand = devm_kzalloc(&pdev->dev, sizeof(struct nuc900_nand), GFP_KERNEL);
   if (!nuc900_nand) return -ENOMEM;
   chip = &(nuc900_nand->chip);
   mtd = nand_to_mtd(chip);
   mtd->dev.parent = &pdev->dev;
   spin_lock_init(&nuc900_nand->lock);
   nuc900_nand->clk = devm_clk_get(&pdev->dev, NULL);
   if (IS_ERR(nuc900_nand->clk)) return -ENOENT;
   clk_enable(nuc900_nand->clk);
-  chip->cmdfunc = nuc900_nand_command_lp;
+  chip->legacy.cmdfunc = nuc900_nand_command_lp;
   chip->dev_ready = nuc900_nand_devready;
   chip->legacy.read_byte = nuc900_nand_read_byte;
   chip->legacy.write_buf = nuc900_nand_write_buf;
   chip->legacy.read_buf = nuc900_nand_read_buf;
   chip->chip_delay = 50;
   chip->options = 0;
   chip->ecc.mode = NAND_ECC_SOFT;
   chip->ecc.algo = NAND_ECC_HAMMING;
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   nuc900_nand->reg = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(nuc900_nand->reg)) return PTR_ERR(nuc900_nand->reg);
   nuc900_nand_enable(nuc900_nand);
   if (nand_scan(chip, 1)) return -ENXIO;
   mtd_device_register(mtd, partitions, ARRAY_SIZE(partitions));
   platform_set_drvdata(pdev, nuc900_nand);
   return 0;
 }<sep>@@
expression chip; 
@@
- chip->cmdfunc
+ chip->legacy.cmdfunc
--- initial
+++ final
@@ -1,21 +1,21 @@
 static void nv17_tv_commit(struct drm_encoder *encoder) {
   struct drm_device *dev = encoder->dev;
   struct nouveau_drm *drm = nouveau_drm(dev);
   struct nouveau_crtc *nv_crtc = nouveau_crtc(encoder->crtc);
   struct nouveau_encoder *nv_encoder = nouveau_encoder(encoder);
   const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
   if (get_tv_norm(encoder)->kind == TV_ENC_MODE) {
     nv17_tv_update_rescaler(encoder);
     nv17_tv_update_properties(encoder);
   } else {
     nv17_ctv_update_rescaler(encoder);
   }
   nv17_tv_state_load(dev, &to_tv_enc(encoder)->state);
   /* This could use refinement for flatpanels, but it should work */
-  if (drm->device.info.chipset < 0x44)
+  if (drm->client.device.info.chipset < 0x44)
     NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0xf0000000);
   else
     NVWriteRAMDAC(dev, 0, NV_PRAMDAC_TEST_CONTROL + nv04_dac_output_offset(encoder), 0x00100000);
   helper->dpms(encoder, DRM_MODE_DPMS_ON);
   NV_INFO(drm, "Output %s is running on CRTC %d using output %c\n", nouveau_encoder_connector_get(nv_encoder)->base.name, nv_crtc->index, '@' + ffs(nv_encoder->dcb->or));
 }<sep>@@
struct nouveau_drm *drm;
@@
- drm->device
+ drm->client.device
--- initial
+++ final
@@ -1,42 +1,42 @@
 static int qcom_nand_host_init_and_register(struct qcom_nand_controller *nandc, struct qcom_nand_host *host, struct device_node *dn) {
   struct nand_chip *chip = &host->chip;
   struct mtd_info *mtd = nand_to_mtd(chip);
   struct device *dev = nandc->dev;
   int ret;
   ret = of_property_read_u32(dn, "reg", &host->cs);
   if (ret) {
     dev_err(dev, "can't get chip-select\n");
     return -ENXIO;
   }
   nand_set_flash_node(chip, dn);
   mtd->name = devm_kasprintf(dev, GFP_KERNEL, "qcom_nand.%d", host->cs);
   if (!mtd->name) return -ENOMEM;
   mtd->owner = THIS_MODULE;
   mtd->dev.parent = dev;
-  chip->cmdfunc = qcom_nandc_command;
+  chip->legacy.cmdfunc = qcom_nandc_command;
   chip->select_chip = qcom_nandc_select_chip;
   chip->legacy.read_byte = qcom_nandc_read_byte;
   chip->legacy.read_buf = qcom_nandc_read_buf;
   chip->legacy.write_buf = qcom_nandc_write_buf;
   chip->set_features = nand_get_set_features_notsupp;
   chip->get_features = nand_get_set_features_notsupp;
   /*
    * the bad block marker is readable only when we read the last codeword
    * of a page with ECC disabled. currently, the nand_base and nand_bbt
    * helpers don't allow us to read BB from a nand chip with ECC
    * disabled (MTD_OPS_PLACE_OOB is set by default). use the block_bad
    * and block_markbad helpers until we permanently switch to using
    * MTD_OPS_RAW for all drivers (with the help of badblockbits)
    */
   chip->block_bad = qcom_nandc_block_bad;
   chip->block_markbad = qcom_nandc_block_markbad;
   chip->controller = &nandc->controller;
   chip->options |= NAND_NO_SUBPAGE_WRITE | NAND_USE_BOUNCE_BUFFER | NAND_SKIP_BBTSCAN;
   /* set up initial status value */
   host->status = NAND_STATUS_READY | NAND_STATUS_WP;
   ret = nand_scan(chip, 1);
   if (ret) return ret;
   ret = mtd_device_register(mtd, NULL, 0);
   if (ret) nand_cleanup(chip);
   return ret;
 }<sep>@@
expression chip; 
@@
- chip->cmdfunc
+ chip->legacy.cmdfunc
--- initial
+++ final
@@ -1,27 +1,27 @@
 int nand_change_write_column_op(struct nand_chip *chip, unsigned int offset_in_page, const void *buf, unsigned int len, bool force_8bit) {
   struct mtd_info *mtd = nand_to_mtd(chip);
   if (len && !buf) return -EINVAL;
   if (offset_in_page + len > mtd->writesize + mtd->oobsize) return -EINVAL;
   /* Small page NANDs do not support column change. */
   if (mtd->writesize <= 512) return -ENOTSUPP;
   if (chip->exec_op) {
     const struct nand_sdr_timings *sdr = nand_get_sdr_timings(&chip->data_interface);
     u8 addrs[2];
     struct nand_op_instr instrs[] = {
         NAND_OP_CMD(NAND_CMD_RNDIN, 0),
         NAND_OP_ADDR(2, addrs, PSEC_TO_NSEC(sdr->tCCS_min)),
         NAND_OP_DATA_OUT(len, buf, 0),
     };
     struct nand_operation op = NAND_OPERATION(instrs);
     int ret;
     ret = nand_fill_column_cycles(chip, addrs, offset_in_page);
     if (ret < 0) return ret;
     instrs[2].ctx.data.force_8bit = force_8bit;
     /* Drop the DATA_OUT instruction if len is set to 0. */
     if (!len) op.ninstrs--;
     return nand_exec_op(chip, &op);
   }
-  chip->cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1);
+  chip->legacy.cmdfunc(chip, NAND_CMD_RNDIN, offset_in_page, -1);
   if (len) chip->legacy.write_buf(chip, buf, len);
   return 0;
 }<sep>@@
expression chip; 
@@
- chip->cmdfunc
+ chip->legacy.cmdfunc
--- initial
+++ final
@@ -1,6 +1,6 @@
 static ssize_t nouveau_hwmon_critical_temp_hyst(struct device *d, struct device_attribute *a, char *buf) {
   struct drm_device *dev = dev_get_drvdata(d);
   struct nouveau_drm *drm = nouveau_drm(dev);
-  struct nvkm_therm *therm = nvxx_therm(&drm->device);
+  struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
   return snprintf(buf, PAGE_SIZE, "%d\n", therm->attr_get(therm, NVKM_THERM_ATTR_THRS_CRITICAL_HYST) * 1000);
 }<sep>@@
struct nouveau_drm *drm;
@@
- drm->device
+ drm->client.device
--- initial
+++ final
@@ -1,18 +1,18 @@
 static void nv04_dfp_update_backlight(struct drm_encoder *encoder, int mode) {
 #ifdef __powerpc__
   struct drm_device *dev = encoder->dev;
-  struct nvif_object *device = &nouveau_drm(dev)->device.object;
+  struct nvif_object *device = &nouveau_drm(dev)->client.device.object;
   /* BIOS scripts usually take care of the backlight, thanks
    * Apple for your consistency.
    */
   if (dev->pdev->device == 0x0174 || dev->pdev->device == 0x0179 || dev->pdev->device == 0x0189 || dev->pdev->device == 0x0329) {
     if (mode == DRM_MODE_DPMS_ON) {
       nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 1 << 31);
       nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 1);
     } else {
       nvif_mask(device, NV_PBUS_DEBUG_DUALHEAD_CTL, 1 << 31, 0);
       nvif_mask(device, NV_PCRTC_GPIO_EXT, 3, 0);
     }
   }
 #endif
 }<sep>@@
expression dev;
@@

-       nouveau_drm(dev)->device
+       nouveau_drm(dev)->client.device
--- initial
+++ final
@@ -1,25 +1,25 @@
 static void nand_set_defaults(struct nand_chip *chip) {
   unsigned int busw = chip->options & NAND_BUSWIDTH_16;
   /* check for proper chip_delay setup, set 20us if not */
   if (!chip->chip_delay) chip->chip_delay = 20;
   /* check, if a user supplied command function given */
-  if (!chip->cmdfunc && !chip->exec_op) chip->cmdfunc = nand_command;
+  if (!chip->legacy.cmdfunc && !chip->exec_op) chip->legacy.cmdfunc = nand_command;
   /* check, if a user supplied wait function given */
   if (chip->waitfunc == NULL) chip->waitfunc = nand_wait;
   if (!chip->select_chip) chip->select_chip = nand_select_chip;
   /* set for ONFI nand */
   if (!chip->set_features) chip->set_features = nand_default_set_features;
   if (!chip->get_features) chip->get_features = nand_default_get_features;
   /* If called twice, pointers that depend on busw may need to be reset */
   if (!chip->legacy.read_byte || chip->legacy.read_byte == nand_read_byte) chip->legacy.read_byte = busw ? nand_read_byte16 : nand_read_byte;
   if (!chip->block_bad) chip->block_bad = nand_block_bad;
   if (!chip->block_markbad) chip->block_markbad = nand_default_block_markbad;
   if (!chip->legacy.write_buf || chip->legacy.write_buf == nand_write_buf) chip->legacy.write_buf = busw ? nand_write_buf16 : nand_write_buf;
   if (!chip->legacy.write_byte || chip->legacy.write_byte == nand_write_byte) chip->legacy.write_byte = busw ? nand_write_byte16 : nand_write_byte;
   if (!chip->legacy.read_buf || chip->legacy.read_buf == nand_read_buf) chip->legacy.read_buf = busw ? nand_read_buf16 : nand_read_buf;
   if (!chip->controller) {
     chip->controller = &chip->dummy_controller;
     nand_controller_init(chip->controller);
   }
   if (!chip->buf_align) chip->buf_align = 1;
 }<sep>@@
expression chip; 
@@
- chip->cmdfunc
+ chip->legacy.cmdfunc
--- initial
+++ final
@@ -1,43 +1,43 @@
 int nouveau_abi16_ioctl_getparam(ABI16_IOCTL_ARGS) {
   struct nouveau_cli *cli = nouveau_cli(file_priv);
   struct nouveau_drm *drm = nouveau_drm(dev);
-  struct nvif_device *device = &drm->device;
+  struct nvif_device *device = &drm->client.device;
   struct nvkm_gr *gr = nvxx_gr(device);
   struct drm_nouveau_getparam *getparam = data;
   switch (getparam->param) {
   case NOUVEAU_GETPARAM_CHIPSET_ID: getparam->value = device->info.chipset; break;
   case NOUVEAU_GETPARAM_PCI_VENDOR:
     if (nvxx_device(device)->func->pci)
       getparam->value = dev->pdev->vendor;
     else
       getparam->value = 0;
     break;
   case NOUVEAU_GETPARAM_PCI_DEVICE:
     if (nvxx_device(device)->func->pci)
       getparam->value = dev->pdev->device;
     else
       getparam->value = 0;
     break;
   case NOUVEAU_GETPARAM_BUS_TYPE:
     if (!nvxx_device(device)->func->pci)
       getparam->value = 3;
     else if (pci_find_capability(dev->pdev, PCI_CAP_ID_AGP))
       getparam->value = 0;
     else if (!pci_is_pcie(dev->pdev))
       getparam->value = 1;
     else
       getparam->value = 2;
     break;
   case NOUVEAU_GETPARAM_FB_SIZE: getparam->value = drm->gem.vram_available; break;
   case NOUVEAU_GETPARAM_AGP_SIZE: getparam->value = drm->gem.gart_available; break;
   case NOUVEAU_GETPARAM_VM_VRAM_BASE:
     getparam->value = 0; /* deprecated */
     break;
   case NOUVEAU_GETPARAM_PTIMER_TIME: getparam->value = nvif_device_time(device); break;
   case NOUVEAU_GETPARAM_HAS_BO_USAGE: getparam->value = 1; break;
   case NOUVEAU_GETPARAM_HAS_PAGEFLIP: getparam->value = 1; break;
   case NOUVEAU_GETPARAM_GRAPH_UNITS: getparam->value = nvkm_gr_units(gr); break;
   default: NV_PRINTK(dbg, cli, "unknown parameter %lld\n", getparam->param); return -EINVAL;
   }
   return 0;
 }<sep>@@
struct nouveau_drm *drm;
@@
- drm->device
+ drm->client.device
--- initial
+++ final
@@ -1,11 +1,11 @@
 static bool nouveau_bios_posted(struct drm_device *dev) {
   struct nouveau_drm *drm = nouveau_drm(dev);
   unsigned htotal;
-  if (drm->device.info.family >= NV_DEVICE_INFO_V0_TESLA) return true;
+  if (drm->client.device.info.family >= NV_DEVICE_INFO_V0_TESLA) return true;
   htotal = NVReadVgaCrtc(dev, 0, 0x06);
   htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x01) << 8;
   htotal |= (NVReadVgaCrtc(dev, 0, 0x07) & 0x20) << 4;
   htotal |= (NVReadVgaCrtc(dev, 0, 0x25) & 0x01) << 10;
   htotal |= (NVReadVgaCrtc(dev, 0, 0x41) & 0x01) << 11;
   return (htotal != 0);
 }<sep>@@
struct nouveau_drm *drm;
@@
- drm->device
+ drm->client.device
--- initial
+++ final
@@ -1,30 +1,30 @@
 static void nouveau_ttm_tt_unpopulate(struct ttm_tt *ttm) {
   struct ttm_dma_tt *ttm_dma = (void *)ttm;
   struct nouveau_drm *drm;
   struct nvkm_device *device;
   struct drm_device *dev;
   struct device *pdev;
   unsigned i;
   bool slave = !!(ttm->page_flags & TTM_PAGE_FLAG_SG);
   if (slave) return;
   drm = nouveau_bdev(ttm->bdev);
-  device = nvxx_device(&drm->device);
+  device = nvxx_device(&drm->client.device);
   dev = drm->dev;
   pdev = device->dev;
 #if IS_ENABLED(CONFIG_AGP)
   if (drm->agp.bridge) {
     ttm_agp_tt_unpopulate(ttm);
     return;
   }
 #endif
 #if IS_ENABLED(CONFIG_SWIOTLB) && IS_ENABLED(CONFIG_X86)
   if (swiotlb_nr_tbl()) {
     ttm_dma_unpopulate((void *)ttm, dev->dev);
     return;
   }
 #endif
   for (i = 0; i < ttm->num_pages; i++) {
     if (ttm_dma->dma_address[i]) { dma_unmap_page(pdev, ttm_dma->dma_address[i], PAGE_SIZE, DMA_BIDIRECTIONAL); }
   }
   ttm_pool_unpopulate(ttm);
 }<sep>@@
struct nouveau_drm *drm;
@@
- drm->device
+ drm->client.device
--- initial
+++ final
@@ -1,52 +1,52 @@
 static int spinand_probe(struct spi_device *spi_nand) {
   struct mtd_info *mtd;
   struct nand_chip *chip;
   struct spinand_info *info;
   struct spinand_state *state;
   info = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info), GFP_KERNEL);
   if (!info) return -ENOMEM;
   info->spi = spi_nand;
   spinand_lock_block(spi_nand, BL_ALL_UNLOCKED);
   state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state), GFP_KERNEL);
   if (!state) return -ENOMEM;
   info->priv = state;
   state->buf_ptr = 0;
   state->buf = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL);
   if (!state->buf) return -ENOMEM;
   chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip), GFP_KERNEL);
   if (!chip) return -ENOMEM;
 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
   chip->ecc.mode = NAND_ECC_HW;
   chip->ecc.size = 0x200;
   chip->ecc.bytes = 0x6;
   chip->ecc.steps = 0x4;
   chip->ecc.strength = 1;
   chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
   chip->ecc.read_page = spinand_read_page_hwecc;
   chip->ecc.write_page = spinand_write_page_hwecc;
 #else
   chip->ecc.mode = NAND_ECC_SOFT;
   chip->ecc.algo = NAND_ECC_HAMMING;
   if (spinand_disable_ecc(spi_nand) < 0) dev_info(&spi_nand->dev, "%s: disable ecc failed!\n", __func__);
 #endif
   nand_set_flash_node(chip, spi_nand->dev.of_node);
   nand_set_controller_data(chip, info);
   chip->legacy.read_buf = spinand_read_buf;
   chip->legacy.write_buf = spinand_write_buf;
   chip->legacy.read_byte = spinand_read_byte;
-  chip->cmdfunc = spinand_cmdfunc;
+  chip->legacy.cmdfunc = spinand_cmdfunc;
   chip->waitfunc = spinand_wait;
   chip->options |= NAND_CACHEPRG;
   chip->select_chip = spinand_select_chip;
   chip->set_features = nand_get_set_features_notsupp;
   chip->get_features = nand_get_set_features_notsupp;
   mtd = nand_to_mtd(chip);
   dev_set_drvdata(&spi_nand->dev, mtd);
   mtd->dev.parent = &spi_nand->dev;
   mtd->oobsize = 64;
 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
   mtd_set_ooblayout(mtd, &spinand_oob_64_ops);
 #endif
   if (nand_scan(chip, 1)) return -ENXIO;
   return mtd_device_register(mtd, NULL, 0);
 }<sep>@@
expression chip; 
@@
- chip->cmdfunc
+ chip->legacy.cmdfunc
--- initial
+++ final
@@ -1,9 +1,9 @@
 static ssize_t nouveau_hwmon_set_critical_temp_hyst(struct device *d, struct device_attribute *a, const char *buf, size_t count) {
   struct drm_device *dev = dev_get_drvdata(d);
   struct nouveau_drm *drm = nouveau_drm(dev);
-  struct nvkm_therm *therm = nvxx_therm(&drm->device);
+  struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
   long value;
   if (kstrtol(buf, 10, &value) == -EINVAL) return count;
   therm->attr_set(therm, NVKM_THERM_ATTR_THRS_CRITICAL_HYST, value / 1000);
   return count;
 }<sep>@@
struct nouveau_drm *drm;
@@
- drm->device
+ drm->client.device
--- initial
+++ final
@@ -1,20 +1,20 @@
 static void nouveau_fbcon_imageblit(struct fb_info *info, const struct fb_image *image) {
   struct nouveau_fbdev *fbcon = info->par;
   struct nouveau_drm *drm = nouveau_drm(fbcon->helper.dev);
-  struct nvif_device *device = &drm->device;
+  struct nvif_device *device = &drm->client.device;
   int ret;
   if (info->state != FBINFO_STATE_RUNNING) return;
   ret = -ENODEV;
   if (!in_interrupt() && !(info->flags & FBINFO_HWACCEL_DISABLED) && mutex_trylock(&drm->client.mutex)) {
     if (device->info.family < NV_DEVICE_INFO_V0_TESLA)
       ret = nv04_fbcon_imageblit(info, image);
     else if (device->info.family < NV_DEVICE_INFO_V0_FERMI)
       ret = nv50_fbcon_imageblit(info, image);
     else
       ret = nvc0_fbcon_imageblit(info, image);
     mutex_unlock(&drm->client.mutex);
   }
   if (ret == 0) return;
   if (ret != -ENODEV) nouveau_fbcon_gpu_lockup(info);
   drm_fb_helper_cfb_imageblit(info, image);
 }<sep>@@
struct nouveau_drm *drm;
@@
- drm->device
+ drm->client.device
--- initial
+++ final
@@ -1,13 +1,13 @@
 void nv04_display_destroy(struct drm_device *dev) {
   struct nv04_display *disp = nv04_display(dev);
   struct nouveau_drm *drm = nouveau_drm(dev);
   struct nouveau_encoder *encoder;
   struct nouveau_crtc *nv_crtc;
   /* Restore state */
   list_for_each_entry(encoder, &dev->mode_config.encoder_list, base.base.head) encoder->enc_restore(&encoder->base.base);
   list_for_each_entry(nv_crtc, &dev->mode_config.crtc_list, base.head) nv_crtc->restore(&nv_crtc->base);
   nouveau_hw_save_vga_fonts(dev, 0);
   nouveau_display(dev)->priv = NULL;
   kfree(disp);
-  nvif_object_unmap(&drm->device.object);
+  nvif_object_unmap(&drm->client.device.object);
 }<sep>@@
struct nouveau_drm *drm;
@@
- drm->device
+ drm->client.device
--- initial
+++ final
@@ -1,12 +1,12 @@
 static void fun_select_chip(struct nand_chip *chip, int mchip_nr) {
   struct fsl_upm_nand *fun = to_fsl_upm_nand(nand_to_mtd(chip));
   if (mchip_nr == -1) {
-    chip->cmd_ctrl(chip, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
+    chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
   } else if (mchip_nr >= 0 && mchip_nr < NAND_MAX_CHIPS) {
     fun->mchip_number = mchip_nr;
     chip->legacy.IO_ADDR_R = fun->io_base + fun->mchip_offsets[mchip_nr];
     chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
   } else {
     BUG();
   }
 }<sep>@@
expression chip; 
@@
- chip->cmd_ctrl
+ chip->legacy.cmd_ctrl
--- initial
+++ final
@@ -1,35 +1,35 @@
 static void nv17_tv_prepare(struct drm_encoder *encoder) {
   struct drm_device *dev = encoder->dev;
   struct nouveau_drm *drm = nouveau_drm(dev);
   const struct drm_encoder_helper_funcs *helper = encoder->helper_private;
   struct nv17_tv_norm_params *tv_norm = get_tv_norm(encoder);
   int head = nouveau_crtc(encoder->crtc)->index;
   uint8_t *cr_lcd = &nv04_display(dev)->mode_reg.crtc_reg[head].CRTC[NV_CIO_CRE_LCD__INDEX];
   uint32_t dacclk_off = NV_PRAMDAC_DACCLK + nv04_dac_output_offset(encoder);
   uint32_t dacclk;
   helper->dpms(encoder, DRM_MODE_DPMS_OFF);
   nv04_dfp_disable(dev, head);
   /* Unbind any FP encoders from this head if we need the FP
    * stuff enabled. */
   if (tv_norm->kind == CTV_ENC_MODE) {
     struct drm_encoder *enc;
     list_for_each_entry(enc, &dev->mode_config.encoder_list, head) {
       struct dcb_output *dcb = nouveau_encoder(enc)->dcb;
       if ((dcb->type == DCB_OUTPUT_TMDS || dcb->type == DCB_OUTPUT_LVDS) && !enc->crtc && nv04_dfp_get_bound_head(dev, dcb) == head) { nv04_dfp_bind_head(dev, dcb, head ^ 1, drm->vbios.fp.dual_link); }
     }
   }
   if (tv_norm->kind == CTV_ENC_MODE) *cr_lcd |= 0x1 | (head ? 0x0 : 0x8);
   /* Set the DACCLK register */
   dacclk = (NVReadRAMDAC(dev, 0, dacclk_off) & ~0x30) | 0x1;
-  if (drm->device.info.family == NV_DEVICE_INFO_V0_CURIE) dacclk |= 0x1a << 16;
+  if (drm->client.device.info.family == NV_DEVICE_INFO_V0_CURIE) dacclk |= 0x1a << 16;
   if (tv_norm->kind == CTV_ENC_MODE) {
     dacclk |= 0x20;
     if (head)
       dacclk |= 0x100;
     else
       dacclk &= ~0x100;
   } else {
     dacclk |= 0x10;
   }
   NVWriteRAMDAC(dev, 0, dacclk_off, dacclk);
 }<sep>@@
struct nouveau_drm *drm;
@@
- drm->device
+ drm->client.device
--- initial
+++ final
@@ -1,9 +1,9 @@
 static ssize_t nouveau_hwmon_get_pwm1_min(struct device *d, struct device_attribute *a, char *buf) {
   struct drm_device *dev = dev_get_drvdata(d);
   struct nouveau_drm *drm = nouveau_drm(dev);
-  struct nvkm_therm *therm = nvxx_therm(&drm->device);
+  struct nvkm_therm *therm = nvxx_therm(&drm->client.device);
   int ret;
   ret = therm->attr_get(therm, NVKM_THERM_ATTR_FAN_MIN_DUTY);
   if (ret < 0) return ret;
   return sprintf(buf, "%i\n", ret);
 }<sep>@@
struct nouveau_drm *drm;
@@
- drm->device
+ drm->client.device
--- initial
+++ final
@@ -1,9 +1,9 @@
 int nand_read_oob_op(struct nand_chip *chip, unsigned int page, unsigned int offset_in_oob, void *buf, unsigned int len) {
   struct mtd_info *mtd = nand_to_mtd(chip);
   if (len && !buf) return -EINVAL;
   if (offset_in_oob + len > mtd->oobsize) return -EINVAL;
   if (chip->exec_op) return nand_read_page_op(chip, page, mtd->writesize + offset_in_oob, buf, len);
-  chip->cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page);
+  chip->legacy.cmdfunc(chip, NAND_CMD_READOOB, offset_in_oob, page);
   if (len) chip->legacy.read_buf(chip, buf, len);
   return 0;
 }<sep>@@
expression chip; 
@@
- chip->cmdfunc
+ chip->legacy.cmdfunc
--- initial
+++ final
@@ -1,58 +1,58 @@
 static int jz4780_nand_init_chip(struct platform_device *pdev, struct jz4780_nand_controller *nfc, struct device_node *np, unsigned int chipnr) {
   struct device *dev = &pdev->dev;
   struct jz4780_nand_chip *nand;
   struct jz4780_nand_cs *cs;
   struct resource *res;
   struct nand_chip *chip;
   struct mtd_info *mtd;
   const __be32 *reg;
   int ret = 0;
   cs = &nfc->cs[chipnr];
   reg = of_get_property(np, "reg", NULL);
   if (!reg) return -EINVAL;
   cs->bank = be32_to_cpu(*reg);
   jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
   res = platform_get_resource(pdev, IORESOURCE_MEM, chipnr);
   cs->base = devm_ioremap_resource(dev, res);
   if (IS_ERR(cs->base)) return PTR_ERR(cs->base);
   nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
   if (!nand) return -ENOMEM;
   nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
   if (IS_ERR(nand->busy_gpio)) {
     ret = PTR_ERR(nand->busy_gpio);
     dev_err(dev, "failed to request busy GPIO: %d\n", ret);
     return ret;
   } else if (nand->busy_gpio) {
     nand->chip.dev_ready = jz4780_nand_dev_ready;
   }
   nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
   if (IS_ERR(nand->wp_gpio)) {
     ret = PTR_ERR(nand->wp_gpio);
     dev_err(dev, "failed to request WP GPIO: %d\n", ret);
     return ret;
   }
   chip = &nand->chip;
   mtd = nand_to_mtd(chip);
   mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), cs->bank);
   if (!mtd->name) return -ENOMEM;
   mtd->dev.parent = dev;
   chip->legacy.IO_ADDR_R = cs->base + OFFSET_DATA;
   chip->legacy.IO_ADDR_W = cs->base + OFFSET_DATA;
   chip->chip_delay = RB_DELAY_US;
   chip->options = NAND_NO_SUBPAGE_WRITE;
   chip->select_chip = jz4780_nand_select_chip;
-  chip->cmd_ctrl = jz4780_nand_cmd_ctrl;
+  chip->legacy.cmd_ctrl = jz4780_nand_cmd_ctrl;
   chip->ecc.mode = NAND_ECC_HW;
   chip->controller = &nfc->controller;
   nand_set_flash_node(chip, np);
   chip->controller->ops = &jz4780_nand_controller_ops;
   ret = nand_scan(chip, 1);
   if (ret) return ret;
   ret = mtd_device_register(mtd, NULL, 0);
   if (ret) {
     nand_release(chip);
     return ret;
   }
   list_add_tail(&nand->chip_list, &nfc->chips);
   return 0;
 }<sep>@@
expression chip; 
@@
- chip->cmd_ctrl
+ chip->legacy.cmd_ctrl