imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,59 +1,59 @@
 static int __init cs553x_init_one(int cs, int mmio, unsigned long adr) {
   int err = 0;
   struct nand_chip *this;
   struct mtd_info *new_mtd;
   pr_notice("Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio ? "MM" : "P", adr);
   if (!mmio) {
     pr_notice("PIO mode not yet implemented for CS553X NAND controller\n");
     return -ENXIO;
   }
   /* Allocate memory for MTD device structure and private data */
   this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
   if (!this) {
     err = -ENOMEM;
     goto out;
   }
   new_mtd = nand_to_mtd(this);
   /* Link the private data with the MTD structure */
   new_mtd->owner = THIS_MODULE;
   /* map physical address */
   this->legacy.IO_ADDR_R = this->legacy.IO_ADDR_W = ioremap(adr, 4096);
   if (!this->legacy.IO_ADDR_R) {
     pr_warn("ioremap cs553x NAND @0x%08lx failed\n", adr);
     err = -EIO;
     goto out_mtd;
   }
   this->legacy.cmd_ctrl = cs553x_hwcontrol;
   this->legacy.dev_ready = cs553x_device_ready;
   this->legacy.read_byte = cs553x_read_byte;
   this->legacy.read_buf = cs553x_read_buf;
   this->legacy.write_buf = cs553x_write_buf;
-  this->chip_delay = 0;
+  this->legacy.chip_delay = 0;
   this->ecc.mode = NAND_ECC_HW;
   this->ecc.size = 256;
   this->ecc.bytes = 3;
   this->ecc.hwctl = cs_enable_hwecc;
   this->ecc.calculate = cs_calculate_ecc;
   this->ecc.correct = nand_correct_data;
   this->ecc.strength = 1;
   /* Enable the following for a flash based bad block table */
   this->bbt_options = NAND_BBT_USE_FLASH;
   new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs);
   if (!new_mtd->name) {
     err = -ENOMEM;
     goto out_ior;
   }
   /* Scan to find existence of the device */
   err = nand_scan(this, 1);
   if (err) goto out_free;
   cs553x_mtd[cs] = new_mtd;
   goto out;
 out_free:
   kfree(new_mtd->name);
 out_ior:
   iounmap(this->legacy.IO_ADDR_R);
 out_mtd:
   kfree(this);
 out:
   return err;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,42 +1,42 @@
 static int fsl_elbc_attach_chip(struct nand_chip *chip) {
   struct mtd_info *mtd = nand_to_mtd(chip);
   struct fsl_elbc_mtd *priv = nand_get_controller_data(chip);
   struct fsl_lbc_ctrl *ctrl = priv->ctrl;
   struct fsl_lbc_regs __iomem *lbc = ctrl->regs;
   unsigned int al;
   /* calculate FMR Address Length field */
   al = 0;
   if (chip->pagemask & 0xffff0000) al++;
   if (chip->pagemask & 0xff000000) al++;
   priv->fmr |= al << FMR_AL_SHIFT;
   dev_dbg(priv->dev, "fsl_elbc_init: nand->numchips = %d\n", chip->numchips);
   dev_dbg(priv->dev, "fsl_elbc_init: nand->chipsize = %lld\n", chip->chipsize);
   dev_dbg(priv->dev, "fsl_elbc_init: nand->pagemask = %8x\n", chip->pagemask);
-  dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n", chip->chip_delay);
+  dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_delay = %d\n", chip->legacy.chip_delay);
   dev_dbg(priv->dev, "fsl_elbc_init: nand->badblockpos = %d\n", chip->badblockpos);
   dev_dbg(priv->dev, "fsl_elbc_init: nand->chip_shift = %d\n", chip->chip_shift);
   dev_dbg(priv->dev, "fsl_elbc_init: nand->page_shift = %d\n", chip->page_shift);
   dev_dbg(priv->dev, "fsl_elbc_init: nand->phys_erase_shift = %d\n", chip->phys_erase_shift);
   dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.mode = %d\n", chip->ecc.mode);
   dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.steps = %d\n", chip->ecc.steps);
   dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.bytes = %d\n", chip->ecc.bytes);
   dev_dbg(priv->dev, "fsl_elbc_init: nand->ecc.total = %d\n", chip->ecc.total);
   dev_dbg(priv->dev, "fsl_elbc_init: mtd->ooblayout = %p\n", mtd->ooblayout);
   dev_dbg(priv->dev, "fsl_elbc_init: mtd->flags = %08x\n", mtd->flags);
   dev_dbg(priv->dev, "fsl_elbc_init: mtd->size = %lld\n", mtd->size);
   dev_dbg(priv->dev, "fsl_elbc_init: mtd->erasesize = %d\n", mtd->erasesize);
   dev_dbg(priv->dev, "fsl_elbc_init: mtd->writesize = %d\n", mtd->writesize);
   dev_dbg(priv->dev, "fsl_elbc_init: mtd->oobsize = %d\n", mtd->oobsize);
   /* adjust Option Register and ECC to match Flash page size */
   if (mtd->writesize == 512) {
     priv->page_size = 0;
     clrbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
   } else if (mtd->writesize == 2048) {
     priv->page_size = 1;
     setbits32(&lbc->bank[priv->bank].or, OR_FCM_PGS);
   } else {
     dev_err(priv->dev, "fsl_elbc_init: page size %d is not supported\n", mtd->writesize);
     return -ENOTSUPP;
   }
   return 0;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,23 +1,23 @@
 static int fsl_ifc_attach_chip(struct nand_chip *chip) {
   struct mtd_info *mtd = nand_to_mtd(chip);
   struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
   dev_dbg(priv->dev, "%s: nand->numchips = %d\n", __func__, chip->numchips);
   dev_dbg(priv->dev, "%s: nand->chipsize = %lld\n", __func__, chip->chipsize);
   dev_dbg(priv->dev, "%s: nand->pagemask = %8x\n", __func__, chip->pagemask);
-  dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__, chip->chip_delay);
+  dev_dbg(priv->dev, "%s: nand->chip_delay = %d\n", __func__, chip->legacy.chip_delay);
   dev_dbg(priv->dev, "%s: nand->badblockpos = %d\n", __func__, chip->badblockpos);
   dev_dbg(priv->dev, "%s: nand->chip_shift = %d\n", __func__, chip->chip_shift);
   dev_dbg(priv->dev, "%s: nand->page_shift = %d\n", __func__, chip->page_shift);
   dev_dbg(priv->dev, "%s: nand->phys_erase_shift = %d\n", __func__, chip->phys_erase_shift);
   dev_dbg(priv->dev, "%s: nand->ecc.mode = %d\n", __func__, chip->ecc.mode);
   dev_dbg(priv->dev, "%s: nand->ecc.steps = %d\n", __func__, chip->ecc.steps);
   dev_dbg(priv->dev, "%s: nand->ecc.bytes = %d\n", __func__, chip->ecc.bytes);
   dev_dbg(priv->dev, "%s: nand->ecc.total = %d\n", __func__, chip->ecc.total);
   dev_dbg(priv->dev, "%s: mtd->ooblayout = %p\n", __func__, mtd->ooblayout);
   dev_dbg(priv->dev, "%s: mtd->flags = %08x\n", __func__, mtd->flags);
   dev_dbg(priv->dev, "%s: mtd->size = %lld\n", __func__, mtd->size);
   dev_dbg(priv->dev, "%s: mtd->erasesize = %d\n", __func__, mtd->erasesize);
   dev_dbg(priv->dev, "%s: mtd->writesize = %d\n", __func__, mtd->writesize);
   dev_dbg(priv->dev, "%s: mtd->oobsize = %d\n", __func__, mtd->oobsize);
   return 0;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,70 +1,70 @@
 static int gpio_nand_probe(struct platform_device *pdev) {
   struct gpiomtd *gpiomtd;
   struct nand_chip *chip;
   struct mtd_info *mtd;
   struct resource *res;
   struct device *dev = &pdev->dev;
   int ret = 0;
   if (!dev->of_node && !dev_get_platdata(dev)) return -EINVAL;
   gpiomtd = devm_kzalloc(dev, sizeof(*gpiomtd), GFP_KERNEL);
   if (!gpiomtd) return -ENOMEM;
   chip = &gpiomtd->nand_chip;
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   chip->legacy.IO_ADDR_R = devm_ioremap_resource(dev, res);
   if (IS_ERR(chip->legacy.IO_ADDR_R)) return PTR_ERR(chip->legacy.IO_ADDR_R);
   res = gpio_nand_get_io_sync(pdev);
   if (res) {
     gpiomtd->io_sync = devm_ioremap_resource(dev, res);
     if (IS_ERR(gpiomtd->io_sync)) return PTR_ERR(gpiomtd->io_sync);
   }
   ret = gpio_nand_get_config(dev, &gpiomtd->plat);
   if (ret) return ret;
   /* Just enable the chip */
   gpiomtd->nce = devm_gpiod_get_optional(dev, "nce", GPIOD_OUT_HIGH);
   if (IS_ERR(gpiomtd->nce)) return PTR_ERR(gpiomtd->nce);
   /* We disable write protection once we know probe() will succeed */
   gpiomtd->nwp = devm_gpiod_get_optional(dev, "nwp", GPIOD_OUT_LOW);
   if (IS_ERR(gpiomtd->nwp)) {
     ret = PTR_ERR(gpiomtd->nwp);
     goto out_ce;
   }
   gpiomtd->ale = devm_gpiod_get(dev, "ale", GPIOD_OUT_LOW);
   if (IS_ERR(gpiomtd->ale)) {
     ret = PTR_ERR(gpiomtd->ale);
     goto out_ce;
   }
   gpiomtd->cle = devm_gpiod_get(dev, "cle", GPIOD_OUT_LOW);
   if (IS_ERR(gpiomtd->cle)) {
     ret = PTR_ERR(gpiomtd->cle);
     goto out_ce;
   }
   gpiomtd->rdy = devm_gpiod_get_optional(dev, "rdy", GPIOD_IN);
   if (IS_ERR(gpiomtd->rdy)) {
     ret = PTR_ERR(gpiomtd->rdy);
     goto out_ce;
   }
   /* Using RDY pin */
   if (gpiomtd->rdy) chip->legacy.dev_ready = gpio_nand_devready;
   nand_set_flash_node(chip, pdev->dev.of_node);
   chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
   chip->ecc.mode = NAND_ECC_SOFT;
   chip->ecc.algo = NAND_ECC_HAMMING;
   chip->options = gpiomtd->plat.options;
-  chip->chip_delay = gpiomtd->plat.chip_delay;
+  chip->legacy.chip_delay = gpiomtd->plat.chip_delay;
   chip->legacy.cmd_ctrl = gpio_nand_cmd_ctrl;
   mtd = nand_to_mtd(chip);
   mtd->dev.parent = dev;
   platform_set_drvdata(pdev, gpiomtd);
   /* Disable write protection, if wired up */
   if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp)) gpiod_direction_output(gpiomtd->nwp, 1);
   ret = nand_scan(chip, 1);
   if (ret) goto err_wp;
   if (gpiomtd->plat.adjust_parts) gpiomtd->plat.adjust_parts(&gpiomtd->plat, mtd->size);
   ret = mtd_device_register(mtd, gpiomtd->plat.parts, gpiomtd->plat.num_parts);
   if (!ret) return 0;
 err_wp:
   if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp)) gpiod_set_value(gpiomtd->nwp, 0);
 out_ce:
   if (gpiomtd->nce && !IS_ERR(gpiomtd->nce)) gpiod_set_value(gpiomtd->nce, 0);
   return ret;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,57 +1,57 @@
 static int hisi_nfc_probe(struct platform_device *pdev) {
   int ret = 0, irq, max_chips = HINFC504_MAX_CHIP;
   struct device *dev = &pdev->dev;
   struct hinfc_host *host;
   struct nand_chip *chip;
   struct mtd_info *mtd;
   struct resource *res;
   struct device_node *np = dev->of_node;
   host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
   if (!host) return -ENOMEM;
   host->dev = dev;
   platform_set_drvdata(pdev, host);
   chip = &host->chip;
   mtd = nand_to_mtd(chip);
   irq = platform_get_irq(pdev, 0);
   if (irq < 0) {
     dev_err(dev, "no IRQ resource defined\n");
     return -ENXIO;
   }
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   host->iobase = devm_ioremap_resource(dev, res);
   if (IS_ERR(host->iobase)) return PTR_ERR(host->iobase);
   res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
   host->mmio = devm_ioremap_resource(dev, res);
   if (IS_ERR(host->mmio)) {
     dev_err(dev, "devm_ioremap_resource[1] fail\n");
     return PTR_ERR(host->mmio);
   }
   mtd->name = "hisi_nand";
   mtd->dev.parent = &pdev->dev;
   nand_set_controller_data(chip, host);
   nand_set_flash_node(chip, np);
   chip->legacy.cmdfunc = hisi_nfc_cmdfunc;
   chip->select_chip = hisi_nfc_select_chip;
   chip->legacy.read_byte = hisi_nfc_read_byte;
   chip->legacy.write_buf = hisi_nfc_write_buf;
   chip->legacy.read_buf = hisi_nfc_read_buf;
-  chip->chip_delay = HINFC504_CHIP_DELAY;
+  chip->legacy.chip_delay = HINFC504_CHIP_DELAY;
   chip->legacy.set_features = nand_get_set_features_notsupp;
   chip->legacy.get_features = nand_get_set_features_notsupp;
   hisi_nfc_host_init(host);
   ret = devm_request_irq(dev, irq, hinfc_irq_handle, 0x0, "nandc", host);
   if (ret) {
     dev_err(dev, "failed to request IRQ\n");
     return ret;
   }
   chip->dummy_controller.ops = &hisi_nfc_controller_ops;
   ret = nand_scan(chip, max_chips);
   if (ret) return ret;
   ret = mtd_device_register(mtd, NULL, 0);
   if (ret) {
     dev_err(dev, "Err MTD partition=%d\n", ret);
     nand_cleanup(chip);
     return ret;
   }
   return 0;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,58 +1,58 @@
 static int jz4780_nand_init_chip(struct platform_device *pdev, struct jz4780_nand_controller *nfc, struct device_node *np, unsigned int chipnr) {
   struct device *dev = &pdev->dev;
   struct jz4780_nand_chip *nand;
   struct jz4780_nand_cs *cs;
   struct resource *res;
   struct nand_chip *chip;
   struct mtd_info *mtd;
   const __be32 *reg;
   int ret = 0;
   cs = &nfc->cs[chipnr];
   reg = of_get_property(np, "reg", NULL);
   if (!reg) return -EINVAL;
   cs->bank = be32_to_cpu(*reg);
   jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
   res = platform_get_resource(pdev, IORESOURCE_MEM, chipnr);
   cs->base = devm_ioremap_resource(dev, res);
   if (IS_ERR(cs->base)) return PTR_ERR(cs->base);
   nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
   if (!nand) return -ENOMEM;
   nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
   if (IS_ERR(nand->busy_gpio)) {
     ret = PTR_ERR(nand->busy_gpio);
     dev_err(dev, "failed to request busy GPIO: %d\n", ret);
     return ret;
   } else if (nand->busy_gpio) {
     nand->chip.legacy.dev_ready = jz4780_nand_dev_ready;
   }
   nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
   if (IS_ERR(nand->wp_gpio)) {
     ret = PTR_ERR(nand->wp_gpio);
     dev_err(dev, "failed to request WP GPIO: %d\n", ret);
     return ret;
   }
   chip = &nand->chip;
   mtd = nand_to_mtd(chip);
   mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), cs->bank);
   if (!mtd->name) return -ENOMEM;
   mtd->dev.parent = dev;
   chip->legacy.IO_ADDR_R = cs->base + OFFSET_DATA;
   chip->legacy.IO_ADDR_W = cs->base + OFFSET_DATA;
-  chip->chip_delay = RB_DELAY_US;
+  chip->legacy.chip_delay = RB_DELAY_US;
   chip->options = NAND_NO_SUBPAGE_WRITE;
   chip->select_chip = jz4780_nand_select_chip;
   chip->legacy.cmd_ctrl = jz4780_nand_cmd_ctrl;
   chip->ecc.mode = NAND_ECC_HW;
   chip->controller = &nfc->controller;
   nand_set_flash_node(chip, np);
   chip->controller->ops = &jz4780_nand_controller_ops;
   ret = nand_scan(chip, 1);
   if (ret) return ret;
   ret = mtd_device_register(mtd, NULL, 0);
   if (ret) {
     nand_release(chip);
     return ret;
   }
   list_add_tail(&nand->chip_list, &nfc->chips);
   return 0;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,22 +1,22 @@
 static void atmel_nand_init(struct atmel_nand_controller *nc, struct atmel_nand *nand) {
   struct nand_chip *chip = &nand->base;
   struct mtd_info *mtd = nand_to_mtd(chip);
   mtd->dev.parent = nc->dev;
   nand->base.controller = &nc->base;
   chip->legacy.cmd_ctrl = atmel_nand_cmd_ctrl;
   chip->legacy.read_byte = atmel_nand_read_byte;
   chip->legacy.write_byte = atmel_nand_write_byte;
   chip->legacy.read_buf = atmel_nand_read_buf;
   chip->legacy.write_buf = atmel_nand_write_buf;
   chip->select_chip = atmel_nand_select_chip;
   if (nc->mck && nc->caps->ops->setup_data_interface) chip->setup_data_interface = atmel_nand_setup_data_interface;
   /* Some NANDs require a longer delay than the default one (20us). */
-  chip->chip_delay = 40;
+  chip->legacy.chip_delay = 40;
   /*
    * Use a bounce buffer when the buffer passed by the MTD user is not
    * suitable for DMA.
    */
   if (nc->dmac) chip->options |= NAND_USE_BOUNCE_BUFFER;
   /* Default to HW ECC if pmecc is available. */
   if (nc->pmecc) chip->ecc.mode = NAND_ECC_HW;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,84 +1,84 @@
 static void nand_command(struct nand_chip *chip, unsigned int command, int column, int page_addr) {
   struct mtd_info *mtd = nand_to_mtd(chip);
   int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
   /* Write out the command to the device */
   if (command == NAND_CMD_SEQIN) {
     int readcmd;
     if (column >= mtd->writesize) {
       /* OOB area */
       column -= mtd->writesize;
       readcmd = NAND_CMD_READOOB;
     } else if (column < 256) {
       /* First 256 bytes --> READ0 */
       readcmd = NAND_CMD_READ0;
     } else {
       column -= 256;
       readcmd = NAND_CMD_READ1;
     }
     chip->legacy.cmd_ctrl(chip, readcmd, ctrl);
     ctrl &= ~NAND_CTRL_CHANGE;
   }
   if (command != NAND_CMD_NONE) chip->legacy.cmd_ctrl(chip, command, ctrl);
   /* Address cycle, when necessary */
   ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
   /* Serially input address */
   if (column != -1) {
     /* Adjust columns for 16 bit buswidth */
     if (chip->options & NAND_BUSWIDTH_16 && !nand_opcode_8bits(command)) column >>= 1;
     chip->legacy.cmd_ctrl(chip, column, ctrl);
     ctrl &= ~NAND_CTRL_CHANGE;
   }
   if (page_addr != -1) {
     chip->legacy.cmd_ctrl(chip, page_addr, ctrl);
     ctrl &= ~NAND_CTRL_CHANGE;
     chip->legacy.cmd_ctrl(chip, page_addr >> 8, ctrl);
     if (chip->options & NAND_ROW_ADDR_3) chip->legacy.cmd_ctrl(chip, page_addr >> 16, ctrl);
   }
   chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
   /*
    * Program and erase have their own busy handlers status and sequential
    * in needs no delay
    */
   switch (command) {
   case NAND_CMD_NONE:
   case NAND_CMD_PAGEPROG:
   case NAND_CMD_ERASE1:
   case NAND_CMD_ERASE2:
   case NAND_CMD_SEQIN:
   case NAND_CMD_STATUS:
   case NAND_CMD_READID:
   case NAND_CMD_SET_FEATURES: return;
   case NAND_CMD_RESET:
     if (chip->legacy.dev_ready) break;
-    udelay(chip->chip_delay);
+    udelay(chip->legacy.chip_delay);
     chip->legacy.cmd_ctrl(chip, NAND_CMD_STATUS, NAND_CTRL_CLE | NAND_CTRL_CHANGE);
     chip->legacy.cmd_ctrl(chip, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
     /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
     nand_wait_status_ready(mtd, 250);
     return;
     /* This applies to read commands */
   case NAND_CMD_READ0:
     /*
      * READ0 is sometimes used to exit GET STATUS mode. When this
      * is the case no address cycles are requested, and we can use
      * this information to detect that we should not wait for the
      * device to be ready.
      */
     if (column == -1 && page_addr == -1) return;
   default:
     /*
      * If we don't have access to the busy pin, we apply the given
      * command delay
      */
     if (!chip->legacy.dev_ready) {
-      udelay(chip->chip_delay);
+      udelay(chip->legacy.chip_delay);
       return;
     }
   }
   /*
    * Apply this short delay always to ensure that we do wait tWB in
    * any case on any machine.
    */
   ndelay(100);
   nand_wait_ready(chip);
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,20 +1,20 @@
 static void nand_set_defaults(struct nand_chip *chip) {
   unsigned int busw = chip->options & NAND_BUSWIDTH_16;
   /* check for proper chip_delay setup, set 20us if not */
-  if (!chip->chip_delay) chip->chip_delay = 20;
+  if (!chip->legacy.chip_delay) chip->legacy.chip_delay = 20;
   /* check, if a user supplied command function given */
   if (!chip->legacy.cmdfunc && !chip->exec_op) chip->legacy.cmdfunc = nand_command;
   /* check, if a user supplied wait function given */
   if (chip->legacy.waitfunc == NULL) chip->legacy.waitfunc = nand_wait;
   if (!chip->select_chip) chip->select_chip = nand_select_chip;
   /* If called twice, pointers that depend on busw may need to be reset */
   if (!chip->legacy.read_byte || chip->legacy.read_byte == nand_read_byte) chip->legacy.read_byte = busw ? nand_read_byte16 : nand_read_byte;
   if (!chip->legacy.write_buf || chip->legacy.write_buf == nand_write_buf) chip->legacy.write_buf = busw ? nand_write_buf16 : nand_write_buf;
   if (!chip->legacy.write_byte || chip->legacy.write_byte == nand_write_byte) chip->legacy.write_byte = busw ? nand_write_byte16 : nand_write_byte;
   if (!chip->legacy.read_buf || chip->legacy.read_buf == nand_read_buf) chip->legacy.read_buf = busw ? nand_read_buf16 : nand_read_buf;
   if (!chip->controller) {
     chip->controller = &chip->dummy_controller;
     nand_controller_init(chip->controller);
   }
   if (!chip->buf_align) chip->buf_align = 1;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,15 +1,15 @@
 static int nand_wait_rdy_op(struct nand_chip *chip, unsigned int timeout_ms, unsigned int delay_ns) {
   if (chip->exec_op) {
     struct nand_op_instr instrs[] = {
         NAND_OP_WAIT_RDY(PSEC_TO_MSEC(timeout_ms), PSEC_TO_NSEC(delay_ns)),
     };
     struct nand_operation op = NAND_OPERATION(instrs);
     return nand_exec_op(chip, &op);
   }
   /* Apply delay or wait for ready/busy pin */
   if (!chip->legacy.dev_ready)
-    udelay(chip->chip_delay);
+    udelay(chip->legacy.chip_delay);
   else
     nand_wait_ready(chip);
   return 0;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,39 +1,39 @@
 static int ndfc_chip_init(struct ndfc_controller *ndfc, struct device_node *node) {
   struct device_node *flash_np;
   struct nand_chip *chip = &ndfc->chip;
   struct mtd_info *mtd = nand_to_mtd(chip);
   int ret;
   chip->legacy.IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
   chip->legacy.IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
   chip->legacy.cmd_ctrl = ndfc_hwcontrol;
   chip->legacy.dev_ready = ndfc_ready;
   chip->select_chip = ndfc_select_chip;
-  chip->chip_delay = 50;
+  chip->legacy.chip_delay = 50;
   chip->controller = &ndfc->ndfc_control;
   chip->legacy.read_buf = ndfc_read_buf;
   chip->legacy.write_buf = ndfc_write_buf;
   chip->ecc.correct = nand_correct_data;
   chip->ecc.hwctl = ndfc_enable_hwecc;
   chip->ecc.calculate = ndfc_calculate_ecc;
   chip->ecc.mode = NAND_ECC_HW;
   chip->ecc.size = 256;
   chip->ecc.bytes = 3;
   chip->ecc.strength = 1;
   nand_set_controller_data(chip, ndfc);
   mtd->dev.parent = &ndfc->ofdev->dev;
   flash_np = of_get_next_child(node, NULL);
   if (!flash_np) return -ENODEV;
   nand_set_flash_node(chip, flash_np);
   mtd->name = kasprintf(GFP_KERNEL, "%s.%pOFn", dev_name(&ndfc->ofdev->dev), flash_np);
   if (!mtd->name) {
     ret = -ENOMEM;
     goto err;
   }
   ret = nand_scan(chip, 1);
   if (ret) goto err;
   ret = mtd_device_register(mtd, NULL, 0);
 err:
   of_node_put(flash_np);
   if (ret) kfree(mtd->name);
   return ret;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,54 +1,54 @@
 static void nuc900_nand_command_lp(struct nand_chip *chip, unsigned int command, int column, int page_addr) {
   struct mtd_info *mtd = nand_to_mtd(chip);
   struct nuc900_nand *nand = mtd_to_nuc900(mtd);
   if (command == NAND_CMD_READOOB) {
     column += mtd->writesize;
     command = NAND_CMD_READ0;
   }
   write_cmd_reg(nand, command & 0xff);
   if (column != -1 || page_addr != -1) {
     if (column != -1) {
       if (chip->options & NAND_BUSWIDTH_16 && !nand_opcode_8bits(command)) column >>= 1;
       write_addr_reg(nand, column);
       write_addr_reg(nand, column >> 8 | ENDADDR);
     }
     if (page_addr != -1) {
       write_addr_reg(nand, page_addr);
       if (chip->options & NAND_ROW_ADDR_3) {
         write_addr_reg(nand, page_addr >> 8);
         write_addr_reg(nand, page_addr >> 16 | ENDADDR);
       } else {
         write_addr_reg(nand, page_addr >> 8 | ENDADDR);
       }
     }
   }
   switch (command) {
   case NAND_CMD_CACHEDPROG:
   case NAND_CMD_PAGEPROG:
   case NAND_CMD_ERASE1:
   case NAND_CMD_ERASE2:
   case NAND_CMD_SEQIN:
   case NAND_CMD_RNDIN:
   case NAND_CMD_STATUS: return;
   case NAND_CMD_RESET:
     if (chip->legacy.dev_ready) break;
-    udelay(chip->chip_delay);
+    udelay(chip->legacy.chip_delay);
     write_cmd_reg(nand, NAND_CMD_STATUS);
     write_cmd_reg(nand, command);
     while (!nuc900_check_rb(nand))
       ;
     return;
   case NAND_CMD_RNDOUT: write_cmd_reg(nand, NAND_CMD_RNDOUTSTART); return;
   case NAND_CMD_READ0: write_cmd_reg(nand, NAND_CMD_READSTART);
   default:
     if (!chip->legacy.dev_ready) {
-      udelay(chip->chip_delay);
+      udelay(chip->legacy.chip_delay);
       return;
     }
   }
   /* Apply this short delay always to ensure that we do wait tWB in
    * any case on any machine. */
   ndelay(100);
   while (!chip->legacy.dev_ready(chip))
     ;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay