--- initial
+++ final
@@ -1,64 +1,64 @@
 static void vega10_didt_set_mask(struct pp_hwmgr *hwmgr, const bool enable) {
   uint32_t data;
   int result;
   uint32_t en = (enable ? 1 : 0);
   uint32_t didt_block_info = SQ_IR_MASK | TCP_IR_MASK | TD_PCC_MASK;
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) {
+  if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
     CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, DIDT_SQ_CTRL0, DIDT_CTRL_EN, en);
     didt_block_info &= ~SQ_Enable_MASK;
     didt_block_info |= en << SQ_Enable_SHIFT;
   }
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) {
+  if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
     CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, DIDT_DB_CTRL0, DIDT_CTRL_EN, en);
     didt_block_info &= ~DB_Enable_MASK;
     didt_block_info |= en << DB_Enable_SHIFT;
   }
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) {
+  if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
     CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, DIDT_TD_CTRL0, DIDT_CTRL_EN, en);
     didt_block_info &= ~TD_Enable_MASK;
     didt_block_info |= en << TD_Enable_SHIFT;
   }
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
+  if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
     CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, DIDT_TCP_CTRL0, DIDT_CTRL_EN, en);
     didt_block_info &= ~TCP_Enable_MASK;
     didt_block_info |= en << TCP_Enable_SHIFT;
   }
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) { CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, DIDT_DBR_CTRL0, DIDT_CTRL_EN, en); }
-  if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DiDtEDCEnable)) {
-    if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SQRamping)) {
+  if (PP_CAP(PHM_PlatformCaps_DBRRamping)) { CGS_WREG32_FIELD_IND(hwmgr->device, CGS_IND_REG__DIDT, DIDT_DBR_CTRL0, DIDT_CTRL_EN, en); }
+  if (PP_CAP(PHM_PlatformCaps_DiDtEDCEnable)) {
+    if (PP_CAP(PHM_PlatformCaps_SQRamping)) {
       data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL);
       data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_EN, en);
       data = CGS_REG_SET_FIELD(data, DIDT_SQ_EDC_CTRL, EDC_SW_RST, ~en);
       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_SQ_EDC_CTRL, data);
     }
-    if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRamping)) {
+    if (PP_CAP(PHM_PlatformCaps_DBRamping)) {
       data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL);
       data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_EN, en);
       data = CGS_REG_SET_FIELD(data, DIDT_DB_EDC_CTRL, EDC_SW_RST, ~en);
       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DB_EDC_CTRL, data);
     }
-    if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TDRamping)) {
+    if (PP_CAP(PHM_PlatformCaps_TDRamping)) {
       data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL);
       data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_EN, en);
       data = CGS_REG_SET_FIELD(data, DIDT_TD_EDC_CTRL, EDC_SW_RST, ~en);
       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TD_EDC_CTRL, data);
     }
-    if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_TCPRamping)) {
+    if (PP_CAP(PHM_PlatformCaps_TCPRamping)) {
       data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL);
       data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_EN, en);
       data = CGS_REG_SET_FIELD(data, DIDT_TCP_EDC_CTRL, EDC_SW_RST, ~en);
       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_TCP_EDC_CTRL, data);
     }
-    if (phm_cap_enabled(hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_DBRRamping)) {
+    if (PP_CAP(PHM_PlatformCaps_DBRRamping)) {
       data = cgs_read_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL);
       data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_EN, en);
       data = CGS_REG_SET_FIELD(data, DIDT_DBR_EDC_CTRL, EDC_SW_RST, ~en);
       cgs_write_ind_register(hwmgr->device, CGS_IND_REG__DIDT, ixDIDT_DBR_EDC_CTRL, data);
     }
   }
   if (enable) {
     /* For Vega10, SMC does not support any mask yet. */
     result = smum_send_msg_to_smc_with_parameter(hwmgr->smumgr, PPSMC_MSG_ConfigureGfxDidt, didt_block_info);
     PP_ASSERT((0 == result), "[EnableDiDtConfig] SMC Configure Gfx Didt Failed!");
   }
 }<sep>@@
expression hwmgr,e;
@@
- phm_cap_enabled(hwmgr->platform_descriptor.platformCaps,e)
+ PP_CAP(e)