--- initial
+++ final
@@ -1,106 +1,106 @@
 static int gfx_v8_0_sw_init(void *handle) {
   int i, j, k, r, ring_id;
   struct amdgpu_ring *ring;
   struct amdgpu_kiq *kiq;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   switch (adev->asic_type) {
   case CHIP_TONGA:
   case CHIP_CARRIZO:
   case CHIP_FIJI:
   case CHIP_POLARIS10:
   case CHIP_POLARIS11:
   case CHIP_POLARIS12:
   case CHIP_VEGAM: adev->gfx.mec.num_mec = 2; break;
   case CHIP_TOPAZ:
   case CHIP_STONEY:
   default: adev->gfx.mec.num_mec = 1; break;
   }
   adev->gfx.mec.num_pipe_per_mec = 4;
   adev->gfx.mec.num_queue_per_pipe = 8;
   /* KIQ event */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 178, &adev->gfx.kiq.irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_INT_IB2, &adev->gfx.kiq.irq);
   if (r) return r;
   /* EOP Event */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 181, &adev->gfx.eop_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_END_OF_PIPE, &adev->gfx.eop_irq);
   if (r) return r;
   /* Privileged reg */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 184, &adev->gfx.priv_reg_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT, &adev->gfx.priv_reg_irq);
   if (r) return r;
   /* Privileged inst */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 185, &adev->gfx.priv_inst_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT, &adev->gfx.priv_inst_irq);
   if (r) return r;
   /* Add CP EDC/ECC irq  */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 197, &adev->gfx.cp_ecc_error_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_CP_ECC_ERROR, &adev->gfx.cp_ecc_error_irq);
   if (r) return r;
   /* SQ interrupts. */
-  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 239, &adev->gfx.sq_irq);
+  r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG, &adev->gfx.sq_irq);
   if (r) {
     DRM_ERROR("amdgpu_irq_add() for SQ failed: %d\n", r);
     return r;
   }
   INIT_WORK(&adev->gfx.sq_work.work, gfx_v8_0_sq_irq_work_func);
   adev->gfx.gfx_current_status = AMDGPU_GFX_NORMAL_MODE;
   gfx_v8_0_scratch_init(adev);
   r = gfx_v8_0_init_microcode(adev);
   if (r) {
     DRM_ERROR("Failed to load gfx firmware!\n");
     return r;
   }
   r = gfx_v8_0_rlc_init(adev);
   if (r) {
     DRM_ERROR("Failed to init rlc BOs!\n");
     return r;
   }
   r = gfx_v8_0_mec_init(adev);
   if (r) {
     DRM_ERROR("Failed to init MEC BOs!\n");
     return r;
   }
   /* set up the gfx ring */
   for (i = 0; i < adev->gfx.num_gfx_rings; i++) {
     ring = &adev->gfx.gfx_ring[i];
     ring->ring_obj = NULL;
     sprintf(ring->name, "gfx");
     /* no gfx doorbells on iceland */
     if (adev->asic_type != CHIP_TOPAZ) {
       ring->use_doorbell = true;
       ring->doorbell_index = AMDGPU_DOORBELL_GFX_RING0;
     }
     r = amdgpu_ring_init(adev, ring, 1024, &adev->gfx.eop_irq, AMDGPU_CP_IRQ_GFX_EOP);
     if (r) return r;
   }
   /* set up the compute queues - allocate horizontally across pipes */
   ring_id = 0;
   for (i = 0; i < adev->gfx.mec.num_mec; ++i) {
     for (j = 0; j < adev->gfx.mec.num_queue_per_pipe; j++) {
       for (k = 0; k < adev->gfx.mec.num_pipe_per_mec; k++) {
         if (!amdgpu_gfx_is_mec_queue_enabled(adev, i, k, j)) continue;
         r = gfx_v8_0_compute_ring_init(adev, ring_id, i, k, j);
         if (r) return r;
         ring_id++;
       }
     }
   }
   r = amdgpu_gfx_kiq_init(adev, GFX8_MEC_HPD_SIZE);
   if (r) {
     DRM_ERROR("Failed to init KIQ BOs!\n");
     return r;
   }
   kiq = &adev->gfx.kiq;
   r = amdgpu_gfx_kiq_init_ring(adev, &kiq->ring, &kiq->irq);
   if (r) return r;
   /* create MQD for all compute queues as well as KIQ for SRIOV case */
   r = amdgpu_gfx_compute_mqd_sw_init(adev, sizeof(struct vi_mqd_allocation));
   if (r) return r;
   /* reserve GDS, GWS and OA resource for gfx */
   r = amdgpu_bo_create_kernel(adev, adev->gds.mem.gfx_partition_size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GDS, &adev->gds.gds_gfx_bo, NULL, NULL);
   if (r) return r;
   r = amdgpu_bo_create_kernel(adev, adev->gds.gws.gfx_partition_size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_GWS, &adev->gds.gws_gfx_bo, NULL, NULL);
   if (r) return r;
   r = amdgpu_bo_create_kernel(adev, adev->gds.oa.gfx_partition_size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_OA, &adev->gds.oa_gfx_bo, NULL, NULL);
   if (r) return r;
   adev->gfx.ce_ram_size = 0x8000;
   r = gfx_v8_0_gpu_early_init(adev);
   if (r) return r;
   return 0;
 }<sep>@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 178
+ VISLANDS30_IV_SRCID_CP_INT_IB2 
...+>,e3)
@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 181
+ VISLANDS30_IV_SRCID_CP_END_OF_PIPE 
...+>,e3)
@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 184
+ VISLANDS30_IV_SRCID_CP_PRIV_REG_FAULT
...+>,e3)
@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 185
+ VISLANDS30_IV_SRCID_CP_PRIV_INSTR_FAULT
...+>,e3)
@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 197
+ VISLANDS30_IV_SRCID_CP_ECC_ERROR 
...+>,e3)

@@
expression e1,e2,e3;
@@
amdgpu_irq_add_id(e1,e2,<+...
- 239
+ VISLANDS30_IV_SRCID_SQ_INTERRUPT_MSG 
...+>,e3)