imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,60 +1,60 @@
 static void intel_panel_init_backlight_funcs(struct intel_panel *panel) {
   struct intel_connector *connector = container_of(panel, struct intel_connector, panel);
   struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
   if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && intel_dp_aux_init_backlight_funcs(connector) == 0) return;
   if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI && intel_dsi_dcs_init_backlight_funcs(connector) == 0) return;
-  if (IS_BROXTON(dev_priv)) {
+  if (IS_GEN9_LP(dev_priv)) {
     panel->backlight.setup = bxt_setup_backlight;
     panel->backlight.enable = bxt_enable_backlight;
     panel->backlight.disable = bxt_disable_backlight;
     panel->backlight.set = bxt_set_backlight;
     panel->backlight.get = bxt_get_backlight;
     panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
   } else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) || HAS_PCH_KBP(dev_priv)) {
     panel->backlight.setup = lpt_setup_backlight;
     panel->backlight.enable = lpt_enable_backlight;
     panel->backlight.disable = lpt_disable_backlight;
     panel->backlight.set = lpt_set_backlight;
     panel->backlight.get = lpt_get_backlight;
     if (HAS_PCH_LPT(dev_priv))
       panel->backlight.hz_to_pwm = lpt_hz_to_pwm;
     else
       panel->backlight.hz_to_pwm = spt_hz_to_pwm;
   } else if (HAS_PCH_SPLIT(dev_priv)) {
     panel->backlight.setup = pch_setup_backlight;
     panel->backlight.enable = pch_enable_backlight;
     panel->backlight.disable = pch_disable_backlight;
     panel->backlight.set = pch_set_backlight;
     panel->backlight.get = pch_get_backlight;
     panel->backlight.hz_to_pwm = pch_hz_to_pwm;
   } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
     if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI) {
       panel->backlight.setup = pwm_setup_backlight;
       panel->backlight.enable = pwm_enable_backlight;
       panel->backlight.disable = pwm_disable_backlight;
       panel->backlight.set = pwm_set_backlight;
       panel->backlight.get = pwm_get_backlight;
     } else {
       panel->backlight.setup = vlv_setup_backlight;
       panel->backlight.enable = vlv_enable_backlight;
       panel->backlight.disable = vlv_disable_backlight;
       panel->backlight.set = vlv_set_backlight;
       panel->backlight.get = vlv_get_backlight;
       panel->backlight.hz_to_pwm = vlv_hz_to_pwm;
     }
   } else if (IS_GEN4(dev_priv)) {
     panel->backlight.setup = i965_setup_backlight;
     panel->backlight.enable = i965_enable_backlight;
     panel->backlight.disable = i965_disable_backlight;
     panel->backlight.set = i9xx_set_backlight;
     panel->backlight.get = i9xx_get_backlight;
     panel->backlight.hz_to_pwm = i965_hz_to_pwm;
   } else {
     panel->backlight.setup = i9xx_setup_backlight;
     panel->backlight.enable = i9xx_enable_backlight;
     panel->backlight.disable = i9xx_disable_backlight;
     panel->backlight.set = i9xx_set_backlight;
     panel->backlight.get = i9xx_get_backlight;
     panel->backlight.hz_to_pwm = i9xx_hz_to_pwm;
   }
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,32 +1,32 @@
 static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) {
   /* All of these values are in units of 50MHz */
   /* static values from HW: RP0 > RP1 > RPn (min_freq) */
-  if (IS_BROXTON(dev_priv)) {
+  if (IS_GEN9_LP(dev_priv)) {
     u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
     dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
     dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
     dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
   } else {
     u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
     dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
     dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
     dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
   }
   /* hw_max = RP0 until we check for overclocking */
   dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
   dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
   if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
     u32 ddcc_status = 0;
     if (sandybridge_pcode_read(dev_priv, HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, &ddcc_status) == 0) dev_priv->rps.efficient_freq = clamp_t(u8, ((ddcc_status >> 8) & 0xff), dev_priv->rps.min_freq, dev_priv->rps.max_freq);
   }
   if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
     /* Store the frequency values in 16.66 MHZ units, which is
      * the natural hardware unit for SKL
      */
     dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
     dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
     dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
     dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
     dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
   }
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,28 +1,28 @@
 static void intel_pps_readout_hw_state(struct drm_i915_private *dev_priv, struct intel_dp *intel_dp, struct edp_power_seq *seq) {
   u32 pp_on, pp_off, pp_div = 0, pp_ctl = 0;
   struct pps_registers regs;
   intel_pps_get_registers(dev_priv, intel_dp, &regs);
   /* Workaround: Need to write PP_CONTROL with the unlock key as
    * the very first thing. */
   pp_ctl = ironlake_get_pp_control(intel_dp);
   pp_on = I915_READ(regs.pp_on);
   pp_off = I915_READ(regs.pp_off);
-  if (!IS_BROXTON(dev_priv)) {
+  if (!IS_GEN9_LP(dev_priv)) {
     I915_WRITE(regs.pp_ctrl, pp_ctl);
     pp_div = I915_READ(regs.pp_div);
   }
   /* Pull timing values out of registers */
   seq->t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> PANEL_POWER_UP_DELAY_SHIFT;
   seq->t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> PANEL_LIGHT_ON_DELAY_SHIFT;
   seq->t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> PANEL_LIGHT_OFF_DELAY_SHIFT;
   seq->t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> PANEL_POWER_DOWN_DELAY_SHIFT;
-  if (IS_BROXTON(dev_priv)) {
+  if (IS_GEN9_LP(dev_priv)) {
     u16 tmp = (pp_ctl & BXT_POWER_CYCLE_DELAY_MASK) >> BXT_POWER_CYCLE_DELAY_SHIFT;
     if (tmp > 0)
       seq->t11_t12 = (tmp - 1) * 1000;
     else
       seq->t11_t12 = 0;
   } else {
     seq->t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000;
   }
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,13 +1,13 @@
 static void intel_pps_get_registers(struct drm_i915_private *dev_priv, struct intel_dp *intel_dp, struct pps_registers *regs) {
   int pps_idx = 0;
   memset(regs, 0, sizeof(*regs));
-  if (IS_BROXTON(dev_priv))
+  if (IS_GEN9_LP(dev_priv))
     pps_idx = bxt_power_sequencer_idx(intel_dp);
   else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
     pps_idx = vlv_power_sequencer_pipe(intel_dp);
   regs->pp_ctrl = PP_CONTROL(pps_idx);
   regs->pp_stat = PP_STATUS(pps_idx);
   regs->pp_on = PP_ON_DELAYS(pps_idx);
   regs->pp_off = PP_OFF_DELAYS(pps_idx);
-  if (!IS_BROXTON(dev_priv)) regs->pp_div = PP_DIVISOR(pps_idx);
+  if (!IS_GEN9_LP(dev_priv)) regs->pp_div = PP_DIVISOR(pps_idx);
 }<sep>@@
expression e;
@@

-       IS_BROXTON
+       IS_GEN9_LP
		(e)
--- initial
+++ final
@@ -1,53 +1,53 @@
 bool rtl_hal_pwrseqcmdparsing(struct rtl_priv *rtlpriv, u8 cut_version, u8 faversion, u8 interface_type, struct wlan_pwr_cfg pwrcfgcmd[]) {
   struct wlan_pwr_cfg cfg_cmd = {0};
   bool polling_bit = false;
   u32 ary_idx = 0;
   u8 value = 0;
   u32 offset = 0;
   u32 polling_count = 0;
   u32 max_polling_cnt = 5000;
   do {
     cfg_cmd = pwrcfgcmd[ary_idx];
     RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "rtl_hal_pwrseqcmdparsing(): offset(%#x),cut_msk(%#x), famsk(%#x), interface_msk(%#x), base(%#x), cmd(%#x), msk(%#x), value(%#x)\n", GET_PWR_CFG_OFFSET(cfg_cmd), GET_PWR_CFG_CUT_MASK(cfg_cmd), GET_PWR_CFG_FAB_MASK(cfg_cmd), GET_PWR_CFG_INTF_MASK(cfg_cmd), GET_PWR_CFG_BASE(cfg_cmd), GET_PWR_CFG_CMD(cfg_cmd), GET_PWR_CFG_MASK(cfg_cmd), GET_PWR_CFG_VALUE(cfg_cmd));
     if ((GET_PWR_CFG_FAB_MASK(cfg_cmd) & faversion) && (GET_PWR_CFG_CUT_MASK(cfg_cmd) & cut_version) && (GET_PWR_CFG_INTF_MASK(cfg_cmd) & interface_type)) {
       switch (GET_PWR_CFG_CMD(cfg_cmd)) {
       case PWR_CMD_READ: RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "rtl_hal_pwrseqcmdparsing(): PWR_CMD_READ\n"); break;
       case PWR_CMD_WRITE:
         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "rtl_hal_pwrseqcmdparsing(): PWR_CMD_WRITE\n");
         offset = GET_PWR_CFG_OFFSET(cfg_cmd);
         /*Read the value from system register*/
         value = rtl_read_byte(rtlpriv, offset);
         value &= (~(GET_PWR_CFG_MASK(cfg_cmd)));
         value |= (GET_PWR_CFG_VALUE(cfg_cmd) & GET_PWR_CFG_MASK(cfg_cmd));
         /*Write the value back to sytem register*/
         rtl_write_byte(rtlpriv, offset, value);
         break;
       case PWR_CMD_POLLING:
         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "rtl_hal_pwrseqcmdparsing(): PWR_CMD_POLLING\n");
         polling_bit = false;
         offset = GET_PWR_CFG_OFFSET(cfg_cmd);
         do {
           value = rtl_read_byte(rtlpriv, offset);
           value &= GET_PWR_CFG_MASK(cfg_cmd);
           if (value == (GET_PWR_CFG_VALUE(cfg_cmd) & GET_PWR_CFG_MASK(cfg_cmd)))
             polling_bit = true;
           else
             udelay(10);
           if (polling_count++ > max_polling_cnt) return false;
         } while (!polling_bit);
         break;
       case PWR_CMD_DELAY:
         RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "rtl_hal_pwrseqcmdparsing(): PWR_CMD_DELAY\n");
         if (GET_PWR_CFG_VALUE(cfg_cmd) == PWRSEQ_DELAY_US)
           udelay(GET_PWR_CFG_OFFSET(cfg_cmd));
         else
           mdelay(GET_PWR_CFG_OFFSET(cfg_cmd));
         break;
       case PWR_CMD_END: RT_TRACE(rtlpriv, COMP_INIT, DBG_TRACE, "rtl_hal_pwrseqcmdparsing(): PWR_CMD_END\n"); return true;
-      default: RT_ASSERT(false, "rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n"); break;
+      default: WARN_ONCE(true, "rtl_hal_pwrseqcmdparsing(): Unknown CMD!!\n"); break;
       }
     }
     ary_idx++;
   } while (1);
   return true;
 }<sep>@@
expression list e;
@@
- RT_ASSERT(false,e)
+ WARN_ONCE(true,e)
--- initial
+++ final
@@ -1,63 +1,63 @@
 void rtl8821ae_add_wowlan_pattern(struct ieee80211_hw *hw, struct rtl_wow_pattern *rtl_pattern, u8 index) {
   struct rtl_priv *rtlpriv = rtl_priv(hw);
   u32 cam = 0;
   u8 addr = 0;
   u16 rxbuf_addr;
   u8 tmp, count = 0;
   u16 cam_start;
   u16 offset;
   /* Count the WFCAM entry start offset. */
   /* RX page size = 128 byte */
   offset = MAX_RX_DMA_BUFFER_SIZE_8812 / 128;
   /* We should start from the boundry */
   cam_start = offset * 128;
   /* Enable Rx packet buffer access. */
   rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, RXPKT_BUF_SELECT);
   for (addr = 0; addr < WKFMCAM_ADDR_NUM; addr++) {
     /* Set Rx packet buffer offset.
      * RxBufer pointer increases 1,
      * we can access 8 bytes in Rx packet buffer.
      * CAM start offset (unit: 1 byte) =  index*WKFMCAM_SIZE
      * RxBufer addr = (CAM start offset +
      *                 per entry offset of a WKFM CAM)/8
      *	* index: The index of the wake up frame mask
      *	* WKFMCAM_SIZE: the total size of one WKFM CAM
      *	* per entry offset of a WKFM CAM: Addr*4 bytes
      */
     rxbuf_addr = (cam_start + index * WKFMCAM_SIZE + addr * 4) >> 3;
     /* Set R/W start offset */
     rtl_write_word(rtlpriv, REG_PKTBUF_DBG_CTRL, rxbuf_addr);
     if (addr == 0) {
       cam = BIT(31) | rtl_pattern->crc;
       if (rtl_pattern->type == UNICAST_PATTERN)
         cam |= BIT(24);
       else if (rtl_pattern->type == MULTICAST_PATTERN)
         cam |= BIT(25);
       else if (rtl_pattern->type == BROADCAST_PATTERN)
         cam |= BIT(26);
       rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
       RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, "WRITE entry[%d] 0x%x: %x\n", addr, REG_PKTBUF_DBG_DATA_L, cam);
       /* Write to Rx packet buffer. */
       rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
     } else if (addr == 2 || addr == 4) { /* WKFM[127:0] */
       cam = rtl_pattern->mask[addr - 2];
       rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_L, cam);
       RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, "WRITE entry[%d] 0x%x: %x\n", addr, REG_PKTBUF_DBG_DATA_L, cam);
       rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0x0f01);
     } else if (addr == 3 || addr == 5) { /* WKFM[127:0] */
       cam = rtl_pattern->mask[addr - 2];
       rtl_write_dword(rtlpriv, REG_PKTBUF_DBG_DATA_H, cam);
       RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE, "WRITE entry[%d] 0x%x: %x\n", addr, REG_PKTBUF_DBG_DATA_H, cam);
       rtl_write_word(rtlpriv, REG_RXPKTBUF_CTRL, 0xf001);
     }
     count = 0;
     do {
       tmp = rtl_read_byte(rtlpriv, REG_RXPKTBUF_CTRL);
       udelay(2);
       count++;
     } while (tmp && count < 100);
-    RT_ASSERT((count < 100), "Write wake up frame mask FAIL %d value!\n", tmp);
+    WARN_ONCE((count >= 100), "Write wake up frame mask FAIL %d value!\n", tmp);
   }
   /* Disable Rx packet buffer access. */
   rtl_write_byte(rtlpriv, REG_PKT_BUFF_ACCESS_CTRL, DISABLE_TRXPKT_BUF_ACCESS);
 }<sep>@@
expression list e;
expression e1,e2;
@@
- RT_ASSERT((e1 < e2),e)
+ WARN_ONCE((e1 >= e2),e)
--- initial
+++ final
@@ -1 +1 @@
-static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset, u32 data) { RT_ASSERT(false, "deprecated!\n"); }
+static void _rtl8723e_phy_fw_rf_serial_write(struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset, u32 data) { WARN_ONCE(true, "deprecated!\n"); }<sep>@@
expression list e;
@@
- RT_ASSERT(false,e)
+ WARN_ONCE(true,e)
--- initial
+++ final
@@ -1,23 +1,23 @@
 void rtl92de_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, u8 desc_name, u8 *val) {
   if (istx) {
     switch (desc_name) {
     case HW_DESC_OWN:
       wmb();
       SET_TX_DESC_OWN(pdesc, 1);
       break;
     case HW_DESC_TX_NEXTDESC_ADDR: SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val); break;
-    default: RT_ASSERT(false, "ERR txdesc :%d not process\n", desc_name); break;
+    default: WARN_ONCE(true, "ERR txdesc :%d not process\n", desc_name); break;
     }
   } else {
     switch (desc_name) {
     case HW_DESC_RXOWN:
       wmb();
       SET_RX_DESC_OWN(pdesc, 1);
       break;
     case HW_DESC_RXBUFF_ADDR: SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *)val); break;
     case HW_DESC_RXPKT_LEN: SET_RX_DESC_PKT_LEN(pdesc, *(u32 *)val); break;
     case HW_DESC_RXERO: SET_RX_DESC_EOR(pdesc, 1); break;
-    default: RT_ASSERT(false, "ERR rxdesc :%d not process\n", desc_name); break;
+    default: WARN_ONCE(true, "ERR rxdesc :%d not process\n", desc_name); break;
     }
   }
 }<sep>@@
expression list e;
@@
- RT_ASSERT(false,e)
+ WARN_ONCE(true,e)
--- initial
+++ final
@@ -1,20 +1,20 @@
 u8 rtl88e_phy_sw_chnl(struct ieee80211_hw *hw) {
   struct rtl_priv *rtlpriv = rtl_priv(hw);
   struct rtl_phy *rtlphy = &rtlpriv->phy;
   struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
   if (rtlphy->sw_chnl_inprogress) return 0;
   if (rtlphy->set_bwmode_inprogress) return 0;
-  RT_ASSERT((rtlphy->current_channel <= 14), "WIRELESS_MODE_G but channel>14");
+  WARN_ONCE((rtlphy->current_channel > 14), "WIRELESS_MODE_G but channel>14");
   rtlphy->sw_chnl_inprogress = true;
   rtlphy->sw_chnl_stage = 0;
   rtlphy->sw_chnl_step = 0;
   if (!(is_hal_stop(rtlhal)) && !(RT_CANNOT_IO(hw))) {
     rtl88e_phy_sw_chnl_callback(hw);
     RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, "sw_chnl_inprogress false schedule workitem current channel %d\n", rtlphy->current_channel);
     rtlphy->sw_chnl_inprogress = false;
   } else {
     RT_TRACE(rtlpriv, COMP_CHAN, DBG_LOUD, "sw_chnl_inprogress false driver sleep or unload\n");
     rtlphy->sw_chnl_inprogress = false;
   }
   return 1;
 }<sep>@@
expression list e;
expression e1,e2;
@@
- RT_ASSERT((e1 <= e2),e)
+ WARN_ONCE((e1 > e2),e)
--- initial
+++ final
@@ -1,18 +1,18 @@
 u32 rtl8723be_get_desc(u8 *pdesc, bool istx, u8 desc_name) {
   u32 ret = 0;
   if (istx) {
     switch (desc_name) {
     case HW_DESC_OWN: ret = GET_TX_DESC_OWN(pdesc); break;
     case HW_DESC_TXBUFF_ADDR: ret = GET_TX_DESC_TX_BUFFER_ADDRESS(pdesc); break;
-    default: RT_ASSERT(false, "ERR txdesc :%d not process\n", desc_name); break;
+    default: WARN_ONCE(true, "ERR txdesc :%d not process\n", desc_name); break;
     }
   } else {
     switch (desc_name) {
     case HW_DESC_OWN: ret = GET_RX_DESC_OWN(pdesc); break;
     case HW_DESC_RXPKT_LEN: ret = GET_RX_DESC_PKT_LEN(pdesc); break;
     case HW_DESC_RXBUFF_ADDR: ret = GET_RX_DESC_BUFF_ADDR(pdesc); break;
-    default: RT_ASSERT(false, "ERR rxdesc :%d not process\n", desc_name); break;
+    default: WARN_ONCE(true, "ERR rxdesc :%d not process\n", desc_name); break;
     }
   }
   return ret;
 }<sep>@@
expression list e;
@@
- RT_ASSERT(false,e)
+ WARN_ONCE(true,e)
--- initial
+++ final
@@ -1,14 +1,14 @@
 static bool _rtl92ee_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid, u32 para1, u32 para2, u32 msdelay) {
   struct swchnlcmd *pcmd;
   if (cmdtable == NULL) {
-    RT_ASSERT(false, "cmdtable cannot be NULL.\n");
+    WARN_ONCE(true, "cmdtable cannot be NULL.\n");
     return false;
   }
   if (cmdtableidx >= cmdtablesz) return false;
   pcmd = cmdtable + cmdtableidx;
   pcmd->cmdid = cmdid;
   pcmd->para1 = para1;
   pcmd->para2 = para2;
   pcmd->msdelay = msdelay;
   return true;
 }<sep>@@
expression list e;
@@
- RT_ASSERT(false,e)
+ WARN_ONCE(true,e)
--- initial
+++ final
@@ -1,18 +1,18 @@
 u32 rtl8723e_get_desc(u8 *pdesc, bool istx, u8 desc_name) {
   u32 ret = 0;
   if (istx == true) {
     switch (desc_name) {
     case HW_DESC_OWN: ret = GET_TX_DESC_OWN(pdesc); break;
     case HW_DESC_TXBUFF_ADDR: ret = GET_TX_DESC_TX_BUFFER_ADDRESS(pdesc); break;
-    default: RT_ASSERT(false, "ERR txdesc :%d not process\n", desc_name); break;
+    default: WARN_ONCE(true, "ERR txdesc :%d not process\n", desc_name); break;
     }
   } else {
     switch (desc_name) {
     case HW_DESC_OWN: ret = GET_RX_DESC_OWN(pdesc); break;
     case HW_DESC_RXPKT_LEN: ret = GET_RX_DESC_PKT_LEN(pdesc); break;
     case HW_DESC_RXBUFF_ADDR: ret = GET_RX_DESC_BUFF_ADDR(pdesc); break;
-    default: RT_ASSERT(false, "ERR rxdesc :%d not process\n", desc_name); break;
+    default: WARN_ONCE(true, "ERR rxdesc :%d not process\n", desc_name); break;
     }
   }
   return ret;
 }<sep>@@
expression list e;
@@
- RT_ASSERT(false,e)
+ WARN_ONCE(true,e)
--- initial
+++ final
@@ -1,53 +1,53 @@
 static bool _rtl88e_phy_sw_chnl_step_by_step(struct ieee80211_hw *hw, u8 channel, u8 *stage, u8 *step, u32 *delay) {
   struct rtl_priv *rtlpriv = rtl_priv(hw);
   struct rtl_phy *rtlphy = &rtlpriv->phy;
   struct swchnlcmd precommoncmd[MAX_PRECMD_CNT];
   u32 precommoncmdcnt;
   struct swchnlcmd postcommoncmd[MAX_POSTCMD_CNT];
   u32 postcommoncmdcnt;
   struct swchnlcmd rfdependcmd[MAX_RFDEPENDCMD_CNT];
   u32 rfdependcmdcnt;
   struct swchnlcmd *currentcmd = NULL;
   u8 rfpath;
   u8 num_total_rfpath = rtlphy->num_total_rfpath;
   precommoncmdcnt = 0;
   _rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, MAX_PRECMD_CNT, CMDID_SET_TXPOWEROWER_LEVEL, 0, 0, 0);
   _rtl88e_phy_set_sw_chnl_cmdarray(precommoncmd, precommoncmdcnt++, MAX_PRECMD_CNT, CMDID_END, 0, 0, 0);
   postcommoncmdcnt = 0;
   _rtl88e_phy_set_sw_chnl_cmdarray(postcommoncmd, postcommoncmdcnt++, MAX_POSTCMD_CNT, CMDID_END, 0, 0, 0);
   rfdependcmdcnt = 0;
-  RT_ASSERT((channel >= 1 && channel <= 14), "illegal channel for Zebra: %d\n", channel);
+  WARN_ONCE((channel < 1 || channel > 14), "illegal channel for Zebra: %d\n", channel);
   _rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, MAX_RFDEPENDCMD_CNT, CMDID_RF_WRITEREG, RF_CHNLBW, channel, 10);
   _rtl88e_phy_set_sw_chnl_cmdarray(rfdependcmd, rfdependcmdcnt++, MAX_RFDEPENDCMD_CNT, CMDID_END, 0, 0, 0);
   do {
     switch (*stage) {
     case 0: currentcmd = &precommoncmd[*step]; break;
     case 1: currentcmd = &rfdependcmd[*step]; break;
     case 2: currentcmd = &postcommoncmd[*step]; break;
     default: RT_TRACE(rtlpriv, COMP_ERR, DBG_EMERG, "Invalid 'stage' = %d, Check it!\n", *stage); return true;
     }
     if (currentcmd->cmdid == CMDID_END) {
       if ((*stage) == 2) return true;
       (*stage)++;
       (*step) = 0;
       continue;
     }
     switch (currentcmd->cmdid) {
     case CMDID_SET_TXPOWEROWER_LEVEL: rtl88e_phy_set_txpower_level(hw, channel); break;
     case CMDID_WRITEPORT_ULONG: rtl_write_dword(rtlpriv, currentcmd->para1, currentcmd->para2); break;
     case CMDID_WRITEPORT_USHORT: rtl_write_word(rtlpriv, currentcmd->para1, (u16)currentcmd->para2); break;
     case CMDID_WRITEPORT_UCHAR: rtl_write_byte(rtlpriv, currentcmd->para1, (u8)currentcmd->para2); break;
     case CMDID_RF_WRITEREG:
       for (rfpath = 0; rfpath < num_total_rfpath; rfpath++) {
         rtlphy->rfreg_chnlval[rfpath] = ((rtlphy->rfreg_chnlval[rfpath] & 0xfffffc00) | currentcmd->para2);
         rtl_set_rfreg(hw, (enum radio_path)rfpath, currentcmd->para1, RFREG_OFFSET_MASK, rtlphy->rfreg_chnlval[rfpath]);
       }
       break;
     default: RT_TRACE(rtlpriv, COMP_ERR, DBG_LOUD, "switch case %#x not processed\n", currentcmd->cmdid); break;
     }
     break;
   } while (true);
   (*delay) = currentcmd->msdelay;
   (*step)++;
   return false;
 }<sep>@@
expression list e;
expression e1,e2,e3;
@@
- RT_ASSERT((e1 >= e2 && e1 <= e3),e)
+ WARN_ONCE((e1 < e2 || e1 > e3),e)
--- initial
+++ final
@@ -1,14 +1,14 @@
 static bool _rtl92s_phy_set_sw_chnl_cmdarray(struct swchnlcmd *cmdtable, u32 cmdtableidx, u32 cmdtablesz, enum swchnlcmd_id cmdid, u32 para1, u32 para2, u32 msdelay) {
   struct swchnlcmd *pcmd;
   if (cmdtable == NULL) {
-    RT_ASSERT(false, "cmdtable cannot be NULL\n");
+    WARN_ONCE(true, "cmdtable cannot be NULL\n");
     return false;
   }
   if (cmdtableidx >= cmdtablesz) return false;
   pcmd = cmdtable + cmdtableidx;
   pcmd->cmdid = cmdid;
   pcmd->para1 = para1;
   pcmd->para2 = para2;
   pcmd->msdelay = msdelay;
   return true;
 }<sep>@@
expression list e;
@@
- RT_ASSERT(false,e)
+ WARN_ONCE(true,e)
--- initial
+++ final
@@ -1,13 +1,13 @@
 void rtl92ee_set_qos(struct ieee80211_hw *hw, int aci) {
   struct rtl_priv *rtlpriv = rtl_priv(hw);
   rtl92ee_dm_init_edca_turbo(hw);
   switch (aci) {
   case AC1_BK: rtl_write_dword(rtlpriv, REG_EDCA_BK_PARAM, 0xa44f); break;
   case AC0_BE:
     /* rtl_write_dword(rtlpriv, REG_EDCA_BE_PARAM, u4b_ac_param); */
     break;
   case AC2_VI: rtl_write_dword(rtlpriv, REG_EDCA_VI_PARAM, 0x5e4322); break;
   case AC3_VO: rtl_write_dword(rtlpriv, REG_EDCA_VO_PARAM, 0x2f3222); break;
-  default: RT_ASSERT(false, "invalid aci: %d !\n", aci); break;
+  default: WARN_ONCE(true, "invalid aci: %d !\n", aci); break;
   }
 }<sep>@@
expression list e;
@@
- RT_ASSERT(false,e)
+ WARN_ONCE(true,e)
--- initial
+++ final
@@ -1,17 +1,17 @@
 void rtl8821ae_set_desc(struct ieee80211_hw *hw, u8 *pdesc, bool istx, u8 desc_name, u8 *val) {
   if (istx) {
     switch (desc_name) {
     case HW_DESC_OWN: SET_TX_DESC_OWN(pdesc, 1); break;
     case HW_DESC_TX_NEXTDESC_ADDR: SET_TX_DESC_NEXT_DESC_ADDRESS(pdesc, *(u32 *)val); break;
-    default: RT_ASSERT(false, "ERR txdesc :%d not process\n", desc_name); break;
+    default: WARN_ONCE(true, "ERR txdesc :%d not process\n", desc_name); break;
     }
   } else {
     switch (desc_name) {
     case HW_DESC_RXOWN: SET_RX_DESC_OWN(pdesc, 1); break;
     case HW_DESC_RXBUFF_ADDR: SET_RX_DESC_BUFF_ADDR(pdesc, *(u32 *)val); break;
     case HW_DESC_RXPKT_LEN: SET_RX_DESC_PKT_LEN(pdesc, *(u32 *)val); break;
     case HW_DESC_RXERO: SET_RX_DESC_EOR(pdesc, 1); break;
-    default: RT_ASSERT(false, "ERR rxdesc :%d not process\n", desc_name); break;
+    default: WARN_ONCE(true, "ERR rxdesc :%d not process\n", desc_name); break;
     }
   }
 }<sep>@@
expression list e;
@@
- RT_ASSERT(false,e)
+ WARN_ONCE(true,e)
--- initial
+++ final
@@ -1,4 +1,4 @@
 u32 _rtl92c_phy_fw_rf_serial_read(struct ieee80211_hw *hw, enum radio_path rfpath, u32 offset) {
-  RT_ASSERT(false, "deprecated!\n");
+  WARN_ONCE(true, "deprecated!\n");
   return 0;
 }<sep>@@
expression list e;
@@
- RT_ASSERT(false,e)
+ WARN_ONCE(true,e)