imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,51 +1,51 @@
 static int brcmnand_init_cs(struct brcmnand_host *host, struct device_node *dn) {
   struct brcmnand_controller *ctrl = host->ctrl;
   struct platform_device *pdev = host->pdev;
   struct mtd_info *mtd;
   struct nand_chip *chip;
   int ret;
   u16 cfg_offs;
   ret = of_property_read_u32(dn, "reg", &host->cs);
   if (ret) {
     dev_err(&pdev->dev, "can't get chip-select\n");
     return -ENXIO;
   }
   mtd = nand_to_mtd(&host->chip);
   chip = &host->chip;
   nand_set_flash_node(chip, dn);
   nand_set_controller_data(chip, host);
   mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "brcmnand.%d", host->cs);
   if (!mtd->name) return -ENOMEM;
   mtd->owner = THIS_MODULE;
   mtd->dev.parent = &pdev->dev;
   chip->IO_ADDR_R = (void __iomem *)0xdeadbeef;
   chip->IO_ADDR_W = (void __iomem *)0xdeadbeef;
   chip->cmd_ctrl = brcmnand_cmd_ctrl;
   chip->cmdfunc = brcmnand_cmdfunc;
   chip->waitfunc = brcmnand_waitfunc;
   chip->read_byte = brcmnand_read_byte;
   chip->read_buf = brcmnand_read_buf;
   chip->write_buf = brcmnand_write_buf;
   chip->ecc.mode = NAND_ECC_HW;
   chip->ecc.read_page = brcmnand_read_page;
   chip->ecc.write_page = brcmnand_write_page;
   chip->ecc.read_page_raw = brcmnand_read_page_raw;
   chip->ecc.write_page_raw = brcmnand_write_page_raw;
   chip->ecc.write_oob_raw = brcmnand_write_oob_raw;
   chip->ecc.read_oob_raw = brcmnand_read_oob_raw;
   chip->ecc.read_oob = brcmnand_read_oob;
   chip->ecc.write_oob = brcmnand_write_oob;
   chip->controller = &ctrl->controller;
   /*
    * The bootloader might have configured 16bit mode but
    * NAND READID command only works in 8bit mode. We force
    * 8bit mode here to ensure that NAND READID commands works.
    */
   cfg_offs = brcmnand_cs_offset(ctrl, host->cs, BRCMNAND_CS_CFG);
   nand_writereg(ctrl, cfg_offs, nand_readreg(ctrl, cfg_offs) & ~CFG_BUS_WIDTH);
-  ret = nand_scan(mtd, 1);
+  ret = nand_scan(&host->chip, 1);
   if (ret) return ret;
   ret = mtd_device_register(mtd, NULL, 0);
   if (ret) nand_cleanup(chip);
   return ret;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,65 +1,65 @@
 static int __init cmx270_init(void) {
   struct nand_chip *this;
   int ret;
   if (!(machine_is_armcore() && cpu_is_pxa27x())) return -ENODEV;
   ret = gpio_request(GPIO_NAND_CS, "NAND CS");
   if (ret) {
     pr_warn("CM-X270: failed to request NAND CS gpio\n");
     return ret;
   }
   gpio_direction_output(GPIO_NAND_CS, 1);
   ret = gpio_request(GPIO_NAND_RB, "NAND R/B");
   if (ret) {
     pr_warn("CM-X270: failed to request NAND R/B gpio\n");
     goto err_gpio_request;
   }
   gpio_direction_input(GPIO_NAND_RB);
   /* Allocate memory for MTD device structure and private data */
   this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
   if (!this) {
     ret = -ENOMEM;
     goto err_kzalloc;
   }
   cmx270_nand_io = ioremap(PXA_CS1_PHYS, 12);
   if (!cmx270_nand_io) {
     pr_debug("Unable to ioremap NAND device\n");
     ret = -EINVAL;
     goto err_ioremap;
   }
   cmx270_nand_mtd = nand_to_mtd(this);
   /* Link the private data with the MTD structure */
   cmx270_nand_mtd->owner = THIS_MODULE;
   /* insert callbacks */
   this->IO_ADDR_R = cmx270_nand_io;
   this->IO_ADDR_W = cmx270_nand_io;
   this->cmd_ctrl = cmx270_hwcontrol;
   this->dev_ready = cmx270_device_ready;
   /* 15 us command delay time */
   this->chip_delay = 20;
   this->ecc.mode = NAND_ECC_SOFT;
   this->ecc.algo = NAND_ECC_HAMMING;
   /* read/write functions */
   this->read_byte = cmx270_read_byte;
   this->read_buf = cmx270_read_buf;
   this->write_buf = cmx270_write_buf;
   /* Scan to find existence of the device */
-  ret = nand_scan(cmx270_nand_mtd, 1);
+  ret = nand_scan(this, 1);
   if (ret) {
     pr_notice("No NAND device\n");
     goto err_scan;
   }
   /* Register the partitions */
   ret = mtd_device_register(cmx270_nand_mtd, partition_info, NUM_PARTITIONS);
   if (ret) goto err_scan;
   /* Return happy */
   return 0;
 err_scan:
   iounmap(cmx270_nand_io);
 err_ioremap:
   kfree(this);
 err_kzalloc:
   gpio_free(GPIO_NAND_RB);
 err_gpio_request:
   gpio_free(GPIO_NAND_CS);
   return ret;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,59 +1,59 @@
 static int __init cs553x_init_one(int cs, int mmio, unsigned long adr) {
   int err = 0;
   struct nand_chip *this;
   struct mtd_info *new_mtd;
   pr_notice("Probing CS553x NAND controller CS#%d at %sIO 0x%08lx\n", cs, mmio ? "MM" : "P", adr);
   if (!mmio) {
     pr_notice("PIO mode not yet implemented for CS553X NAND controller\n");
     return -ENXIO;
   }
   /* Allocate memory for MTD device structure and private data */
   this = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
   if (!this) {
     err = -ENOMEM;
     goto out;
   }
   new_mtd = nand_to_mtd(this);
   /* Link the private data with the MTD structure */
   new_mtd->owner = THIS_MODULE;
   /* map physical address */
   this->IO_ADDR_R = this->IO_ADDR_W = ioremap(adr, 4096);
   if (!this->IO_ADDR_R) {
     pr_warn("ioremap cs553x NAND @0x%08lx failed\n", adr);
     err = -EIO;
     goto out_mtd;
   }
   this->cmd_ctrl = cs553x_hwcontrol;
   this->dev_ready = cs553x_device_ready;
   this->read_byte = cs553x_read_byte;
   this->read_buf = cs553x_read_buf;
   this->write_buf = cs553x_write_buf;
   this->chip_delay = 0;
   this->ecc.mode = NAND_ECC_HW;
   this->ecc.size = 256;
   this->ecc.bytes = 3;
   this->ecc.hwctl = cs_enable_hwecc;
   this->ecc.calculate = cs_calculate_ecc;
   this->ecc.correct = nand_correct_data;
   this->ecc.strength = 1;
   /* Enable the following for a flash based bad block table */
   this->bbt_options = NAND_BBT_USE_FLASH;
   new_mtd->name = kasprintf(GFP_KERNEL, "cs553x_nand_cs%d", cs);
   if (!new_mtd->name) {
     err = -ENOMEM;
     goto out_ior;
   }
   /* Scan to find existence of the device */
-  err = nand_scan(new_mtd, 1);
+  err = nand_scan(this, 1);
   if (err) goto out_free;
   cs553x_mtd[cs] = new_mtd;
   goto out;
 out_free:
   kfree(new_mtd->name);
 out_ior:
   iounmap(this->IO_ADDR_R);
 out_mtd:
   kfree(this);
 out:
   return err;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,78 +1,78 @@
 static int fsl_elbc_nand_probe(struct platform_device *pdev) {
   struct fsl_lbc_regs __iomem *lbc;
   struct fsl_elbc_mtd *priv;
   struct resource res;
   struct fsl_elbc_fcm_ctrl *elbc_fcm_ctrl;
   static const char *part_probe_types[] = {"cmdlinepart", "RedBoot", "ofpart", NULL};
   int ret;
   int bank;
   struct device *dev;
   struct device_node *node = pdev->dev.of_node;
   struct mtd_info *mtd;
   if (!fsl_lbc_ctrl_dev || !fsl_lbc_ctrl_dev->regs) return -ENODEV;
   lbc = fsl_lbc_ctrl_dev->regs;
   dev = fsl_lbc_ctrl_dev->dev;
   /* get, allocate and map the memory resource */
   ret = of_address_to_resource(node, 0, &res);
   if (ret) {
     dev_err(dev, "failed to get resource\n");
     return ret;
   }
   /* find which chip select it is connected to */
   for (bank = 0; bank < MAX_BANKS; bank++)
     if ((in_be32(&lbc->bank[bank].br) & BR_V) && (in_be32(&lbc->bank[bank].br) & BR_MSEL) == BR_MS_FCM && (in_be32(&lbc->bank[bank].br) & in_be32(&lbc->bank[bank].or) & BR_BA) == fsl_lbc_addr(res.start)) break;
   if (bank >= MAX_BANKS) {
     dev_err(dev, "address did not match any chip selects\n");
     return -ENODEV;
   }
   priv = kzalloc(sizeof(*priv), GFP_KERNEL);
   if (!priv) return -ENOMEM;
   mutex_lock(&fsl_elbc_nand_mutex);
   if (!fsl_lbc_ctrl_dev->nand) {
     elbc_fcm_ctrl = kzalloc(sizeof(*elbc_fcm_ctrl), GFP_KERNEL);
     if (!elbc_fcm_ctrl) {
       mutex_unlock(&fsl_elbc_nand_mutex);
       ret = -ENOMEM;
       goto err;
     }
     elbc_fcm_ctrl->counter++;
     nand_controller_init(&elbc_fcm_ctrl->controller);
     fsl_lbc_ctrl_dev->nand = elbc_fcm_ctrl;
   } else {
     elbc_fcm_ctrl = fsl_lbc_ctrl_dev->nand;
   }
   mutex_unlock(&fsl_elbc_nand_mutex);
   elbc_fcm_ctrl->chips[bank] = priv;
   priv->bank = bank;
   priv->ctrl = fsl_lbc_ctrl_dev;
   priv->dev = &pdev->dev;
   dev_set_drvdata(priv->dev, priv);
   priv->vbase = ioremap(res.start, resource_size(&res));
   if (!priv->vbase) {
     dev_err(dev, "failed to map chip region\n");
     ret = -ENOMEM;
     goto err;
   }
   mtd = nand_to_mtd(&priv->chip);
   mtd->name = kasprintf(GFP_KERNEL, "%llx.flash", (u64)res.start);
   if (!nand_to_mtd(&priv->chip)->name) {
     ret = -ENOMEM;
     goto err;
   }
   ret = fsl_elbc_chip_init(priv);
   if (ret) goto err;
   priv->chip.controller->ops = &fsl_elbc_controller_ops;
-  ret = nand_scan(mtd, 1);
+  ret = nand_scan(&priv->chip, 1);
   if (ret) goto err;
   /* First look for RedBoot table or partitions on the command
    * line, these take precedence over device tree information */
   ret = mtd_device_parse_register(mtd, part_probe_types, NULL, NULL, 0);
   if (ret) goto cleanup_nand;
   pr_info("eLBC NAND device at 0x%llx, bank %d\n", (unsigned long long)res.start, priv->bank);
   return 0;
 cleanup_nand:
   nand_cleanup(&priv->chip);
 err:
   fsl_elbc_chip_remove(priv);
   return ret;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,70 +1,70 @@
 static int gpio_nand_probe(struct platform_device *pdev) {
   struct gpiomtd *gpiomtd;
   struct nand_chip *chip;
   struct mtd_info *mtd;
   struct resource *res;
   struct device *dev = &pdev->dev;
   int ret = 0;
   if (!dev->of_node && !dev_get_platdata(dev)) return -EINVAL;
   gpiomtd = devm_kzalloc(dev, sizeof(*gpiomtd), GFP_KERNEL);
   if (!gpiomtd) return -ENOMEM;
   chip = &gpiomtd->nand_chip;
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   chip->IO_ADDR_R = devm_ioremap_resource(dev, res);
   if (IS_ERR(chip->IO_ADDR_R)) return PTR_ERR(chip->IO_ADDR_R);
   res = gpio_nand_get_io_sync(pdev);
   if (res) {
     gpiomtd->io_sync = devm_ioremap_resource(dev, res);
     if (IS_ERR(gpiomtd->io_sync)) return PTR_ERR(gpiomtd->io_sync);
   }
   ret = gpio_nand_get_config(dev, &gpiomtd->plat);
   if (ret) return ret;
   /* Just enable the chip */
   gpiomtd->nce = devm_gpiod_get_optional(dev, "nce", GPIOD_OUT_HIGH);
   if (IS_ERR(gpiomtd->nce)) return PTR_ERR(gpiomtd->nce);
   /* We disable write protection once we know probe() will succeed */
   gpiomtd->nwp = devm_gpiod_get_optional(dev, "nwp", GPIOD_OUT_LOW);
   if (IS_ERR(gpiomtd->nwp)) {
     ret = PTR_ERR(gpiomtd->nwp);
     goto out_ce;
   }
   gpiomtd->ale = devm_gpiod_get(dev, "ale", GPIOD_OUT_LOW);
   if (IS_ERR(gpiomtd->ale)) {
     ret = PTR_ERR(gpiomtd->ale);
     goto out_ce;
   }
   gpiomtd->cle = devm_gpiod_get(dev, "cle", GPIOD_OUT_LOW);
   if (IS_ERR(gpiomtd->cle)) {
     ret = PTR_ERR(gpiomtd->cle);
     goto out_ce;
   }
   gpiomtd->rdy = devm_gpiod_get_optional(dev, "rdy", GPIOD_IN);
   if (IS_ERR(gpiomtd->rdy)) {
     ret = PTR_ERR(gpiomtd->rdy);
     goto out_ce;
   }
   /* Using RDY pin */
   if (gpiomtd->rdy) chip->dev_ready = gpio_nand_devready;
   nand_set_flash_node(chip, pdev->dev.of_node);
   chip->IO_ADDR_W = chip->IO_ADDR_R;
   chip->ecc.mode = NAND_ECC_SOFT;
   chip->ecc.algo = NAND_ECC_HAMMING;
   chip->options = gpiomtd->plat.options;
   chip->chip_delay = gpiomtd->plat.chip_delay;
   chip->cmd_ctrl = gpio_nand_cmd_ctrl;
   mtd = nand_to_mtd(chip);
   mtd->dev.parent = dev;
   platform_set_drvdata(pdev, gpiomtd);
   /* Disable write protection, if wired up */
   if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp)) gpiod_direction_output(gpiomtd->nwp, 1);
-  ret = nand_scan(mtd, 1);
+  ret = nand_scan(chip, 1);
   if (ret) goto err_wp;
   if (gpiomtd->plat.adjust_parts) gpiomtd->plat.adjust_parts(&gpiomtd->plat, mtd->size);
   ret = mtd_device_register(mtd, gpiomtd->plat.parts, gpiomtd->plat.num_parts);
   if (!ret) return 0;
 err_wp:
   if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp)) gpiod_set_value(gpiomtd->nwp, 0);
 out_ce:
   if (gpiomtd->nce && !IS_ERR(gpiomtd->nce)) gpiod_set_value(gpiomtd->nce, 0);
   return ret;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,58 +1,58 @@
 static int jz4780_nand_init_chip(struct platform_device *pdev, struct jz4780_nand_controller *nfc, struct device_node *np, unsigned int chipnr) {
   struct device *dev = &pdev->dev;
   struct jz4780_nand_chip *nand;
   struct jz4780_nand_cs *cs;
   struct resource *res;
   struct nand_chip *chip;
   struct mtd_info *mtd;
   const __be32 *reg;
   int ret = 0;
   cs = &nfc->cs[chipnr];
   reg = of_get_property(np, "reg", NULL);
   if (!reg) return -EINVAL;
   cs->bank = be32_to_cpu(*reg);
   jz4780_nemc_set_type(nfc->dev, cs->bank, JZ4780_NEMC_BANK_NAND);
   res = platform_get_resource(pdev, IORESOURCE_MEM, chipnr);
   cs->base = devm_ioremap_resource(dev, res);
   if (IS_ERR(cs->base)) return PTR_ERR(cs->base);
   nand = devm_kzalloc(dev, sizeof(*nand), GFP_KERNEL);
   if (!nand) return -ENOMEM;
   nand->busy_gpio = devm_gpiod_get_optional(dev, "rb", GPIOD_IN);
   if (IS_ERR(nand->busy_gpio)) {
     ret = PTR_ERR(nand->busy_gpio);
     dev_err(dev, "failed to request busy GPIO: %d\n", ret);
     return ret;
   } else if (nand->busy_gpio) {
     nand->chip.dev_ready = jz4780_nand_dev_ready;
   }
   nand->wp_gpio = devm_gpiod_get_optional(dev, "wp", GPIOD_OUT_LOW);
   if (IS_ERR(nand->wp_gpio)) {
     ret = PTR_ERR(nand->wp_gpio);
     dev_err(dev, "failed to request WP GPIO: %d\n", ret);
     return ret;
   }
   chip = &nand->chip;
   mtd = nand_to_mtd(chip);
   mtd->name = devm_kasprintf(dev, GFP_KERNEL, "%s.%d", dev_name(dev), cs->bank);
   if (!mtd->name) return -ENOMEM;
   mtd->dev.parent = dev;
   chip->IO_ADDR_R = cs->base + OFFSET_DATA;
   chip->IO_ADDR_W = cs->base + OFFSET_DATA;
   chip->chip_delay = RB_DELAY_US;
   chip->options = NAND_NO_SUBPAGE_WRITE;
   chip->select_chip = jz4780_nand_select_chip;
   chip->cmd_ctrl = jz4780_nand_cmd_ctrl;
   chip->ecc.mode = NAND_ECC_HW;
   chip->controller = &nfc->controller;
   nand_set_flash_node(chip, np);
   chip->controller->ops = &jz4780_nand_controller_ops;
-  ret = nand_scan(mtd, 1);
+  ret = nand_scan(chip, 1);
   if (ret) return ret;
   ret = mtd_device_register(mtd, NULL, 0);
   if (ret) {
     nand_release(mtd);
     return ret;
   }
   list_add_tail(&nand->chip_list, &nfc->chips);
   return 0;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,52 +1,52 @@
 static int spinand_probe(struct spi_device *spi_nand) {
   struct mtd_info *mtd;
   struct nand_chip *chip;
   struct spinand_info *info;
   struct spinand_state *state;
   info = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_info), GFP_KERNEL);
   if (!info) return -ENOMEM;
   info->spi = spi_nand;
   spinand_lock_block(spi_nand, BL_ALL_UNLOCKED);
   state = devm_kzalloc(&spi_nand->dev, sizeof(struct spinand_state), GFP_KERNEL);
   if (!state) return -ENOMEM;
   info->priv = state;
   state->buf_ptr = 0;
   state->buf = devm_kzalloc(&spi_nand->dev, BUFSIZE, GFP_KERNEL);
   if (!state->buf) return -ENOMEM;
   chip = devm_kzalloc(&spi_nand->dev, sizeof(struct nand_chip), GFP_KERNEL);
   if (!chip) return -ENOMEM;
 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
   chip->ecc.mode = NAND_ECC_HW;
   chip->ecc.size = 0x200;
   chip->ecc.bytes = 0x6;
   chip->ecc.steps = 0x4;
   chip->ecc.strength = 1;
   chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
   chip->ecc.read_page = spinand_read_page_hwecc;
   chip->ecc.write_page = spinand_write_page_hwecc;
 #else
   chip->ecc.mode = NAND_ECC_SOFT;
   chip->ecc.algo = NAND_ECC_HAMMING;
   if (spinand_disable_ecc(spi_nand) < 0) dev_info(&spi_nand->dev, "%s: disable ecc failed!\n", __func__);
 #endif
   nand_set_flash_node(chip, spi_nand->dev.of_node);
   nand_set_controller_data(chip, info);
   chip->read_buf = spinand_read_buf;
   chip->write_buf = spinand_write_buf;
   chip->read_byte = spinand_read_byte;
   chip->cmdfunc = spinand_cmdfunc;
   chip->waitfunc = spinand_wait;
   chip->options |= NAND_CACHEPRG;
   chip->select_chip = spinand_select_chip;
   chip->set_features = nand_get_set_features_notsupp;
   chip->get_features = nand_get_set_features_notsupp;
   mtd = nand_to_mtd(chip);
   dev_set_drvdata(&spi_nand->dev, mtd);
   mtd->dev.parent = &spi_nand->dev;
   mtd->oobsize = 64;
 #ifdef CONFIG_MTD_SPINAND_ONDIEECC
   mtd_set_ooblayout(mtd, &spinand_oob_64_ops);
 #endif
-  if (nand_scan(mtd, 1)) return -ENXIO;
+  if (nand_scan(chip, 1)) return -ENXIO;
   return mtd_device_register(mtd, NULL, 0);
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,39 +1,39 @@
 static int ndfc_chip_init(struct ndfc_controller *ndfc, struct device_node *node) {
   struct device_node *flash_np;
   struct nand_chip *chip = &ndfc->chip;
   struct mtd_info *mtd = nand_to_mtd(chip);
   int ret;
   chip->IO_ADDR_R = ndfc->ndfcbase + NDFC_DATA;
   chip->IO_ADDR_W = ndfc->ndfcbase + NDFC_DATA;
   chip->cmd_ctrl = ndfc_hwcontrol;
   chip->dev_ready = ndfc_ready;
   chip->select_chip = ndfc_select_chip;
   chip->chip_delay = 50;
   chip->controller = &ndfc->ndfc_control;
   chip->read_buf = ndfc_read_buf;
   chip->write_buf = ndfc_write_buf;
   chip->ecc.correct = nand_correct_data;
   chip->ecc.hwctl = ndfc_enable_hwecc;
   chip->ecc.calculate = ndfc_calculate_ecc;
   chip->ecc.mode = NAND_ECC_HW;
   chip->ecc.size = 256;
   chip->ecc.bytes = 3;
   chip->ecc.strength = 1;
   nand_set_controller_data(chip, ndfc);
   mtd->dev.parent = &ndfc->ofdev->dev;
   flash_np = of_get_next_child(node, NULL);
   if (!flash_np) return -ENODEV;
   nand_set_flash_node(chip, flash_np);
   mtd->name = kasprintf(GFP_KERNEL, "%s.%pOFn", dev_name(&ndfc->ofdev->dev), flash_np);
   if (!mtd->name) {
     ret = -ENOMEM;
     goto err;
   }
-  ret = nand_scan(mtd, 1);
+  ret = nand_scan(chip, 1);
   if (ret) goto err;
   ret = mtd_device_register(mtd, NULL, 0);
 err:
   of_node_put(flash_np);
   if (ret) kfree(mtd->name);
   return ret;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,32 +1,32 @@
 static int nuc900_nand_probe(struct platform_device *pdev) {
   struct nuc900_nand *nuc900_nand;
   struct nand_chip *chip;
   struct mtd_info *mtd;
   struct resource *res;
   nuc900_nand = devm_kzalloc(&pdev->dev, sizeof(struct nuc900_nand), GFP_KERNEL);
   if (!nuc900_nand) return -ENOMEM;
   chip = &(nuc900_nand->chip);
   mtd = nand_to_mtd(chip);
   mtd->dev.parent = &pdev->dev;
   spin_lock_init(&nuc900_nand->lock);
   nuc900_nand->clk = devm_clk_get(&pdev->dev, NULL);
   if (IS_ERR(nuc900_nand->clk)) return -ENOENT;
   clk_enable(nuc900_nand->clk);
   chip->cmdfunc = nuc900_nand_command_lp;
   chip->dev_ready = nuc900_nand_devready;
   chip->read_byte = nuc900_nand_read_byte;
   chip->write_buf = nuc900_nand_write_buf;
   chip->read_buf = nuc900_nand_read_buf;
   chip->chip_delay = 50;
   chip->options = 0;
   chip->ecc.mode = NAND_ECC_SOFT;
   chip->ecc.algo = NAND_ECC_HAMMING;
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   nuc900_nand->reg = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(nuc900_nand->reg)) return PTR_ERR(nuc900_nand->reg);
   nuc900_nand_enable(nuc900_nand);
-  if (nand_scan(mtd, 1)) return -ENXIO;
+  if (nand_scan(chip, 1)) return -ENXIO;
   mtd_device_register(mtd, partitions, ARRAY_SIZE(partitions));
   platform_set_drvdata(pdev, nuc900_nand);
   return 0;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)
--- initial
+++ final
@@ -1,74 +1,74 @@
 static int omap_nand_probe(struct platform_device *pdev) {
   struct omap_nand_info *info;
   struct mtd_info *mtd;
   struct nand_chip *nand_chip;
   int err;
   struct resource *res;
   struct device *dev = &pdev->dev;
   info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info), GFP_KERNEL);
   if (!info) return -ENOMEM;
   info->pdev = pdev;
   err = omap_get_dt_info(dev, info);
   if (err) return err;
   info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs);
   if (!info->ops) {
     dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n");
     return -ENODEV;
   }
   nand_chip = &info->nand;
   mtd = nand_to_mtd(nand_chip);
   mtd->dev.parent = &pdev->dev;
   nand_chip->ecc.priv = NULL;
   nand_set_flash_node(nand_chip, dev->of_node);
   if (!mtd->name) {
     mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "omap2-nand.%d", info->gpmc_cs);
     if (!mtd->name) {
       dev_err(&pdev->dev, "Failed to set MTD name\n");
       return -ENOMEM;
     }
   }
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   nand_chip->IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(nand_chip->IO_ADDR_R)) return PTR_ERR(nand_chip->IO_ADDR_R);
   info->phys_base = res->start;
   nand_chip->controller = &omap_gpmc_controller;
   nand_chip->IO_ADDR_W = nand_chip->IO_ADDR_R;
   nand_chip->cmd_ctrl = omap_hwcontrol;
   info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "rb", GPIOD_IN);
   if (IS_ERR(info->ready_gpiod)) {
     dev_err(dev, "failed to get ready gpio\n");
     return PTR_ERR(info->ready_gpiod);
   }
   /*
    * If RDY/BSY line is connected to OMAP then use the omap ready
    * function and the generic nand_wait function which reads the status
    * register after monitoring the RDY/BSY line. Otherwise use a standard
    * chip delay which is slightly more than tR (AC Timing) of the NAND
    * device and read status register until you get a failure or success
    */
   if (info->ready_gpiod) {
     nand_chip->dev_ready = omap_dev_ready;
     nand_chip->chip_delay = 0;
   } else {
     nand_chip->waitfunc = omap_wait;
     nand_chip->chip_delay = 50;
   }
   if (info->flash_bbt) nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
   /* scan NAND device connected to chip controller */
   nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
-  err = nand_scan(mtd, 1);
+  err = nand_scan(nand_chip, 1);
   if (err) goto return_error;
   err = mtd_device_register(mtd, NULL, 0);
   if (err) goto cleanup_nand;
   platform_set_drvdata(pdev, mtd);
   return 0;
 cleanup_nand:
   nand_cleanup(nand_chip);
 return_error:
   if (!IS_ERR_OR_NULL(info->dma)) dma_release_channel(info->dma);
   if (nand_chip->ecc.priv) {
     nand_bch_free(nand_chip->ecc.priv);
     nand_chip->ecc.priv = NULL;
   }
   return err;
 }<sep>@@
expression board_mtd,this;
@@
board_mtd = nand_to_mtd(this)
...
-        nand_scan (board_mtd, 1)
+        nand_scan (this, 1)