--- initial
+++ final
@@ -1,86 +1,86 @@
 int amdgpu_uvd_sw_init(struct amdgpu_device *adev) {
   struct amdgpu_ring *ring;
   struct drm_sched_rq *rq;
   unsigned long bo_size;
   const char *fw_name;
   const struct common_firmware_header *hdr;
   unsigned version_major, version_minor, family_id;
   int i, r;
   INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler);
   switch (adev->asic_type) {
 #ifdef CONFIG_DRM_AMDGPU_CIK
   case CHIP_BONAIRE: fw_name = FIRMWARE_BONAIRE; break;
   case CHIP_KABINI: fw_name = FIRMWARE_KABINI; break;
   case CHIP_KAVERI: fw_name = FIRMWARE_KAVERI; break;
   case CHIP_HAWAII: fw_name = FIRMWARE_HAWAII; break;
   case CHIP_MULLINS: fw_name = FIRMWARE_MULLINS; break;
 #endif
   case CHIP_TONGA: fw_name = FIRMWARE_TONGA; break;
   case CHIP_FIJI: fw_name = FIRMWARE_FIJI; break;
   case CHIP_CARRIZO: fw_name = FIRMWARE_CARRIZO; break;
   case CHIP_STONEY: fw_name = FIRMWARE_STONEY; break;
   case CHIP_POLARIS10: fw_name = FIRMWARE_POLARIS10; break;
   case CHIP_POLARIS11: fw_name = FIRMWARE_POLARIS11; break;
   case CHIP_POLARIS12: fw_name = FIRMWARE_POLARIS12; break;
   case CHIP_VEGA10: fw_name = FIRMWARE_VEGA10; break;
   case CHIP_VEGA12: fw_name = FIRMWARE_VEGA12; break;
   case CHIP_VEGAM: fw_name = FIRMWARE_VEGAM; break;
   default: return -EINVAL;
   }
   r = request_firmware(&adev->uvd.fw, fw_name, adev->dev);
   if (r) {
     dev_err(adev->dev, "amdgpu_uvd: Can't load firmware \"%s\"\n", fw_name);
     return r;
   }
   r = amdgpu_ucode_validate(adev->uvd.fw);
   if (r) {
     dev_err(adev->dev, "amdgpu_uvd: Can't validate firmware \"%s\"\n", fw_name);
     release_firmware(adev->uvd.fw);
     adev->uvd.fw = NULL;
     return r;
   }
   /* Set the default UVD handles that the firmware can handle */
   adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES;
   hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
   family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
   version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
   version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
   DRM_INFO("Found UVD firmware Version: %hu.%hu Family ID: %hu\n", version_major, version_minor, family_id);
   /*
    * Limit the number of UVD handles depending on microcode major
    * and minor versions. The firmware version which has 40 UVD
    * instances support is 1.80. So all subsequent versions should
    * also have the same support.
    */
   if ((version_major > 0x01) || ((version_major == 0x01) && (version_minor >= 0x50))) adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES;
   adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | (family_id << 8));
   if ((adev->asic_type == CHIP_POLARIS10 || adev->asic_type == CHIP_POLARIS11) && (adev->uvd.fw_version < FW_1_66_16)) DRM_ERROR("POLARIS10/11 UVD firmware version %hu.%hu is too old.\n", version_major, version_minor);
   bo_size = AMDGPU_UVD_STACK_SIZE + AMDGPU_UVD_HEAP_SIZE + AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles;
   if (adev->firmware.load_type != AMDGPU_FW_LOAD_PSP) bo_size += AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8);
   r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, &adev->uvd.vcpu_bo, &adev->uvd.gpu_addr, &adev->uvd.cpu_addr);
   if (r) {
     dev_err(adev->dev, "(%d) failed to allocate UVD bo\n", r);
     return r;
   }
   ring = &adev->uvd.ring;
   rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-  r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity, rq, amdgpu_sched_jobs, NULL);
+  r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity, rq, NULL);
   if (r != 0) {
     DRM_ERROR("Failed setting up UVD run queue.\n");
     return r;
   }
   for (i = 0; i < adev->uvd.max_handles; ++i) {
     atomic_set(&adev->uvd.handles[i], 0);
     adev->uvd.filp[i] = NULL;
   }
   /* from uvd v5.0 HW addressing capacity increased to 64 bits */
   if (!amdgpu_device_ip_block_version_cmp(adev, AMD_IP_BLOCK_TYPE_UVD, 5, 0)) adev->uvd.address_64_bit = true;
   switch (adev->asic_type) {
   case CHIP_TONGA: adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_65_10; break;
   case CHIP_CARRIZO: adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_11; break;
   case CHIP_FIJI: adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_87_12; break;
   case CHIP_STONEY: adev->uvd.use_ctx_buf = adev->uvd.fw_version >= FW_1_37_15; break;
   default: adev->uvd.use_ctx_buf = adev->asic_type >= CHIP_POLARIS10;
   }
   return 0;
 }<sep>@@
expression e1,e2,e3,e4,d;
@@

 	drm_sched_entity_init(e1,e2,e3,
- 				  d,
 				  e4)