imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,10 +1,9 @@
 static void xfs_symlink_read_verify(struct xfs_buf *bp) {
   struct xfs_mount *mp = bp->b_target->bt_mount;
   /* no verification of non-crc buffers */
   if (!xfs_sb_version_hascrc(&mp->m_sb)) return;
   if (!xfs_buf_verify_cksum(bp, XFS_SYMLINK_CRC_OFF))
-    xfs_buf_ioerror(bp, -EFSBADCRC);
+    xfs_verifier_error(bp, -EFSBADCRC);
   else if (!xfs_symlink_verify(bp))
-    xfs_buf_ioerror(bp, -EFSCORRUPTED);
-  if (bp->b_error) xfs_verifier_error(bp);
+    xfs_verifier_error(bp, -EFSCORRUPTED);
 }<sep>@@
expression bp;
@@

	if (...)
-               xfs_buf_ioerror(bp, -EFSBADCRC);
+               xfs_verifier_error(bp, -EFSBADCRC);
        else if (...)
-               xfs_buf_ioerror(bp, -EFSCORRUPTED);
-
-       if (bp->b_error)
-               xfs_verifier_error(bp);
+               xfs_verifier_error(bp, -EFSCORRUPTED);
--- initial
+++ final
@@ -1,16 +1,15 @@
 static void xfs_symlink_write_verify(struct xfs_buf *bp) {
   struct xfs_mount *mp = bp->b_target->bt_mount;
   struct xfs_buf_log_item *bip = bp->b_fspriv;
   /* no verification of non-crc buffers */
   if (!xfs_sb_version_hascrc(&mp->m_sb)) return;
   if (!xfs_symlink_verify(bp)) {
-    xfs_buf_ioerror(bp, -EFSCORRUPTED);
-    xfs_verifier_error(bp);
+    xfs_verifier_error(bp, -EFSCORRUPTED);
     return;
   }
   if (bip) {
     struct xfs_dsymlink_hdr *dsl = bp->b_addr;
     dsl->sl_lsn = cpu_to_be64(bip->bli_item.li_lsn);
   }
   xfs_buf_update_cksum(bp, XFS_SYMLINK_CRC_OFF);
 }<sep>@@
expression bp,e;
@@

-               xfs_buf_ioerror(bp, e);
-               xfs_verifier_error(bp);
+               xfs_verifier_error(bp, e);
--- initial
+++ final
@@ -1,21 +1,21 @@
 static int clsact_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) {
   struct clsact_sched_data *q = qdisc_priv(sch);
   struct net_device *dev = qdisc_dev(sch);
   int err;
   net_inc_ingress_queue();
   net_inc_egress_queue();
   mini_qdisc_pair_init(&q->miniqp_ingress, sch, &dev->miniq_ingress);
   q->ingress_block_info.binder_type = TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS;
   q->ingress_block_info.chain_head_change = clsact_chain_head_change;
   q->ingress_block_info.chain_head_change_priv = &q->miniqp_ingress;
-  err = tcf_block_get_ext(&q->ingress_block, sch, &q->ingress_block_info);
+  err = tcf_block_get_ext(&q->ingress_block, sch, &q->ingress_block_info, extack);
   if (err) return err;
   mini_qdisc_pair_init(&q->miniqp_egress, sch, &dev->miniq_egress);
   q->egress_block_info.binder_type = TCF_BLOCK_BINDER_TYPE_CLSACT_EGRESS;
   q->egress_block_info.chain_head_change = clsact_chain_head_change;
   q->egress_block_info.chain_head_change_priv = &q->miniqp_egress;
-  err = tcf_block_get_ext(&q->egress_block, sch, &q->egress_block_info);
+  err = tcf_block_get_ext(&q->egress_block, sch, &q->egress_block_info, extack);
   if (err) return err;
   sch->flags |= TCQ_F_CPUSTATS;
   return 0;
 }<sep>@@
identifier f,extack;
expression e1,e2,e3;
@@

f(...,struct netlink_ext_ack *extack,...) { <...
tcf_block_get_ext(e1,e2,e3
+                   ,extack
             )
...> }
--- initial
+++ final
@@ -1,14 +1,14 @@
 static int ingress_init(struct Qdisc *sch, struct nlattr *opt, struct netlink_ext_ack *extack) {
   struct ingress_sched_data *q = qdisc_priv(sch);
   struct net_device *dev = qdisc_dev(sch);
   int err;
   net_inc_ingress_queue();
   mini_qdisc_pair_init(&q->miniqp, sch, &dev->miniq_ingress);
   q->block_info.binder_type = TCF_BLOCK_BINDER_TYPE_CLSACT_INGRESS;
   q->block_info.chain_head_change = clsact_chain_head_change;
   q->block_info.chain_head_change_priv = &q->miniqp;
-  err = tcf_block_get_ext(&q->block, sch, &q->block_info);
+  err = tcf_block_get_ext(&q->block, sch, &q->block_info, extack);
   if (err) return err;
   sch->flags |= TCQ_F_CPUSTATS;
   return 0;
 }<sep>@@
identifier f,extack;
expression e1,e2,e3;
@@

f(...,struct netlink_ext_ack *extack,...) { <...
tcf_block_get_ext(e1,e2,e3
+                   ,extack
             )
...> }
--- initial
+++ final
@@ -1,38 +1,39 @@
 static int amdgpu_cs_bo_validate(struct amdgpu_cs_parser *p, struct amdgpu_bo *bo) {
+  struct ttm_operation_ctx ctx = {true, false};
   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
   u64 initial_bytes_moved, bytes_moved;
   uint32_t domain;
   int r;
   if (bo->pin_count) return 0;
   /* Don't move this buffer if we have depleted our allowance
    * to move it. Don't move anything if the threshold is zero.
    */
   if (p->bytes_moved < p->bytes_moved_threshold) {
     if (adev->mc.visible_vram_size < adev->mc.real_vram_size && (bo->flags & AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED)) {
       /* And don't move a CPU_ACCESS_REQUIRED BO to limited
        * visible VRAM if we've depleted our allowance to do
        * that.
        */
       if (p->bytes_moved_vis < p->bytes_moved_vis_threshold)
         domain = bo->preferred_domains;
       else
         domain = bo->allowed_domains;
     } else {
       domain = bo->preferred_domains;
     }
   } else {
     domain = bo->allowed_domains;
   }
 retry:
   amdgpu_ttm_placement_from_domain(bo, domain);
   initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
-  r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+  r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
   bytes_moved = atomic64_read(&adev->num_bytes_moved) - initial_bytes_moved;
   p->bytes_moved += bytes_moved;
   if (adev->mc.visible_vram_size < adev->mc.real_vram_size && bo->tbo.mem.mem_type == TTM_PL_VRAM && bo->tbo.mem.start<adev->mc.visible_vram_size> > PAGE_SHIFT) p->bytes_moved_vis += bytes_moved;
   if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
     domain = bo->allowed_domains;
     goto retry;
   }
   return r;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,20 +1,21 @@
 int amdgpu_cs_find_mapping(struct amdgpu_cs_parser *parser, uint64_t addr, struct amdgpu_bo **bo, struct amdgpu_bo_va_mapping **map) {
+  struct ttm_operation_ctx ctx = {false, false};
   struct amdgpu_fpriv *fpriv = parser->filp->driver_priv;
   struct amdgpu_vm *vm = &fpriv->vm;
   struct amdgpu_bo_va_mapping *mapping;
   int r;
   addr /= AMDGPU_GPU_PAGE_SIZE;
   mapping = amdgpu_vm_bo_lookup_mapping(vm, addr);
   if (!mapping || !mapping->bo_va || !mapping->bo_va->base.bo) return -EINVAL;
   *bo = mapping->bo_va->base.bo;
   *map = mapping;
   /* Double check that the BO is reserved by this CS */
   if (READ_ONCE((*bo)->tbo.resv->lock.ctx) != &parser->ticket) return -EINVAL;
   if (!((*bo)->flags & AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS)) {
     (*bo)->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
     amdgpu_ttm_placement_from_domain(*bo, (*bo)->allowed_domains);
-    r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, false, false);
+    r = ttm_bo_validate(&(*bo)->tbo, &(*bo)->placement, &ctx);
     if (r) return r;
   }
   return amdgpu_ttm_alloc_gart(&(*bo)->tbo);
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,27 +1,28 @@
 static int amdgpu_cs_list_validate(struct amdgpu_cs_parser *p, struct list_head *validated) {
+  struct ttm_operation_ctx ctx = {true, false};
   struct amdgpu_bo_list_entry *lobj;
   int r;
   list_for_each_entry(lobj, validated, tv.head) {
     struct amdgpu_bo *bo = lobj->robj;
     bool binding_userptr = false;
     struct mm_struct *usermm;
     usermm = amdgpu_ttm_tt_get_usermm(bo->tbo.ttm);
     if (usermm && usermm != current->mm) return -EPERM;
     /* Check if we have user pages and nobody bound the BO already */
     if (amdgpu_ttm_tt_userptr_needs_pages(bo->tbo.ttm) && lobj->user_pages) {
       amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_CPU);
-      r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+      r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
       if (r) return r;
       amdgpu_ttm_tt_set_user_pages(bo->tbo.ttm, lobj->user_pages);
       binding_userptr = true;
     }
     if (p->evictable == lobj) p->evictable = NULL;
     r = amdgpu_cs_validate(p, bo);
     if (r) return r;
     if (binding_userptr) {
       kvfree(lobj->user_pages);
       lobj->user_pages = NULL;
     }
   }
   return 0;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,36 +1,37 @@
 static bool amdgpu_cs_try_evict(struct amdgpu_cs_parser *p, struct amdgpu_bo *validated) {
+  struct ttm_operation_ctx ctx = {true, false};
   uint32_t domain = validated->allowed_domains;
   int r;
   if (!p->evictable) return false;
   for (; &p->evictable->tv.head != &p->validated; p->evictable = list_prev_entry(p->evictable, tv.head)) {
     struct amdgpu_bo_list_entry *candidate = p->evictable;
     struct amdgpu_bo *bo = candidate->robj;
     struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
     u64 initial_bytes_moved, bytes_moved;
     bool update_bytes_moved_vis;
     uint32_t other;
     /* If we reached our current BO we can forget it */
     if (candidate->robj == validated) break;
     /* We can't move pinned BOs here */
     if (bo->pin_count) continue;
     other = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
     /* Check if this BO is in one of the domains we need space for */
     if (!(other & domain)) continue;
     /* Check if we can move this BO somewhere else */
     other = bo->allowed_domains & ~domain;
     if (!other) continue;
     /* Good we can try to move this BO somewhere else */
     amdgpu_ttm_placement_from_domain(bo, other);
     update_bytes_moved_vis = adev->mc.visible_vram_size < adev->mc.real_vram_size && bo->tbo.mem.mem_type == TTM_PL_VRAM && bo->tbo.mem.start<adev->mc.visible_vram_size> > PAGE_SHIFT;
     initial_bytes_moved = atomic64_read(&adev->num_bytes_moved);
-    r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+    r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
     bytes_moved = atomic64_read(&adev->num_bytes_moved) - initial_bytes_moved;
     p->bytes_moved += bytes_moved;
     if (update_bytes_moved_vis) p->bytes_moved_vis += bytes_moved;
     if (unlikely(r)) break;
     p->evictable = list_prev_entry(p->evictable, tv.head);
     list_move(&candidate->tv.head, &p->validated);
     return true;
   }
   return false;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,48 +1,49 @@
 int amdgpu_gem_userptr_ioctl(struct drm_device *dev, void *data, struct drm_file *filp) {
+  struct ttm_operation_ctx ctx = {true, false};
   struct amdgpu_device *adev = dev->dev_private;
   struct drm_amdgpu_gem_userptr *args = data;
   struct drm_gem_object *gobj;
   struct amdgpu_bo *bo;
   uint32_t handle;
   int r;
   if (offset_in_page(args->addr | args->size)) return -EINVAL;
   /* reject unknown flag values */
   if (args->flags & ~(AMDGPU_GEM_USERPTR_READONLY | AMDGPU_GEM_USERPTR_ANONONLY | AMDGPU_GEM_USERPTR_VALIDATE | AMDGPU_GEM_USERPTR_REGISTER)) return -EINVAL;
   if (!(args->flags & AMDGPU_GEM_USERPTR_READONLY) && !(args->flags & AMDGPU_GEM_USERPTR_REGISTER)) {
     /* if we want to write to it we must install a MMU notifier */
     return -EACCES;
   }
   /* create a gem object to contain this object in */
   r = amdgpu_gem_object_create(adev, args->size, 0, AMDGPU_GEM_DOMAIN_CPU, 0, 0, NULL, &gobj);
   if (r) return r;
   bo = gem_to_amdgpu_bo(gobj);
   bo->preferred_domains = AMDGPU_GEM_DOMAIN_GTT;
   bo->allowed_domains = AMDGPU_GEM_DOMAIN_GTT;
   r = amdgpu_ttm_tt_set_userptr(bo->tbo.ttm, args->addr, args->flags);
   if (r) goto release_object;
   if (args->flags & AMDGPU_GEM_USERPTR_REGISTER) {
     r = amdgpu_mn_register(bo, args->addr);
     if (r) goto release_object;
   }
   if (args->flags & AMDGPU_GEM_USERPTR_VALIDATE) {
     r = amdgpu_ttm_tt_get_user_pages(bo->tbo.ttm, bo->tbo.ttm->pages);
     if (r) goto release_object;
     r = amdgpu_bo_reserve(bo, true);
     if (r) goto free_pages;
     amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_GTT);
-    r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+    r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
     amdgpu_bo_unreserve(bo);
     if (r) goto free_pages;
   }
   r = drm_gem_handle_create(filp, gobj, &handle);
   /* drop reference from allocate - handle holds it now */
   drm_gem_object_put_unlocked(gobj);
   if (r) return r;
   args->handle = handle;
   return 0;
 free_pages:
   release_pages(bo->tbo.ttm->pages, bo->tbo.ttm->num_pages);
 release_object:
   drm_gem_object_put_unlocked(gobj);
   return r;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,28 +1,29 @@
 int amdgpu_bo_fault_reserve_notify(struct ttm_buffer_object *bo) {
+  struct ttm_operation_ctx ctx = {false, false};
   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->bdev);
   struct amdgpu_bo *abo;
   unsigned long offset, size;
   int r;
   if (!amdgpu_ttm_bo_is_amdgpu_bo(bo)) return 0;
   abo = ttm_to_amdgpu_bo(bo);
   /* Remember that this BO was accessed by the CPU */
   abo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
   if (bo->mem.mem_type != TTM_PL_VRAM) return 0;
   size = bo->mem.num_pages << PAGE_SHIFT;
   offset = bo->mem.start << PAGE_SHIFT;
   if ((offset + size) <= adev->mc.visible_vram_size) return 0;
   /* Can't move a pinned BO to visible VRAM */
   if (abo->pin_count > 0) return -EINVAL;
   /* hurrah the memory is not visible ! */
   atomic64_inc(&adev->num_vram_cpu_page_faults);
   amdgpu_ttm_placement_from_domain(abo, AMDGPU_GEM_DOMAIN_VRAM | AMDGPU_GEM_DOMAIN_GTT);
   /* Avoid costly evictions; only set GTT as a busy placement */
   abo->placement.num_busy_placement = 1;
   abo->placement.busy_placement = &abo->placements[1];
-  r = ttm_bo_validate(bo, &abo->placement, false, false);
+  r = ttm_bo_validate(bo, &abo->placement, &ctx);
   if (unlikely(r != 0)) return r;
   offset = bo->mem.start << PAGE_SHIFT;
   /* this should never happen */
   if (bo->mem.mem_type == TTM_PL_VRAM && (offset + size) > adev->mc.visible_vram_size) return -EINVAL;
   return 0;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,52 +1,53 @@
 int amdgpu_bo_pin_restricted(struct amdgpu_bo *bo, u32 domain, u64 min_offset, u64 max_offset, u64 *gpu_addr) {
+  struct ttm_operation_ctx ctx = {false, false};
   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
   int r, i;
   if (amdgpu_ttm_tt_get_usermm(bo->tbo.ttm)) return -EPERM;
   if (WARN_ON_ONCE(min_offset > max_offset)) return -EINVAL;
   /* A shared bo cannot be migrated to VRAM */
   if (bo->prime_shared_count && (domain == AMDGPU_GEM_DOMAIN_VRAM)) return -EINVAL;
   if (bo->pin_count) {
     uint32_t mem_type = bo->tbo.mem.mem_type;
     if (!(domain & amdgpu_mem_type_to_domain(mem_type))) return -EINVAL;
     bo->pin_count++;
     if (gpu_addr) *gpu_addr = amdgpu_bo_gpu_offset(bo);
     if (max_offset != 0) {
       u64 domain_start = bo->tbo.bdev->man[mem_type].gpu_offset;
       WARN_ON_ONCE(max_offset < (amdgpu_bo_gpu_offset(bo) - domain_start));
     }
     return 0;
   }
   bo->flags |= AMDGPU_GEM_CREATE_VRAM_CONTIGUOUS;
   /* force to pin into visible video ram */
   if (!(bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS)) bo->flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
   amdgpu_ttm_placement_from_domain(bo, domain);
   for (i = 0; i < bo->placement.num_placement; i++) {
     unsigned fpfn, lpfn;
     fpfn = min_offset >> PAGE_SHIFT;
     lpfn = max_offset >> PAGE_SHIFT;
     if (fpfn > bo->placements[i].fpfn) bo->placements[i].fpfn = fpfn;
     if (!bo->placements[i].lpfn || (lpfn && lpfn < bo->placements[i].lpfn)) bo->placements[i].lpfn = lpfn;
     bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
   }
-  r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+  r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
   if (unlikely(r)) {
     dev_err(adev->dev, "%p pin failed\n", bo);
     goto error;
   }
   r = amdgpu_ttm_alloc_gart(&bo->tbo);
   if (unlikely(r)) {
     dev_err(adev->dev, "%p bind failed\n", bo);
     goto error;
   }
   bo->pin_count = 1;
   if (gpu_addr != NULL) *gpu_addr = amdgpu_bo_gpu_offset(bo);
   domain = amdgpu_mem_type_to_domain(bo->tbo.mem.mem_type);
   if (domain == AMDGPU_GEM_DOMAIN_VRAM) {
     adev->vram_pin_size += amdgpu_bo_size(bo);
     if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) adev->invisible_pin_size += amdgpu_bo_size(bo);
   } else if (domain == AMDGPU_GEM_DOMAIN_GTT) {
     adev->gart_pin_size += amdgpu_bo_size(bo);
   }
 error:
   return r;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,27 +1,28 @@
 int amdgpu_bo_unpin(struct amdgpu_bo *bo) {
+  struct ttm_operation_ctx ctx = {false, false};
   struct amdgpu_device *adev = amdgpu_ttm_adev(bo->tbo.bdev);
   int r, i;
   if (!bo->pin_count) {
     dev_warn(adev->dev, "%p unpin not necessary\n", bo);
     return 0;
   }
   bo->pin_count--;
   if (bo->pin_count) return 0;
   for (i = 0; i < bo->placement.num_placement; i++) {
     bo->placements[i].lpfn = 0;
     bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
   }
-  r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+  r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
   if (unlikely(r)) {
     dev_err(adev->dev, "%p validate failed for unpin\n", bo);
     goto error;
   }
   if (bo->tbo.mem.mem_type == TTM_PL_VRAM) {
     adev->vram_pin_size -= amdgpu_bo_size(bo);
     if (bo->flags & AMDGPU_GEM_CREATE_NO_CPU_ACCESS) adev->invisible_pin_size -= amdgpu_bo_size(bo);
   } else if (bo->tbo.mem.mem_type == TTM_PL_TT) {
     adev->gart_pin_size -= amdgpu_bo_size(bo);
   }
 error:
   return r;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,14 +1,15 @@
 int amdgpu_bo_validate(struct amdgpu_bo *bo) {
+  struct ttm_operation_ctx ctx = {false, false};
   uint32_t domain;
   int r;
   if (bo->pin_count) return 0;
   domain = bo->preferred_domains;
 retry:
   amdgpu_ttm_placement_from_domain(bo, domain);
-  r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+  r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
   if (unlikely(r == -ENOMEM) && domain != bo->allowed_domains) {
     domain = bo->allowed_domains;
     goto retry;
   }
   return r;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,24 +1,25 @@
 static int amdgpu_uvd_cs_pass1(struct amdgpu_uvd_cs_ctx *ctx) {
+  struct ttm_operation_ctx ctx = {false, false};
   struct amdgpu_bo_va_mapping *mapping;
   struct amdgpu_bo *bo;
   uint32_t cmd;
   uint64_t addr = amdgpu_uvd_get_addr_from_ctx(ctx);
   int r = 0;
   r = amdgpu_cs_find_mapping(ctx->parser, addr, &bo, &mapping);
   if (r) {
     DRM_ERROR("Can't find BO for addr 0x%08Lx\n", addr);
     return r;
   }
   if (!ctx->parser->adev->uvd.address_64_bit) {
     /* check if it's a message or feedback command */
     cmd = amdgpu_get_ib_value(ctx->parser, ctx->ib_idx, ctx->idx) >> 1;
     if (cmd == 0x0 || cmd == 0x3) {
       /* yes, force it into VRAM */
       uint32_t domain = AMDGPU_GEM_DOMAIN_VRAM;
       amdgpu_ttm_placement_from_domain(bo, domain);
     }
     amdgpu_uvd_force_into_uvd_segment(bo);
-    r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
+    r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
   }
   return r;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }
--- initial
+++ final
@@ -1,69 +1,70 @@
 static int amdgpu_uvd_send_msg(struct amdgpu_ring *ring, struct amdgpu_bo *bo, bool direct, struct dma_fence **fence) {
+  struct ttm_operation_ctx ctx = {true, false};
   struct ttm_validate_buffer tv;
   struct ww_acquire_ctx ticket;
   struct list_head head;
   struct amdgpu_job *job;
   struct amdgpu_ib *ib;
   struct dma_fence *f = NULL;
   struct amdgpu_device *adev = ring->adev;
   uint64_t addr;
   uint32_t data[4];
   int i, r;
   memset(&tv, 0, sizeof(tv));
   tv.bo = &bo->tbo;
   INIT_LIST_HEAD(&head);
   list_add(&tv.head, &head);
   r = ttm_eu_reserve_buffers(&ticket, &head, true, NULL);
   if (r) return r;
   if (!ring->adev->uvd.address_64_bit) {
     amdgpu_ttm_placement_from_domain(bo, AMDGPU_GEM_DOMAIN_VRAM);
     amdgpu_uvd_force_into_uvd_segment(bo);
   }
-  r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
+  r = ttm_bo_validate(&bo->tbo, &bo->placement, &ctx);
   if (r) goto err;
   r = amdgpu_job_alloc_with_ib(adev, 64, &job);
   if (r) goto err;
   if (adev->asic_type >= CHIP_VEGA10) {
     data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0_VEGA10, 0);
     data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1_VEGA10, 0);
     data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD_VEGA10, 0);
     data[3] = PACKET0(mmUVD_NO_OP_VEGA10, 0);
   } else {
     data[0] = PACKET0(mmUVD_GPCOM_VCPU_DATA0, 0);
     data[1] = PACKET0(mmUVD_GPCOM_VCPU_DATA1, 0);
     data[2] = PACKET0(mmUVD_GPCOM_VCPU_CMD, 0);
     data[3] = PACKET0(mmUVD_NO_OP, 0);
   }
   ib = &job->ibs[0];
   addr = amdgpu_bo_gpu_offset(bo);
   ib->ptr[0] = data[0];
   ib->ptr[1] = addr;
   ib->ptr[2] = data[1];
   ib->ptr[3] = addr >> 32;
   ib->ptr[4] = data[2];
   ib->ptr[5] = 0;
   for (i = 6; i < 16; i += 2) {
     ib->ptr[i] = data[3];
     ib->ptr[i + 1] = 0;
   }
   ib->length_dw = 16;
   if (direct) {
     r = amdgpu_ib_schedule(ring, 1, ib, NULL, &f);
     job->fence = dma_fence_get(f);
     if (r) goto err_free;
     amdgpu_job_free(job);
   } else {
     r = amdgpu_job_submit(job, ring, &adev->uvd.entity, AMDGPU_FENCE_OWNER_UNDEFINED, &f);
     if (r) goto err_free;
   }
   ttm_eu_fence_buffer_objects(&ticket, &head, f);
   if (fence) *fence = dma_fence_get(f);
   amdgpu_bo_unref(&bo);
   dma_fence_put(f);
   return 0;
 err_free:
   amdgpu_job_free(job);
 err:
   ttm_eu_backoff_reservation(&ticket, &head);
   return r;
 }<sep>@@
identifier f;
expression e1,e2,x,y;
symbol ctx;
@@

f(...) {
++ struct ttm_operation_ctx ctx = { e1,e2 };
<+...
               ttm_bo_validate(x,y,
-                               e1,e2
+              			&ctx
			      )
...+> }