imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,54 +1,53 @@
 int xfs_reflink_cancel_cow_blocks(struct xfs_inode *ip, struct xfs_trans **tpp, xfs_fileoff_t offset_fsb, xfs_fileoff_t end_fsb, bool cancel_real) {
   struct xfs_ifork *ifp = XFS_IFORK_PTR(ip, XFS_COW_FORK);
   struct xfs_bmbt_irec got, del;
   struct xfs_iext_cursor icur;
   xfs_fsblock_t firstfsb;
   struct xfs_defer_ops dfops;
   struct xfs_defer_ops *odfops = (*tpp)->t_dfops;
   int error = 0;
   if (!xfs_is_reflink_inode(ip)) return 0;
   if (!xfs_iext_lookup_extent_before(ip, ifp, &end_fsb, &icur, &got)) return 0;
   /* Walk backwards until we're out of the I/O range... */
   while (got.br_startoff + got.br_blockcount > offset_fsb) {
     del = got;
     xfs_trim_extent(&del, offset_fsb, end_fsb - offset_fsb);
     /* Extent delete may have bumped ext forward */
     if (!del.br_blockcount) {
       xfs_iext_prev(ifp, &icur);
       goto next_extent;
     }
     trace_xfs_reflink_cancel_cow(ip, &del);
     if (isnullstartblock(del.br_startblock)) {
       error = xfs_bmap_del_extent_delay(ip, XFS_COW_FORK, &icur, &got, &del);
       if (error) break;
     } else if (del.br_state == XFS_EXT_UNWRITTEN || cancel_real) {
-      xfs_defer_init(&dfops, &firstfsb);
-      (*tpp)->t_dfops = &dfops;
+      xfs_defer_init(*tpp, &dfops, &firstfsb);
       /* Free the CoW orphan record. */
       error = xfs_refcount_free_cow_extent(ip->i_mount, (*tpp)->t_dfops, del.br_startblock, del.br_blockcount);
       if (error) break;
       xfs_bmap_add_free(ip->i_mount, (*tpp)->t_dfops, del.br_startblock, del.br_blockcount, NULL);
       /* Roll the transaction */
       xfs_defer_ijoin((*tpp)->t_dfops, ip);
       error = xfs_defer_finish(tpp, (*tpp)->t_dfops);
       if (error) {
         xfs_defer_cancel((*tpp)->t_dfops);
         break;
       }
       /* Remove the mapping from the CoW fork. */
       xfs_bmap_del_extent_cow(ip, &icur, &got, &del);
       /* Remove the quota reservation */
       error = xfs_trans_reserve_quota_nblks(NULL, ip, -(long)del.br_blockcount, 0, XFS_QMOPT_RES_REGBLKS);
       if (error) break;
     } else {
       /* Didn't do anything, push cursor back. */
       xfs_iext_prev(ifp, &icur);
     }
   next_extent:
     if (!xfs_iext_get_extent(ifp, &icur, &got)) break;
   }
   /* clear tag if cow fork is emptied */
   if (!ifp->if_bytes) xfs_inode_clear_cowblocks_tag(ip);
   (*tpp)->t_dfops = odfops;
   return error;
 }<sep>@@
expression e1,e2,tp;
@@

-		xfs_defer_init(e1, e2);
-		(tp)->t_dfops = e1;
+		xfs_defer_init(tp, e1, e2);
--- initial
+++ final
@@ -1,91 +1,90 @@
 STATIC int xfs_inactive_symlink_rmt(struct xfs_inode *ip) {
   xfs_buf_t *bp;
   int done;
   int error;
   xfs_fsblock_t first_block;
   struct xfs_defer_ops dfops;
   int i;
   xfs_mount_t *mp;
   xfs_bmbt_irec_t mval[XFS_SYMLINK_MAPS];
   int nmaps;
   int size;
   xfs_trans_t *tp;
   mp = ip->i_mount;
   ASSERT(ip->i_df.if_flags & XFS_IFEXTENTS);
   /*
    * We're freeing a symlink that has some
    * blocks allocated to it.  Free the
    * blocks here.  We know that we've got
    * either 1 or 2 extents and that we can
    * free them all in one bunmapi call.
    */
   ASSERT(ip->i_d.di_nextents > 0 && ip->i_d.di_nextents <= 2);
   error = xfs_trans_alloc(mp, &M_RES(mp)->tr_itruncate, 0, 0, 0, &tp);
   if (error) return error;
   xfs_ilock(ip, XFS_ILOCK_EXCL);
   xfs_trans_ijoin(tp, ip, 0);
   /*
    * Lock the inode, fix the size, and join it to the transaction.
    * Hold it so in the normal path, we still have it locked for
    * the second transaction.  In the error paths we need it
    * held so the cancel won't rele it, see below.
    */
   size = (int)ip->i_d.di_size;
   ip->i_d.di_size = 0;
   xfs_trans_log_inode(tp, ip, XFS_ILOG_CORE);
   /*
    * Find the block(s) so we can inval and unmap them.
    */
   done = 0;
-  xfs_defer_init(&dfops, &first_block);
-  tp->t_dfops = &dfops;
+  xfs_defer_init(tp, &dfops, &first_block);
   nmaps = ARRAY_SIZE(mval);
   error = xfs_bmapi_read(ip, 0, xfs_symlink_blocks(mp, size), mval, &nmaps, 0);
   if (error) goto error_trans_cancel;
   /*
    * Invalidate the block(s). No validation is done.
    */
   for (i = 0; i < nmaps; i++) {
     bp = xfs_trans_get_buf(tp, mp->m_ddev_targp, XFS_FSB_TO_DADDR(mp, mval[i].br_startblock), XFS_FSB_TO_BB(mp, mval[i].br_blockcount), 0);
     if (!bp) {
       error = -ENOMEM;
       goto error_bmap_cancel;
     }
     xfs_trans_binval(tp, bp);
   }
   /*
    * Unmap the dead block(s) to the dfops.
    */
   error = xfs_bunmapi(tp, ip, 0, size, 0, nmaps, &first_block, &done);
   if (error) goto error_bmap_cancel;
   ASSERT(done);
   /*
    * Commit the first transaction.  This logs the EFI and the inode.
    */
   xfs_defer_ijoin(tp->t_dfops, ip);
   error = xfs_defer_finish(&tp, tp->t_dfops);
   if (error) goto error_bmap_cancel;
   /*
    * Commit the transaction containing extent freeing and EFDs.
    */
   xfs_trans_log_inode(tp, ip, XFS_ILOG_CORE);
   error = xfs_trans_commit(tp);
   if (error) {
     ASSERT(XFS_FORCED_SHUTDOWN(mp));
     goto error_unlock;
   }
   /*
    * Remove the memory for extent descriptions (just bookkeeping).
    */
   if (ip->i_df.if_bytes) xfs_idata_realloc(ip, -ip->i_df.if_bytes, XFS_DATA_FORK);
   ASSERT(ip->i_df.if_bytes == 0);
   xfs_iunlock(ip, XFS_ILOCK_EXCL);
   return 0;
 error_bmap_cancel:
   xfs_defer_cancel(tp->t_dfops);
 error_trans_cancel:
   xfs_trans_cancel(tp);
 error_unlock:
   xfs_iunlock(ip, XFS_ILOCK_EXCL);
   return error;
 }<sep>@@
expression e1,e2,tp;
@@

-		xfs_defer_init(e1, e2);
-		(tp)->t_dfops = e1;
+		xfs_defer_init(tp, e1, e2);
--- initial
+++ final
@@ -1,8 +1,8 @@
 struct dma_buf *armada_gem_prime_export(struct drm_device *dev, struct drm_gem_object *obj, int flags) {
   DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
   exp_info.ops = &armada_gem_prime_dmabuf_ops;
   exp_info.size = obj->size;
   exp_info.flags = O_RDWR;
   exp_info.priv = obj;
-  return dma_buf_export(&exp_info);
+  return drm_gem_dmabuf_export(dev, &exp_info);
 }<sep>@@
identifier f,dev;
expression e;
@@

f(...,struct drm_device *dev,...) {
  ...
- dma_buf_export(e)
+ drm_gem_dmabuf_export(dev, e)
  ...
}
--- initial
+++ final
@@ -1,12 +1,12 @@
 struct dma_buf *drm_gem_prime_export(struct drm_device *dev, struct drm_gem_object *obj, int flags) {
   struct dma_buf_export_info exp_info = {
       .exp_name = KBUILD_MODNAME, /* white lie for debug */
       .owner = dev->driver->fops->owner,
       .ops = &drm_gem_prime_dmabuf_ops,
       .size = obj->size,
       .flags = flags,
       .priv = obj,
   };
   if (dev->driver->gem_prime_res_obj) exp_info.resv = dev->driver->gem_prime_res_obj(obj);
-  return dma_buf_export(&exp_info);
+  return drm_gem_dmabuf_export(dev, &exp_info);
 }<sep>@@
identifier f,dev;
expression e;
@@

f(...,struct drm_device *dev,...) {
  ...
- dma_buf_export(e)
+ drm_gem_dmabuf_export(dev, e)
  ...
}
--- initial
+++ final
@@ -1,8 +1,8 @@
 struct dma_buf *tegra_gem_prime_export(struct drm_device *drm, struct drm_gem_object *gem, int flags) {
   DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
   exp_info.ops = &tegra_gem_prime_dmabuf_ops;
   exp_info.size = gem->size;
   exp_info.flags = flags;
   exp_info.priv = gem;
-  return dma_buf_export(&exp_info);
+  return drm_gem_dmabuf_export(drm, &exp_info);
 }<sep>@@
identifier f,dev;
expression e;
@@

f(...,struct drm_device *dev,...) {
  ...
- dma_buf_export(e)
+ drm_gem_dmabuf_export(dev, e)
  ...
}
--- initial
+++ final
@@ -1,17 +1,17 @@
 struct dma_buf *i915_gem_prime_export(struct drm_device *dev, struct drm_gem_object *gem_obj, int flags) {
   struct drm_i915_gem_object *obj = to_intel_bo(gem_obj);
   DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
   struct dma_buf *dma_buf;
   exp_info.ops = &i915_dmabuf_ops;
   exp_info.size = gem_obj->size;
   exp_info.flags = flags;
   exp_info.priv = gem_obj;
   if (obj->ops->dmabuf_export) {
     int ret = obj->ops->dmabuf_export(obj);
     if (ret) return ERR_PTR(ret);
   }
-  dma_buf = dma_buf_export(&exp_info);
+  dma_buf = drm_gem_dmabuf_export(dev, &exp_info);
   if (IS_ERR(dma_buf)) return dma_buf;
   export_fences(obj, dma_buf);
   return dma_buf;
 }<sep>@@
identifier f,dev;
expression e;
@@

f(...,struct drm_device *dev,...) {
  ...
- dma_buf_export(e)
+ drm_gem_dmabuf_export(dev, e)
  ...
}
--- initial
+++ final
@@ -1,8 +1,8 @@
 struct dma_buf *udl_gem_prime_export(struct drm_device *dev, struct drm_gem_object *obj, int flags) {
   DEFINE_DMA_BUF_EXPORT_INFO(exp_info);
   exp_info.ops = &udl_dmabuf_ops;
   exp_info.size = obj->size;
   exp_info.flags = flags;
   exp_info.priv = obj;
-  return dma_buf_export(&exp_info);
+  return drm_gem_dmabuf_export(dev, &exp_info);
 }<sep>@@
identifier f,dev;
expression e;
@@

f(...,struct drm_device *dev,...) {
  ...
- dma_buf_export(e)
+ drm_gem_dmabuf_export(dev, e)
  ...
}
--- initial
+++ final
@@ -1,41 +1,41 @@
 static int amdgpu_ctx_init(struct amdgpu_device *adev, enum drm_sched_priority priority, struct drm_file *filp, struct amdgpu_ctx *ctx) {
   unsigned i, j;
   int r;
   if (priority < 0 || priority >= DRM_SCHED_PRIORITY_MAX) return -EINVAL;
   r = amdgpu_ctx_priority_permit(filp, priority);
   if (r) return r;
   memset(ctx, 0, sizeof(*ctx));
   ctx->adev = adev;
   kref_init(&ctx->refcount);
   spin_lock_init(&ctx->ring_lock);
   ctx->fences = kcalloc(amdgpu_sched_jobs * AMDGPU_MAX_RINGS, sizeof(struct dma_fence *), GFP_KERNEL);
   if (!ctx->fences) return -ENOMEM;
   mutex_init(&ctx->lock);
   for (i = 0; i < AMDGPU_MAX_RINGS; ++i) {
     ctx->rings[i].sequence = 1;
     ctx->rings[i].fences = &ctx->fences[amdgpu_sched_jobs * i];
   }
   ctx->reset_counter = atomic_read(&adev->gpu_reset_counter);
   ctx->reset_counter_query = ctx->reset_counter;
   ctx->vram_lost_counter = atomic_read(&adev->vram_lost_counter);
   ctx->init_priority = priority;
   ctx->override_priority = DRM_SCHED_PRIORITY_UNSET;
   /* create context entity for each ring */
   for (i = 0; i < adev->num_rings; i++) {
     struct amdgpu_ring *ring = adev->rings[i];
     struct drm_sched_rq *rq;
     rq = &ring->sched.sched_rq[priority];
     if (ring == &adev->gfx.kiq.ring) continue;
-    r = drm_sched_entity_init(&ring->sched, &ctx->rings[i].entity, rq, amdgpu_sched_jobs, &ctx->guilty);
+    r = drm_sched_entity_init(&ring->sched, &ctx->rings[i].entity, rq, &ctx->guilty);
     if (r) goto failed;
   }
   r = amdgpu_queue_mgr_init(adev, &ctx->queue_mgr);
   if (r) goto failed;
   return 0;
 failed:
   for (j = 0; j < i; j++)
     drm_sched_entity_fini(&adev->rings[j]->sched, &ctx->rings[j].entity);
   kfree(ctx->fences);
   ctx->fences = NULL;
   return r;
 }<sep>@@
expression e1,e2,e3,e4,d;
@@

 	drm_sched_entity_init(e1,e2,e3,
- 				  d,
 				  e4)
--- initial
+++ final
@@ -1,45 +1,45 @@
 static int amdgpu_ttm_global_init(struct amdgpu_device *adev) {
   struct drm_global_reference *global_ref;
   struct amdgpu_ring *ring;
   struct drm_sched_rq *rq;
   int r;
   adev->mman.mem_global_referenced = false;
   global_ref = &adev->mman.mem_global_ref;
   global_ref->global_type = DRM_GLOBAL_TTM_MEM;
   global_ref->size = sizeof(struct ttm_mem_global);
   global_ref->init = &amdgpu_ttm_mem_global_init;
   global_ref->release = &amdgpu_ttm_mem_global_release;
   r = drm_global_item_ref(global_ref);
   if (r) {
     DRM_ERROR("Failed setting up TTM memory accounting "
               "subsystem.\n");
     goto error_mem;
   }
   adev->mman.bo_global_ref.mem_glob = adev->mman.mem_global_ref.object;
   global_ref = &adev->mman.bo_global_ref.ref;
   global_ref->global_type = DRM_GLOBAL_TTM_BO;
   global_ref->size = sizeof(struct ttm_bo_global);
   global_ref->init = &ttm_bo_global_init;
   global_ref->release = &ttm_bo_global_release;
   r = drm_global_item_ref(global_ref);
   if (r) {
     DRM_ERROR("Failed setting up TTM BO subsystem.\n");
     goto error_bo;
   }
   mutex_init(&adev->mman.gtt_window_lock);
   ring = adev->mman.buffer_funcs_ring;
   rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_KERNEL];
-  r = drm_sched_entity_init(&ring->sched, &adev->mman.entity, rq, amdgpu_sched_jobs, NULL);
+  r = drm_sched_entity_init(&ring->sched, &adev->mman.entity, rq, NULL);
   if (r) {
     DRM_ERROR("Failed setting up TTM BO move run queue.\n");
     goto error_entity;
   }
   adev->mman.mem_global_referenced = true;
   return 0;
 error_entity:
   drm_global_item_unref(&adev->mman.bo_global_ref.ref);
 error_bo:
   drm_global_item_unref(&adev->mman.mem_global_ref);
 error_mem:
   return r;
 }<sep>@@
expression e1,e2,e3,e4,d;
@@

 	drm_sched_entity_init(e1,e2,e3,
- 				  d,
 				  e4)
--- initial
+++ final
@@ -1,66 +1,66 @@
 int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size) {
   struct amdgpu_ring *ring;
   struct drm_sched_rq *rq;
   const char *fw_name;
   const struct common_firmware_header *hdr;
   unsigned ucode_version, version_major, version_minor, binary_id;
   int i, r;
   switch (adev->asic_type) {
 #ifdef CONFIG_DRM_AMDGPU_CIK
   case CHIP_BONAIRE: fw_name = FIRMWARE_BONAIRE; break;
   case CHIP_KAVERI: fw_name = FIRMWARE_KAVERI; break;
   case CHIP_KABINI: fw_name = FIRMWARE_KABINI; break;
   case CHIP_HAWAII: fw_name = FIRMWARE_HAWAII; break;
   case CHIP_MULLINS: fw_name = FIRMWARE_MULLINS; break;
 #endif
   case CHIP_TONGA: fw_name = FIRMWARE_TONGA; break;
   case CHIP_CARRIZO: fw_name = FIRMWARE_CARRIZO; break;
   case CHIP_FIJI: fw_name = FIRMWARE_FIJI; break;
   case CHIP_STONEY: fw_name = FIRMWARE_STONEY; break;
   case CHIP_POLARIS10: fw_name = FIRMWARE_POLARIS10; break;
   case CHIP_POLARIS11: fw_name = FIRMWARE_POLARIS11; break;
   case CHIP_POLARIS12: fw_name = FIRMWARE_POLARIS12; break;
   case CHIP_VEGAM: fw_name = FIRMWARE_VEGAM; break;
   case CHIP_VEGA10: fw_name = FIRMWARE_VEGA10; break;
   case CHIP_VEGA12: fw_name = FIRMWARE_VEGA12; break;
   default: return -EINVAL;
   }
   r = request_firmware(&adev->vce.fw, fw_name, adev->dev);
   if (r) {
     dev_err(adev->dev, "amdgpu_vce: Can't load firmware \"%s\"\n", fw_name);
     return r;
   }
   r = amdgpu_ucode_validate(adev->vce.fw);
   if (r) {
     dev_err(adev->dev, "amdgpu_vce: Can't validate firmware \"%s\"\n", fw_name);
     release_firmware(adev->vce.fw);
     adev->vce.fw = NULL;
     return r;
   }
   hdr = (const struct common_firmware_header *)adev->vce.fw->data;
   ucode_version = le32_to_cpu(hdr->ucode_version);
   version_major = (ucode_version >> 20) & 0xfff;
   version_minor = (ucode_version >> 8) & 0xfff;
   binary_id = ucode_version & 0xff;
   DRM_INFO("Found VCE firmware Version: %hhd.%hhd Binary ID: %hhd\n", version_major, version_minor, binary_id);
   adev->vce.fw_version = ((version_major << 24) | (version_minor << 16) | (binary_id << 8));
   r = amdgpu_bo_create_kernel(adev, size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, &adev->vce.vcpu_bo, &adev->vce.gpu_addr, &adev->vce.cpu_addr);
   if (r) {
     dev_err(adev->dev, "(%d) failed to allocate VCE bo\n", r);
     return r;
   }
   ring = &adev->vce.ring[0];
   rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-  r = drm_sched_entity_init(&ring->sched, &adev->vce.entity, rq, amdgpu_sched_jobs, NULL);
+  r = drm_sched_entity_init(&ring->sched, &adev->vce.entity, rq, NULL);
   if (r != 0) {
     DRM_ERROR("Failed setting up VCE run queue.\n");
     return r;
   }
   for (i = 0; i < AMDGPU_MAX_VCE_HANDLES; ++i) {
     atomic_set(&adev->vce.handles[i], 0);
     adev->vce.filp[i] = NULL;
   }
   INIT_DELAYED_WORK(&adev->vce.idle_work, amdgpu_vce_idle_work_handler);
   mutex_init(&adev->vce.idle_mutex);
   return 0;
 }<sep>@@
expression e1,e2,e3,e4,d;
@@

 	drm_sched_entity_init(e1,e2,e3,
- 				  d,
 				  e4)
--- initial
+++ final
@@ -1,52 +1,52 @@
 int amdgpu_vcn_sw_init(struct amdgpu_device *adev) {
   struct amdgpu_ring *ring;
   struct drm_sched_rq *rq;
   unsigned long bo_size;
   const char *fw_name;
   const struct common_firmware_header *hdr;
   unsigned version_major, version_minor, family_id;
   int r;
   INIT_DELAYED_WORK(&adev->vcn.idle_work, amdgpu_vcn_idle_work_handler);
   switch (adev->asic_type) {
   case CHIP_RAVEN: fw_name = FIRMWARE_RAVEN; break;
   default: return -EINVAL;
   }
   r = request_firmware(&adev->vcn.fw, fw_name, adev->dev);
   if (r) {
     dev_err(adev->dev, "amdgpu_vcn: Can't load firmware \"%s\"\n", fw_name);
     return r;
   }
   r = amdgpu_ucode_validate(adev->vcn.fw);
   if (r) {
     dev_err(adev->dev, "amdgpu_vcn: Can't validate firmware \"%s\"\n", fw_name);
     release_firmware(adev->vcn.fw);
     adev->vcn.fw = NULL;
     return r;
   }
   hdr = (const struct common_firmware_header *)adev->vcn.fw->data;
   family_id = le32_to_cpu(hdr->ucode_version) & 0xff;
   version_major = (le32_to_cpu(hdr->ucode_version) >> 24) & 0xff;
   version_minor = (le32_to_cpu(hdr->ucode_version) >> 8) & 0xff;
   DRM_INFO("Found VCN firmware Version: %hu.%hu Family ID: %hu\n", version_major, version_minor, family_id);
   bo_size = AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(hdr->ucode_size_bytes) + 8) + AMDGPU_VCN_STACK_SIZE + AMDGPU_VCN_HEAP_SIZE + AMDGPU_VCN_SESSION_SIZE * 40;
   r = amdgpu_bo_create_kernel(adev, bo_size, PAGE_SIZE, AMDGPU_GEM_DOMAIN_VRAM, &adev->vcn.vcpu_bo, &adev->vcn.gpu_addr, &adev->vcn.cpu_addr);
   if (r) {
     dev_err(adev->dev, "(%d) failed to allocate vcn bo\n", r);
     return r;
   }
   ring = &adev->vcn.ring_dec;
   rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-  r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_dec, rq, amdgpu_sched_jobs, NULL);
+  r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_dec, rq, NULL);
   if (r != 0) {
     DRM_ERROR("Failed setting up VCN dec run queue.\n");
     return r;
   }
   ring = &adev->vcn.ring_enc[0];
   rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-  r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_enc, rq, amdgpu_sched_jobs, NULL);
+  r = drm_sched_entity_init(&ring->sched, &adev->vcn.entity_enc, rq, NULL);
   if (r != 0) {
     DRM_ERROR("Failed setting up VCN enc run queue.\n");
     return r;
   }
   return 0;
 }<sep>@@
expression e1,e2,e3,e4,d;
@@

 	drm_sched_entity_init(e1,e2,e3,
- 				  d,
 				  e4)
--- initial
+++ final
@@ -1,13 +1,13 @@
 static int etnaviv_open(struct drm_device *dev, struct drm_file *file) {
   struct etnaviv_drm_private *priv = dev->dev_private;
   struct etnaviv_file_private *ctx;
   int i;
   ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
   if (!ctx) return -ENOMEM;
   for (i = 0; i < ETNA_MAX_PIPES; i++) {
     struct etnaviv_gpu *gpu = priv->gpu[i];
-    if (gpu) { drm_sched_entity_init(&gpu->sched, &ctx->sched_entity[i], &gpu->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL], 32, NULL); }
+    if (gpu) { drm_sched_entity_init(&gpu->sched, &ctx->sched_entity[i], &gpu->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL], NULL); }
   }
   file->driver_priv = ctx;
   return 0;
 }<sep>@@
expression e1,e2,e3,e4,d;
@@

 	drm_sched_entity_init(e1,e2,e3,
- 				  d,
 				  e4)
--- initial
+++ final
@@ -1,48 +1,48 @@
 static int uvd_v6_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   int i, r;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   /* UVD TRAP */
   r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, 124, &adev->uvd.irq);
   if (r) return r;
   /* UVD ENC TRAP */
   if (uvd_v6_0_enc_support(adev)) {
     for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
       r = amdgpu_irq_add_id(adev, AMDGPU_IH_CLIENTID_LEGACY, i + 119, &adev->uvd.irq);
       if (r) return r;
     }
   }
   r = amdgpu_uvd_sw_init(adev);
   if (r) return r;
   if (!uvd_v6_0_enc_support(adev)) {
     for (i = 0; i < adev->uvd.num_enc_rings; ++i)
       adev->uvd.ring_enc[i].funcs = NULL;
     adev->uvd.irq.num_types = 1;
     adev->uvd.num_enc_rings = 0;
     DRM_INFO("UVD ENC is disabled\n");
   } else {
     struct drm_sched_rq *rq;
     ring = &adev->uvd.ring_enc[0];
     rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-    r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc, rq, amdgpu_sched_jobs, NULL);
+    r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc, rq, NULL);
     if (r) {
       DRM_ERROR("Failed setting up UVD ENC run queue.\n");
       return r;
     }
   }
   r = amdgpu_uvd_resume(adev);
   if (r) return r;
   ring = &adev->uvd.ring;
   sprintf(ring->name, "uvd");
   r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
   if (r) return r;
   if (uvd_v6_0_enc_support(adev)) {
     for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
       ring = &adev->uvd.ring_enc[i];
       sprintf(ring->name, "uvd_enc%d", i);
       r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
       if (r) return r;
     }
   }
   return r;
 }<sep>@@
expression e1,e2,e3,e4,d;
@@

 	drm_sched_entity_init(e1,e2,e3,
- 				  d,
 				  e4)
--- initial
+++ final
@@ -1,58 +1,58 @@
 static int uvd_v7_0_sw_init(void *handle) {
   struct amdgpu_ring *ring;
   struct drm_sched_rq *rq;
   int i, r;
   struct amdgpu_device *adev = (struct amdgpu_device *)handle;
   /* UVD TRAP */
   r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UVD, 124, &adev->uvd.irq);
   if (r) return r;
   /* UVD ENC TRAP */
   for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
     r = amdgpu_irq_add_id(adev, SOC15_IH_CLIENTID_UVD, i + 119, &adev->uvd.irq);
     if (r) return r;
   }
   r = amdgpu_uvd_sw_init(adev);
   if (r) return r;
   if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
     const struct common_firmware_header *hdr;
     hdr = (const struct common_firmware_header *)adev->uvd.fw->data;
     adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].ucode_id = AMDGPU_UCODE_ID_UVD;
     adev->firmware.ucode[AMDGPU_UCODE_ID_UVD].fw = adev->uvd.fw;
     adev->firmware.fw_size += ALIGN(le32_to_cpu(hdr->ucode_size_bytes), PAGE_SIZE);
     DRM_INFO("PSP loading UVD firmware\n");
   }
   ring = &adev->uvd.ring_enc[0];
   rq = &ring->sched.sched_rq[DRM_SCHED_PRIORITY_NORMAL];
-  r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc, rq, amdgpu_sched_jobs, NULL);
+  r = drm_sched_entity_init(&ring->sched, &adev->uvd.entity_enc, rq, NULL);
   if (r) {
     DRM_ERROR("Failed setting up UVD ENC run queue.\n");
     return r;
   }
   r = amdgpu_uvd_resume(adev);
   if (r) return r;
   if (!amdgpu_sriov_vf(adev)) {
     ring = &adev->uvd.ring;
     sprintf(ring->name, "uvd");
     r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
     if (r) return r;
   }
   for (i = 0; i < adev->uvd.num_enc_rings; ++i) {
     ring = &adev->uvd.ring_enc[i];
     sprintf(ring->name, "uvd_enc%d", i);
     if (amdgpu_sriov_vf(adev)) {
       ring->use_doorbell = true;
       /* currently only use the first enconding ring for
        * sriov, so set unused location for other unused rings.
        */
       if (i == 0)
         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING0_1 * 2;
       else
         ring->doorbell_index = AMDGPU_DOORBELL64_UVD_RING2_3 * 2 + 1;
     }
     r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.irq, 0);
     if (r) return r;
   }
   r = amdgpu_virt_alloc_mm_table(adev);
   if (r) return r;
   return r;
 }<sep>@@
expression e1,e2,e3,e4,d;
@@

 	drm_sched_entity_init(e1,e2,e3,
- 				  d,
 				  e4)
--- initial
+++ final
@@ -1,20 +1,18 @@
 int mmc_gpiod_request_cd(struct mmc_host *host, const char *con_id, unsigned int idx, bool override_active_level, unsigned int debounce) {
   struct mmc_gpio *ctx;
   struct gpio_desc *desc;
   int ret;
   ret = mmc_gpio_alloc(host);
   if (ret < 0) return ret;
   ctx = host->slot.handler_priv;
   if (!con_id) con_id = ctx->cd_label;
-  desc = devm_gpiod_get_index(host->parent, con_id, idx);
+  desc = devm_gpiod_get_index(host->parent, con_id, idx, GPIOD_IN);
   if (IS_ERR(desc)) return PTR_ERR(desc);
-  ret = gpiod_direction_input(desc);
-  if (ret < 0) return ret;
   if (debounce) {
     ret = gpiod_set_debounce(desc, debounce);
     if (ret < 0) return ret;
   }
   ctx->override_cd_active_level = override_active_level;
   ctx->cd_gpio = desc;
   return 0;
 }<sep>@@
expression e1,e2,e3,gpio,ret;
statement S;
@@

-	gpio = devm_gpiod_get_index(e1, e2, e3);
+	gpio = devm_gpiod_get_index(e1, e2, e3, GPIOD_IN);
	...
-	ret = gpiod_direction_input(gpio);
-	if (\(ret\|ret < 0\)) S