--- initial
+++ final
@@ -1,76 +1,76 @@
 static void __init titan_init_one_pachip_port(titan_pachip_port *port, int index) {
   struct pci_controller *hose;
   hose = alloc_pci_controller();
   if (index == 0) pci_isa_hose = hose;
   hose->io_space = alloc_resource();
   hose->mem_space = alloc_resource();
   /*
    * This is for userland consumption.  The 40-bit PIO bias that we
    * use in the kernel through KSEG doesn't work in the page table
    * based user mappings. (43-bit KSEG sign extends the physical
    * address from bit 40 to hit the I/O bit - mapped addresses don't).
    * So make sure we get the 43-bit PIO bias.
    */
   hose->sparse_mem_base = 0;
   hose->sparse_io_base = 0;
   hose->dense_mem_base = (TITAN_MEM(index) & 0xffffffffffUL) | 0x80000000000UL;
   hose->dense_io_base = (TITAN_IO(index) & 0xffffffffffUL) | 0x80000000000UL;
   hose->config_space_base = TITAN_CONF(index);
   hose->index = index;
   hose->io_space->start = TITAN_IO(index) - TITAN_IO_BIAS;
   hose->io_space->end = hose->io_space->start + TITAN_IO_SPACE - 1;
   hose->io_space->name = pci_io_names[index];
   hose->io_space->flags = IORESOURCE_IO;
   hose->mem_space->start = TITAN_MEM(index) - TITAN_MEM_BIAS;
   hose->mem_space->end = hose->mem_space->start + 0xffffffff;
   hose->mem_space->name = pci_mem_names[index];
   hose->mem_space->flags = IORESOURCE_MEM;
   if (request_resource(&ioport_resource, hose->io_space) < 0) printk(KERN_ERR "Failed to request IO on hose %d\n", index);
   if (request_resource(&iomem_resource, hose->mem_space) < 0) printk(KERN_ERR "Failed to request MEM on hose %d\n", index);
   /*
    * Save the existing PCI window translations.  SRM will
    * need them when we go to reboot.
    */
   saved_config[index].wsba[0] = port->wsba[0].csr;
   saved_config[index].wsm[0] = port->wsm[0].csr;
   saved_config[index].tba[0] = port->tba[0].csr;
   saved_config[index].wsba[1] = port->wsba[1].csr;
   saved_config[index].wsm[1] = port->wsm[1].csr;
   saved_config[index].tba[1] = port->tba[1].csr;
   saved_config[index].wsba[2] = port->wsba[2].csr;
   saved_config[index].wsm[2] = port->wsm[2].csr;
   saved_config[index].tba[2] = port->tba[2].csr;
   saved_config[index].wsba[3] = port->wsba[3].csr;
   saved_config[index].wsm[3] = port->wsm[3].csr;
   saved_config[index].tba[3] = port->tba[3].csr;
   /*
    * Set up the PCI to main memory translation windows.
    *
    * Note: Window 3 on Titan is Scatter-Gather ONLY.
    *
    * Window 0 is scatter-gather 8MB at 8MB (for isa)
    * Window 1 is direct access 1GB at 2GB
    * Window 2 is scatter-gather 1GB at 3GB
    */
-  hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, 0);
+  hose->sg_isa = iommu_arena_new(hose, 0x00800000, 0x00800000, SMP_CACHE_BYTES);
   hose->sg_isa->align_entry = 8; /* 64KB for ISA */
-  hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x40000000, 0);
+  hose->sg_pci = iommu_arena_new(hose, 0xc0000000, 0x40000000, SMP_CACHE_BYTES);
   hose->sg_pci->align_entry = 4; /* Titan caches 4 PTEs at a time */
   port->wsba[0].csr = hose->sg_isa->dma_base | 3;
   port->wsm[0].csr = (hose->sg_isa->size - 1) & 0xfff00000;
   port->tba[0].csr = virt_to_phys(hose->sg_isa->ptes);
   port->wsba[1].csr = __direct_map_base | 1;
   port->wsm[1].csr = (__direct_map_size - 1) & 0xfff00000;
   port->tba[1].csr = 0;
   port->wsba[2].csr = hose->sg_pci->dma_base | 3;
   port->wsm[2].csr = (hose->sg_pci->size - 1) & 0xfff00000;
   port->tba[2].csr = virt_to_phys(hose->sg_pci->ptes);
   port->wsba[3].csr = 0;
   /* Enable the Monster Window to make DAC pci64 possible.  */
   port->pctl.csr |= pctl_m_mwin;
   /*
    * If it's an AGP port, initialize agplastwr.
    */
   if (titan_query_agp(port)) port->port_specific.a.agplastwr.csr = __direct_map_base;
   titan_pci_tbi(hose, 0, -1);
 }<sep>@@
expression hose, base, length;
@@

-	iommu_arena_new(hose, base, length, 0)
+	iommu_arena_new(hose, base, length, SMP_CACHE_BYTES)