imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,37 +1,37 @@
 static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg) {
   int ret;
   /* Clear interrupt */
-  dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
+  dwc2_writel(hsotg, GINTSTS_WKUPINT, GINTSTS);
   dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
   dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
   if (hsotg->lx_state == DWC2_L1) {
     dwc2_wakeup_from_lpm_l1(hsotg);
     return;
   }
   if (dwc2_is_device_mode(hsotg)) {
-    dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dwc2_readl(hsotg->regs + DSTS));
+    dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dwc2_readl(hsotg, DSTS));
     if (hsotg->lx_state == DWC2_L2) {
-      u32 dctl = dwc2_readl(hsotg->regs + DCTL);
+      u32 dctl = dwc2_readl(hsotg, DCTL);
       /* Clear Remote Wakeup Signaling */
       dctl &= ~DCTL_RMTWKUPSIG;
-      dwc2_writel(dctl, hsotg->regs + DCTL);
+      dwc2_writel(hsotg, dctl, DCTL);
       ret = dwc2_exit_partial_power_down(hsotg, true);
       if (ret && (ret != -ENOTSUPP)) dev_err(hsotg->dev, "exit power_down failed\n");
       call_gadget(hsotg, resume);
     }
     /* Change to L0 state */
     hsotg->lx_state = DWC2_L0;
   } else {
     if (hsotg->params.power_down) return;
     if (hsotg->lx_state != DWC2_L1) {
-      u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
+      u32 pcgcctl = dwc2_readl(hsotg, PCGCTL);
       /* Restart the Phy Clock */
       pcgcctl &= ~PCGCTL_STOPPCLK;
-      dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
+      dwc2_writel(hsotg, pcgcctl, PCGCTL);
       mod_timer(&hsotg->wkp_timer, jiffies + msecs_to_jiffies(71));
     } else {
       /* Change to L0 state */
       hsotg->lx_state = DWC2_L0;
     }
   }
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)

@@
expression hsotg,e,v;
@@
- dwc2_writel(v, hsotg->regs + e)
+ dwc2_writel(hsotg, v, e)
--- initial
+++ final
@@ -1,56 +1,56 @@
 static int dwc2_fs_phy_init(struct dwc2_hsotg *hsotg, bool select_phy) {
   u32 usbcfg, ggpio, i2cctl;
   int retval = 0;
   /*
    * core_init() is now called on every switch so only call the
    * following for the first time through
    */
   if (select_phy) {
     dev_dbg(hsotg->dev, "FS PHY selected\n");
-    usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
+    usbcfg = dwc2_readl(hsotg, GUSBCFG);
     if (!(usbcfg & GUSBCFG_PHYSEL)) {
       usbcfg |= GUSBCFG_PHYSEL;
-      dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
+      dwc2_writel(hsotg, usbcfg, GUSBCFG);
       /* Reset after a PHY select */
       retval = dwc2_core_reset(hsotg, false);
       if (retval) {
         dev_err(hsotg->dev, "%s: Reset failed, aborting", __func__);
         return retval;
       }
     }
     if (hsotg->params.activate_stm_fs_transceiver) {
-      ggpio = dwc2_readl(hsotg->regs + GGPIO);
+      ggpio = dwc2_readl(hsotg, GGPIO);
       if (!(ggpio & GGPIO_STM32_OTG_GCCFG_PWRDWN)) {
         dev_dbg(hsotg->dev, "Activating transceiver\n");
         /*
          * STM32F4x9 uses the GGPIO register as general
          * core configuration register.
          */
         ggpio |= GGPIO_STM32_OTG_GCCFG_PWRDWN;
-        dwc2_writel(ggpio, hsotg->regs + GGPIO);
+        dwc2_writel(hsotg, ggpio, GGPIO);
       }
     }
   }
   /*
    * Program DCFG.DevSpd or HCFG.FSLSPclkSel to 48Mhz in FS. Also
    * do this on HNP Dev/Host mode switches (done in dev_init and
    * host_init).
    */
   if (dwc2_is_host_mode(hsotg)) dwc2_init_fs_ls_pclk_sel(hsotg);
   if (hsotg->params.i2c_enable) {
     dev_dbg(hsotg->dev, "FS PHY enabling I2C\n");
     /* Program GUSBCFG.OtgUtmiFsSel to I2C */
-    usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
+    usbcfg = dwc2_readl(hsotg, GUSBCFG);
     usbcfg |= GUSBCFG_OTG_UTMI_FS_SEL;
-    dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
+    dwc2_writel(hsotg, usbcfg, GUSBCFG);
     /* Program GI2CCTL.I2CEn */
-    i2cctl = dwc2_readl(hsotg->regs + GI2CCTL);
+    i2cctl = dwc2_readl(hsotg, GI2CCTL);
     i2cctl &= ~GI2CCTL_I2CDEVADDR_MASK;
     i2cctl |= 1 << GI2CCTL_I2CDEVADDR_SHIFT;
     i2cctl &= ~GI2CCTL_I2CEN;
-    dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
+    dwc2_writel(hsotg, i2cctl, GI2CCTL);
     i2cctl |= GI2CCTL_I2CEN;
-    dwc2_writel(i2cctl, hsotg->regs + GI2CCTL);
+    dwc2_writel(hsotg, i2cctl, GI2CCTL);
   }
   return retval;
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)

@@
expression hsotg,e,v;
@@
- dwc2_writel(v, hsotg->regs + e)
+ dwc2_writel(hsotg, v, e)
--- initial
+++ final
@@ -1,21 +1,21 @@
 static void dwc2_gusbcfg_init(struct dwc2_hsotg *hsotg) {
   u32 usbcfg;
-  usbcfg = dwc2_readl(hsotg->regs + GUSBCFG);
+  usbcfg = dwc2_readl(hsotg, GUSBCFG);
   usbcfg &= ~(GUSBCFG_HNPCAP | GUSBCFG_SRPCAP);
   switch (hsotg->hw_params.op_mode) {
   case GHWCFG2_OP_MODE_HNP_SRP_CAPABLE:
     if (hsotg->params.otg_cap == DWC2_CAP_PARAM_HNP_SRP_CAPABLE) usbcfg |= GUSBCFG_HNPCAP;
     if (hsotg->params.otg_cap != DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) usbcfg |= GUSBCFG_SRPCAP;
     break;
   case GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE:
   case GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE:
   case GHWCFG2_OP_MODE_SRP_CAPABLE_HOST:
     if (hsotg->params.otg_cap != DWC2_CAP_PARAM_NO_HNP_SRP_CAPABLE) usbcfg |= GUSBCFG_SRPCAP;
     break;
   case GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE:
   case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE:
   case GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST:
   default: break;
   }
-  dwc2_writel(usbcfg, hsotg->regs + GUSBCFG);
+  dwc2_writel(hsotg, usbcfg, GUSBCFG);
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)

@@
expression hsotg,e,v;
@@
- dwc2_writel(v, hsotg->regs + e)
+ dwc2_writel(hsotg, v, e)
--- initial
+++ final
@@ -1,13 +1,13 @@
 static void dwc2_enable_host_interrupts(struct dwc2_hsotg *hsotg) {
   u32 intmsk;
   dev_dbg(hsotg->dev, "%s()\n", __func__);
   /* Disable all interrupts */
-  dwc2_writel(0, hsotg->regs + GINTMSK);
-  dwc2_writel(0, hsotg->regs + HAINTMSK);
+  dwc2_writel(hsotg, 0, GINTMSK);
+  dwc2_writel(hsotg, 0, HAINTMSK);
   /* Enable the common interrupts */
   dwc2_enable_common_interrupts(hsotg);
   /* Enable host mode interrupts without disturbing common interrupts */
-  intmsk = dwc2_readl(hsotg->regs + GINTMSK);
+  intmsk = dwc2_readl(hsotg, GINTMSK);
   intmsk |= GINTSTS_DISCONNINT | GINTSTS_PRTINT | GINTSTS_HCHINT;
-  dwc2_writel(intmsk, hsotg->regs + GINTMSK);
+  dwc2_writel(hsotg, intmsk, GINTMSK);
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)

@@
expression hsotg,e,v;
@@
- dwc2_writel(v, hsotg->regs + e)
+ dwc2_writel(hsotg, v, e)
--- initial
+++ final
@@ -1,45 +1,45 @@
 irqreturn_t dwc2_handle_common_intr(int irq, void *dev) {
   struct dwc2_hsotg *hsotg = dev;
   u32 gintsts;
   irqreturn_t retval = IRQ_NONE;
   spin_lock(&hsotg->lock);
   if (!dwc2_is_controller_alive(hsotg)) {
     dev_warn(hsotg->dev, "Controller is dead\n");
     goto out;
   }
   /* Reading current frame number value in device or host modes. */
   if (dwc2_is_device_mode(hsotg))
-    hsotg->frame_number = (dwc2_readl(hsotg->regs + DSTS) & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT;
+    hsotg->frame_number = (dwc2_readl(hsotg, DSTS) & DSTS_SOFFN_MASK) >> DSTS_SOFFN_SHIFT;
   else
-    hsotg->frame_number = (dwc2_readl(hsotg->regs + HFNUM) & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
+    hsotg->frame_number = (dwc2_readl(hsotg, HFNUM) & HFNUM_FRNUM_MASK) >> HFNUM_FRNUM_SHIFT;
   gintsts = dwc2_read_common_intr(hsotg);
   if (gintsts & ~GINTSTS_PRTINT) retval = IRQ_HANDLED;
   /* In case of hibernated state gintsts must not work */
   if (hsotg->hibernated) {
     dwc2_handle_gpwrdn_intr(hsotg);
     retval = IRQ_HANDLED;
     goto out;
   }
   if (gintsts & GINTSTS_MODEMIS) dwc2_handle_mode_mismatch_intr(hsotg);
   if (gintsts & GINTSTS_OTGINT) dwc2_handle_otg_intr(hsotg);
   if (gintsts & GINTSTS_CONIDSTSCHNG) dwc2_handle_conn_id_status_change_intr(hsotg);
   if (gintsts & GINTSTS_DISCONNINT) dwc2_handle_disconnect_intr(hsotg);
   if (gintsts & GINTSTS_SESSREQINT) dwc2_handle_session_req_intr(hsotg);
   if (gintsts & GINTSTS_WKUPINT) dwc2_handle_wakeup_detected_intr(hsotg);
   if (gintsts & GINTSTS_USBSUSP) dwc2_handle_usb_suspend_intr(hsotg);
   if (gintsts & GINTSTS_LPMTRANRCVD) dwc2_handle_lpm_intr(hsotg);
   if (gintsts & GINTSTS_PRTINT) {
     /*
      * The port interrupt occurs while in device mode with HPRT0
      * Port Enable/Disable
      */
     if (dwc2_is_device_mode(hsotg)) {
       dev_dbg(hsotg->dev, " --Port interrupt received in Device mode--\n");
       dwc2_handle_usb_port_intr(hsotg);
       retval = IRQ_HANDLED;
     }
   }
 out:
   spin_unlock(&hsotg->lock);
   return retval;
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)
--- initial
+++ final
@@ -1,9 +1,9 @@
 static void dwc2_hsotg_en_gsint(struct dwc2_hsotg *hsotg, u32 ints) {
-  u32 gsintmsk = dwc2_readl(hsotg->regs + GINTMSK);
+  u32 gsintmsk = dwc2_readl(hsotg, GINTMSK);
   u32 new_gsintmsk;
   new_gsintmsk = gsintmsk | ints;
   if (new_gsintmsk != gsintmsk) {
     dev_dbg(hsotg->dev, "gsintmsk now 0x%08x\n", new_gsintmsk);
-    dwc2_writel(new_gsintmsk, hsotg->regs + GINTMSK);
+    dwc2_writel(hsotg, new_gsintmsk, GINTMSK);
   }
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)

@@
expression hsotg,e,v;
@@
- dwc2_writel(v, hsotg->regs + e)
+ dwc2_writel(hsotg, v, e)
--- initial
+++ final
@@ -1,6 +1,6 @@
 bool dwc2_is_controller_alive(struct dwc2_hsotg *hsotg) {
-  if (dwc2_readl(hsotg->regs + GSNPSID) == 0xffffffff)
+  if (dwc2_readl(hsotg, GSNPSID) == 0xffffffff)
     return false;
   else
     return true;
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)
--- initial
+++ final
@@ -1,44 +1,44 @@
 static void dwc2_hsotg_process_control(struct dwc2_hsotg *hsotg, struct usb_ctrlrequest *ctrl) {
   struct dwc2_hsotg_ep *ep0 = hsotg->eps_out[0];
   int ret = 0;
   u32 dcfg;
   dev_dbg(hsotg->dev, "ctrl Type=%02x, Req=%02x, V=%04x, I=%04x, L=%04x\n", ctrl->bRequestType, ctrl->bRequest, ctrl->wValue, ctrl->wIndex, ctrl->wLength);
   if (ctrl->wLength == 0) {
     ep0->dir_in = 1;
     hsotg->ep0_state = DWC2_EP0_STATUS_IN;
   } else if (ctrl->bRequestType & USB_DIR_IN) {
     ep0->dir_in = 1;
     hsotg->ep0_state = DWC2_EP0_DATA_IN;
   } else {
     ep0->dir_in = 0;
     hsotg->ep0_state = DWC2_EP0_DATA_OUT;
   }
   if ((ctrl->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
     switch (ctrl->bRequest) {
     case USB_REQ_SET_ADDRESS:
       hsotg->connected = 1;
-      dcfg = dwc2_readl(hsotg->regs + DCFG);
+      dcfg = dwc2_readl(hsotg, DCFG);
       dcfg &= ~DCFG_DEVADDR_MASK;
       dcfg |= (le16_to_cpu(ctrl->wValue) << DCFG_DEVADDR_SHIFT) & DCFG_DEVADDR_MASK;
-      dwc2_writel(dcfg, hsotg->regs + DCFG);
+      dwc2_writel(hsotg, dcfg, DCFG);
       dev_info(hsotg->dev, "new address %d\n", ctrl->wValue);
       ret = dwc2_hsotg_send_reply(hsotg, ep0, NULL, 0);
       return;
     case USB_REQ_GET_STATUS: ret = dwc2_hsotg_process_req_status(hsotg, ctrl); break;
     case USB_REQ_CLEAR_FEATURE:
     case USB_REQ_SET_FEATURE: ret = dwc2_hsotg_process_req_feature(hsotg, ctrl); break;
     }
   }
   /* as a fallback, try delivering it to the driver to deal with */
   if (ret == 0 && hsotg->driver) {
     spin_unlock(&hsotg->lock);
     ret = hsotg->driver->setup(&hsotg->gadget, ctrl);
     spin_lock(&hsotg->lock);
     if (ret < 0) dev_dbg(hsotg->dev, "driver->setup() ret %d\n", ret);
   }
   /*
    * the request is either unhandlable, or is not formatted correctly
    * so respond with a STALL for the status stage to indicate failure.
    */
   if (ret < 0) dwc2_hsotg_stall_ep0(hsotg);
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)

@@
expression hsotg,e,v;
@@
- dwc2_writel(v, hsotg->regs + e)
+ dwc2_writel(hsotg, v, e)
--- initial
+++ final
@@ -1,5 +1,5 @@
 static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg) {
   /* Clear interrupt */
-  dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
+  dwc2_writel(hsotg, GINTSTS_MODEMIS, GINTSTS);
   dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n", dwc2_is_host_mode(hsotg) ? "Host" : "Device");
 }<sep>@@
expression hsotg,e,v;
@@
- dwc2_writel(v, hsotg->regs + e)
+ dwc2_writel(hsotg, v, e)
--- initial
+++ final
@@ -1,15 +1,15 @@
 static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg) {
   u32 gintsts;
   u32 gintmsk;
   u32 gahbcfg;
   u32 gintmsk_common = GINTMSK_COMMON;
-  gintsts = dwc2_readl(hsotg->regs + GINTSTS);
-  gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
-  gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
+  gintsts = dwc2_readl(hsotg, GINTSTS);
+  gintmsk = dwc2_readl(hsotg, GINTMSK);
+  gahbcfg = dwc2_readl(hsotg, GAHBCFG);
   /* If any common interrupts set */
   if (gintsts & gintmsk_common) dev_dbg(hsotg->dev, "gintsts=%08x  gintmsk=%08x\n", gintsts, gintmsk);
   if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
     return gintsts & gintmsk & gintmsk_common;
   else
     return 0;
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)
--- initial
+++ final
@@ -1,15 +1,15 @@
 static void dwc2_init_fs_ls_pclk_sel(struct dwc2_hsotg *hsotg) {
   u32 hcfg, val;
   if ((hsotg->hw_params.hs_phy_type == GHWCFG2_HS_PHY_TYPE_ULPI && hsotg->hw_params.fs_phy_type == GHWCFG2_FS_PHY_TYPE_DEDICATED && hsotg->params.ulpi_fs_ls) || hsotg->params.phy_type == DWC2_PHY_TYPE_PARAM_FS) {
     /* Full speed PHY */
     val = HCFG_FSLSPCLKSEL_48_MHZ;
   } else {
     /* High speed PHY running at full speed or high speed */
     val = HCFG_FSLSPCLKSEL_30_60_MHZ;
   }
   dev_dbg(hsotg->dev, "Initializing HCFG.FSLSPClkSel to %08x\n", val);
-  hcfg = dwc2_readl(hsotg->regs + HCFG);
+  hcfg = dwc2_readl(hsotg, HCFG);
   hcfg &= ~HCFG_FSLSPCLKSEL_MASK;
   hcfg |= val << HCFG_FSLSPCLKSEL_SHIFT;
-  dwc2_writel(hcfg, hsotg->regs + HCFG);
+  dwc2_writel(hsotg, hcfg, HCFG);
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)

@@
expression hsotg,e,v;
@@
- dwc2_writel(v, hsotg->regs + e)
+ dwc2_writel(hsotg, v, e)
--- initial
+++ final
@@ -1,33 +1,33 @@
 void dwc2_hc_start_transfer_ddma(struct dwc2_hsotg *hsotg, struct dwc2_host_chan *chan) {
   u32 hcchar;
   u32 hctsiz = 0;
   if (chan->do_ping) hctsiz |= TSIZ_DOPNG;
   if (chan->ep_type == USB_ENDPOINT_XFER_ISOC) dwc2_set_pid_isoc(chan);
   /* Packet Count and Xfer Size are not used in Descriptor DMA mode */
   hctsiz |= chan->data_pid_start << TSIZ_SC_MC_PID_SHIFT & TSIZ_SC_MC_PID_MASK;
   /* 0 - 1 descriptor, 1 - 2 descriptors, etc */
   hctsiz |= (chan->ntd - 1) << TSIZ_NTD_SHIFT & TSIZ_NTD_MASK;
   /* Non-zero only for high-speed interrupt endpoints */
   hctsiz |= chan->schinfo << TSIZ_SCHINFO_SHIFT & TSIZ_SCHINFO_MASK;
   if (dbg_hc(chan)) {
     dev_vdbg(hsotg->dev, "%s: Channel %d\n", __func__, chan->hc_num);
     dev_vdbg(hsotg->dev, "	 Start PID: %d\n", chan->data_pid_start);
     dev_vdbg(hsotg->dev, "	 NTD: %d\n", chan->ntd - 1);
   }
-  dwc2_writel(hctsiz, hsotg->regs + HCTSIZ(chan->hc_num));
+  dwc2_writel(hsotg, hctsiz, HCTSIZ(chan->hc_num));
   dma_sync_single_for_device(hsotg->dev, chan->desc_list_addr, chan->desc_list_sz, DMA_TO_DEVICE);
-  dwc2_writel(chan->desc_list_addr, hsotg->regs + HCDMA(chan->hc_num));
+  dwc2_writel(hsotg, chan->desc_list_addr, HCDMA(chan->hc_num));
   if (dbg_hc(chan)) dev_vdbg(hsotg->dev, "Wrote %pad to HCDMA(%d)\n", &chan->desc_list_addr, chan->hc_num);
-  hcchar = dwc2_readl(hsotg->regs + HCCHAR(chan->hc_num));
+  hcchar = dwc2_readl(hsotg, HCCHAR(chan->hc_num));
   hcchar &= ~HCCHAR_MULTICNT_MASK;
   hcchar |= chan->multi_count << HCCHAR_MULTICNT_SHIFT & HCCHAR_MULTICNT_MASK;
   if (hcchar & HCCHAR_CHDIS) dev_warn(hsotg->dev, "%s: chdis set, channel %d, hcchar 0x%08x\n", __func__, chan->hc_num, hcchar);
   /* Set host channel enable after all other setup is complete */
   hcchar |= HCCHAR_CHENA;
   hcchar &= ~HCCHAR_CHDIS;
   if (dbg_hc(chan)) dev_vdbg(hsotg->dev, "	 Multi Cnt: %d\n", (hcchar & HCCHAR_MULTICNT_MASK) >> HCCHAR_MULTICNT_SHIFT);
-  dwc2_writel(hcchar, hsotg->regs + HCCHAR(chan->hc_num));
+  dwc2_writel(hsotg, hcchar, HCCHAR(chan->hc_num));
   if (dbg_hc(chan)) dev_vdbg(hsotg->dev, "Wrote %08x to HCCHAR(%d)\n", hcchar, chan->hc_num);
   chan->xfer_started = 1;
   chan->requests++;
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)

@@
expression hsotg,e,v;
@@
- dwc2_writel(v, hsotg->regs + e)
+ dwc2_writel(hsotg, v, e)
--- initial
+++ final
@@ -1,11 +1,11 @@
 static void dwc2_get_host_hwparams(struct dwc2_hsotg *hsotg) {
   struct dwc2_hw_params *hw = &hsotg->hw_params;
   u32 gnptxfsiz;
   u32 hptxfsiz;
   if (hsotg->dr_mode == USB_DR_MODE_PERIPHERAL) return;
   dwc2_force_mode(hsotg, true);
-  gnptxfsiz = dwc2_readl(hsotg->regs + GNPTXFSIZ);
-  hptxfsiz = dwc2_readl(hsotg->regs + HPTXFSIZ);
+  gnptxfsiz = dwc2_readl(hsotg, GNPTXFSIZ);
+  hptxfsiz = dwc2_readl(hsotg, HPTXFSIZ);
   hw->host_nperio_tx_fifo_size = (gnptxfsiz & FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
   hw->host_perio_tx_fifo_size = (hptxfsiz & FIFOSIZE_DEPTH_MASK) >> FIFOSIZE_DEPTH_SHIFT;
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)
--- initial
+++ final
@@ -1,53 +1,53 @@
 static void dwc2_hsotg_init_fifo(struct dwc2_hsotg *hsotg) {
   unsigned int ep;
   unsigned int addr;
   int timeout;
   u32 val;
   u32 *txfsz = hsotg->params.g_tx_fifo_size;
   /* Reset fifo map if not correctly cleared during previous session */
   WARN_ON(hsotg->fifo_map);
   hsotg->fifo_map = 0;
   /* set RX/NPTX FIFO sizes */
-  dwc2_writel(hsotg->params.g_rx_fifo_size, hsotg->regs + GRXFSIZ);
-  dwc2_writel((hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), hsotg->regs + GNPTXFSIZ);
+  dwc2_writel(hsotg, hsotg->params.g_rx_fifo_size, GRXFSIZ);
+  dwc2_writel(hsotg, (hsotg->params.g_rx_fifo_size << FIFOSIZE_STARTADDR_SHIFT) | (hsotg->params.g_np_tx_fifo_size << FIFOSIZE_DEPTH_SHIFT), GNPTXFSIZ);
   /*
    * arange all the rest of the TX FIFOs, as some versions of this
    * block have overlapping default addresses. This also ensures
    * that if the settings have been changed, then they are set to
    * known values.
    */
   /* start at the end of the GNPTXFSIZ, rounded up */
   addr = hsotg->params.g_rx_fifo_size + hsotg->params.g_np_tx_fifo_size;
   /*
    * Configure fifos sizes from provided configuration and assign
    * them to endpoints dynamically according to maxpacket size value of
    * given endpoint.
    */
   for (ep = 1; ep < MAX_EPS_CHANNELS; ep++) {
     if (!txfsz[ep]) continue;
     val = addr;
     val |= txfsz[ep] << FIFOSIZE_DEPTH_SHIFT;
     WARN_ONCE(addr + txfsz[ep] > hsotg->fifo_mem, "insufficient fifo memory");
     addr += txfsz[ep];
-    dwc2_writel(val, hsotg->regs + DPTXFSIZN(ep));
-    val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep));
+    dwc2_writel(hsotg, val, DPTXFSIZN(ep));
+    val = dwc2_readl(hsotg, DPTXFSIZN(ep));
   }
-  dwc2_writel(hsotg->hw_params.total_fifo_size | addr << GDFIFOCFG_EPINFOBASE_SHIFT, hsotg->regs + GDFIFOCFG);
+  dwc2_writel(hsotg, hsotg->hw_params.total_fifo_size | addr << GDFIFOCFG_EPINFOBASE_SHIFT, GDFIFOCFG);
   /*
    * according to p428 of the design guide, we need to ensure that
    * all fifos are flushed before continuing
    */
-  dwc2_writel(GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH, hsotg->regs + GRSTCTL);
+  dwc2_writel(hsotg, GRSTCTL_TXFNUM(0x10) | GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH, GRSTCTL);
   /* wait until the fifos are both flushed */
   timeout = 100;
   while (1) {
-    val = dwc2_readl(hsotg->regs + GRSTCTL);
+    val = dwc2_readl(hsotg, GRSTCTL);
     if ((val & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH)) == 0) break;
     if (--timeout == 0) {
       dev_err(hsotg->dev, "%s: timeout flushing fifos (GRSTCTL=%08x)\n", __func__, val);
       break;
     }
     udelay(1);
   }
   dev_dbg(hsotg->dev, "FIFOs reset, timeout at %d\n", timeout);
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)

@@
expression hsotg,e,v;
@@
- dwc2_writel(v, hsotg->regs + e)
+ dwc2_writel(hsotg, v, e)
--- initial
+++ final
@@ -1,14 +1,14 @@
 void dwc2_hcd_start(struct dwc2_hsotg *hsotg) {
   u32 hprt0;
   if (hsotg->op_state == OTG_STATE_B_HOST) {
     /*
      * Reset the port. During a HNP mode switch the reset
      * needs to occur within 1ms and have a duration of at
      * least 50ms.
      */
     hprt0 = dwc2_read_hprt0(hsotg);
     hprt0 |= HPRT0_RST;
-    dwc2_writel(hprt0, hsotg->regs + HPRT0);
+    dwc2_writel(hsotg, hprt0, HPRT0);
   }
   queue_delayed_work(hsotg->wq_otg, &hsotg->start_work, msecs_to_jiffies(50));
 }<sep>@@
expression hsotg,e,v;
@@
- dwc2_writel(v, hsotg->regs + e)
+ dwc2_writel(hsotg, v, e)
--- initial
+++ final
@@ -1,24 +1,24 @@
 int dwc2_restore_global_registers(struct dwc2_hsotg *hsotg) {
   struct dwc2_gregs_backup *gr;
   dev_dbg(hsotg->dev, "%s\n", __func__);
   /* Restore global regs */
   gr = &hsotg->gr_backup;
   if (!gr->valid) {
     dev_err(hsotg->dev, "%s: no global registers to restore\n", __func__);
     return -EINVAL;
   }
   gr->valid = false;
-  dwc2_writel(0xffffffff, hsotg->regs + GINTSTS);
-  dwc2_writel(gr->gotgctl, hsotg->regs + GOTGCTL);
-  dwc2_writel(gr->gintmsk, hsotg->regs + GINTMSK);
-  dwc2_writel(gr->gusbcfg, hsotg->regs + GUSBCFG);
-  dwc2_writel(gr->gahbcfg, hsotg->regs + GAHBCFG);
-  dwc2_writel(gr->grxfsiz, hsotg->regs + GRXFSIZ);
-  dwc2_writel(gr->gnptxfsiz, hsotg->regs + GNPTXFSIZ);
-  dwc2_writel(gr->gdfifocfg, hsotg->regs + GDFIFOCFG);
-  dwc2_writel(gr->pcgcctl1, hsotg->regs + PCGCCTL1);
-  dwc2_writel(gr->glpmcfg, hsotg->regs + GLPMCFG);
-  dwc2_writel(gr->pcgcctl, hsotg->regs + PCGCTL);
-  dwc2_writel(gr->gi2cctl, hsotg->regs + GI2CCTL);
+  dwc2_writel(hsotg, 0xffffffff, GINTSTS);
+  dwc2_writel(hsotg, gr->gotgctl, GOTGCTL);
+  dwc2_writel(hsotg, gr->gintmsk, GINTMSK);
+  dwc2_writel(hsotg, gr->gusbcfg, GUSBCFG);
+  dwc2_writel(hsotg, gr->gahbcfg, GAHBCFG);
+  dwc2_writel(hsotg, gr->grxfsiz, GRXFSIZ);
+  dwc2_writel(hsotg, gr->gnptxfsiz, GNPTXFSIZ);
+  dwc2_writel(hsotg, gr->gdfifocfg, GDFIFOCFG);
+  dwc2_writel(hsotg, gr->pcgcctl1, PCGCCTL1);
+  dwc2_writel(hsotg, gr->glpmcfg, GLPMCFG);
+  dwc2_writel(hsotg, gr->pcgcctl, PCGCTL);
+  dwc2_writel(hsotg, gr->gi2cctl, GI2CCTL);
   return 0;
 }<sep>@@
expression hsotg,e,v;
@@
- dwc2_writel(v, hsotg->regs + e)
+ dwc2_writel(hsotg, v, e)
--- initial
+++ final
@@ -1,8 +1,8 @@
 int dwc2_hsotg_wait_bit_clear(struct dwc2_hsotg *hsotg, u32 offset, u32 mask, u32 timeout) {
   u32 i;
   for (i = 0; i < timeout; i++) {
-    if (!(dwc2_readl(hsotg->regs + offset) & mask)) return 0;
+    if (!(dwc2_readl(hsotg, offset) & mask)) return 0;
     udelay(1);
   }
   return -ETIMEDOUT;
 }<sep>@@
expression hsotg,e;
@@

- dwc2_readl(hsotg->regs + e)
+ dwc2_readl(hsotg, e)
--- initial
+++ final
@@ -1,12 +1,12 @@
 void dwc2_flush_tx_fifo(struct dwc2_hsotg *hsotg, const int num) {
   u32 greset;
   dev_vdbg(hsotg->dev, "Flush Tx FIFO %d\n", num);
   /* Wait for AHB master IDLE state */
   if (dwc2_hsotg_wait_bit_set(hsotg, GRSTCTL, GRSTCTL_AHBIDLE, 10000)) dev_warn(hsotg->dev, "%s:  HANG! AHB Idle GRSCTL\n", __func__);
   greset = GRSTCTL_TXFFLSH;
   greset |= num << GRSTCTL_TXFNUM_SHIFT & GRSTCTL_TXFNUM_MASK;
-  dwc2_writel(greset, hsotg->regs + GRSTCTL);
+  dwc2_writel(hsotg, greset, GRSTCTL);
   if (dwc2_hsotg_wait_bit_clear(hsotg, GRSTCTL, GRSTCTL_TXFFLSH, 10000)) dev_warn(hsotg->dev, "%s:  HANG! timeout GRSTCTL GRSTCTL_TXFFLSH\n", __func__);
   /* Wait for at least 3 PHY Clocks */
   udelay(1);
 }<sep>@@
expression hsotg,e,v;
@@
- dwc2_writel(v, hsotg->regs + e)
+ dwc2_writel(hsotg, v, e)