imamnurby/smpl_train_seed8 huggingface dataset:
--- initial
+++ final
@@ -1,32 +1,32 @@
 static int nuc900_nand_probe(struct platform_device *pdev) {
   struct nuc900_nand *nuc900_nand;
   struct nand_chip *chip;
   struct mtd_info *mtd;
   struct resource *res;
   nuc900_nand = devm_kzalloc(&pdev->dev, sizeof(struct nuc900_nand), GFP_KERNEL);
   if (!nuc900_nand) return -ENOMEM;
   chip = &(nuc900_nand->chip);
   mtd = nand_to_mtd(chip);
   mtd->dev.parent = &pdev->dev;
   spin_lock_init(&nuc900_nand->lock);
   nuc900_nand->clk = devm_clk_get(&pdev->dev, NULL);
   if (IS_ERR(nuc900_nand->clk)) return -ENOENT;
   clk_enable(nuc900_nand->clk);
   chip->legacy.cmdfunc = nuc900_nand_command_lp;
   chip->legacy.dev_ready = nuc900_nand_devready;
   chip->legacy.read_byte = nuc900_nand_read_byte;
   chip->legacy.write_buf = nuc900_nand_write_buf;
   chip->legacy.read_buf = nuc900_nand_read_buf;
-  chip->chip_delay = 50;
+  chip->legacy.chip_delay = 50;
   chip->options = 0;
   chip->ecc.mode = NAND_ECC_SOFT;
   chip->ecc.algo = NAND_ECC_HAMMING;
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   nuc900_nand->reg = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(nuc900_nand->reg)) return PTR_ERR(nuc900_nand->reg);
   nuc900_nand_enable(nuc900_nand);
   if (nand_scan(chip, 1)) return -ENXIO;
   mtd_device_register(mtd, partitions, ARRAY_SIZE(partitions));
   platform_set_drvdata(pdev, nuc900_nand);
   return 0;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,74 +1,74 @@
 static int omap_nand_probe(struct platform_device *pdev) {
   struct omap_nand_info *info;
   struct mtd_info *mtd;
   struct nand_chip *nand_chip;
   int err;
   struct resource *res;
   struct device *dev = &pdev->dev;
   info = devm_kzalloc(&pdev->dev, sizeof(struct omap_nand_info), GFP_KERNEL);
   if (!info) return -ENOMEM;
   info->pdev = pdev;
   err = omap_get_dt_info(dev, info);
   if (err) return err;
   info->ops = gpmc_omap_get_nand_ops(&info->reg, info->gpmc_cs);
   if (!info->ops) {
     dev_err(&pdev->dev, "Failed to get GPMC->NAND interface\n");
     return -ENODEV;
   }
   nand_chip = &info->nand;
   mtd = nand_to_mtd(nand_chip);
   mtd->dev.parent = &pdev->dev;
   nand_chip->ecc.priv = NULL;
   nand_set_flash_node(nand_chip, dev->of_node);
   if (!mtd->name) {
     mtd->name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "omap2-nand.%d", info->gpmc_cs);
     if (!mtd->name) {
       dev_err(&pdev->dev, "Failed to set MTD name\n");
       return -ENOMEM;
     }
   }
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   nand_chip->legacy.IO_ADDR_R = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(nand_chip->legacy.IO_ADDR_R)) return PTR_ERR(nand_chip->legacy.IO_ADDR_R);
   info->phys_base = res->start;
   nand_chip->controller = &omap_gpmc_controller;
   nand_chip->legacy.IO_ADDR_W = nand_chip->legacy.IO_ADDR_R;
   nand_chip->legacy.cmd_ctrl = omap_hwcontrol;
   info->ready_gpiod = devm_gpiod_get_optional(&pdev->dev, "rb", GPIOD_IN);
   if (IS_ERR(info->ready_gpiod)) {
     dev_err(dev, "failed to get ready gpio\n");
     return PTR_ERR(info->ready_gpiod);
   }
   /*
    * If RDY/BSY line is connected to OMAP then use the omap ready
    * function and the generic nand_wait function which reads the status
    * register after monitoring the RDY/BSY line. Otherwise use a standard
    * chip delay which is slightly more than tR (AC Timing) of the NAND
    * device and read status register until you get a failure or success
    */
   if (info->ready_gpiod) {
     nand_chip->legacy.dev_ready = omap_dev_ready;
-    nand_chip->chip_delay = 0;
+    nand_chip->legacy.chip_delay = 0;
   } else {
     nand_chip->legacy.waitfunc = omap_wait;
-    nand_chip->chip_delay = 50;
+    nand_chip->legacy.chip_delay = 50;
   }
   if (info->flash_bbt) nand_chip->bbt_options |= NAND_BBT_USE_FLASH;
   /* scan NAND device connected to chip controller */
   nand_chip->options |= info->devsize & NAND_BUSWIDTH_16;
   err = nand_scan(nand_chip, 1);
   if (err) goto return_error;
   err = mtd_device_register(mtd, NULL, 0);
   if (err) goto cleanup_nand;
   platform_set_drvdata(pdev, mtd);
   return 0;
 cleanup_nand:
   nand_cleanup(nand_chip);
 return_error:
   if (!IS_ERR_OR_NULL(info->dma)) dma_release_channel(info->dma);
   if (nand_chip->ecc.priv) {
     nand_bch_free(nand_chip->ecc.priv);
     nand_chip->ecc.priv = NULL;
   }
   return err;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,65 +1,65 @@
 int bcm47xxnflash_ops_bcm4706_init(struct bcm47xxnflash *b47n) {
   struct nand_chip *nand_chip = (struct nand_chip *)&b47n->nand_chip;
   int err;
   u32 freq;
   u16 clock;
   u8 w0, w1, w2, w3, w4;
   unsigned long chipsize; /* MiB */
   u8 tbits, col_bits, col_size, row_bits, row_bsize;
   u32 val;
   b47n->nand_chip.select_chip = bcm47xxnflash_ops_bcm4706_select_chip;
   nand_chip->legacy.cmd_ctrl = bcm47xxnflash_ops_bcm4706_cmd_ctrl;
   nand_chip->legacy.dev_ready = bcm47xxnflash_ops_bcm4706_dev_ready;
   b47n->nand_chip.legacy.cmdfunc = bcm47xxnflash_ops_bcm4706_cmdfunc;
   b47n->nand_chip.legacy.read_byte = bcm47xxnflash_ops_bcm4706_read_byte;
   b47n->nand_chip.legacy.read_buf = bcm47xxnflash_ops_bcm4706_read_buf;
   b47n->nand_chip.legacy.write_buf = bcm47xxnflash_ops_bcm4706_write_buf;
   b47n->nand_chip.legacy.set_features = nand_get_set_features_notsupp;
   b47n->nand_chip.legacy.get_features = nand_get_set_features_notsupp;
-  nand_chip->chip_delay = 50;
+  nand_chip->legacy.chip_delay = 50;
   b47n->nand_chip.bbt_options = NAND_BBT_USE_FLASH;
   b47n->nand_chip.ecc.mode = NAND_ECC_NONE; /* TODO: implement ECC */
   /* Enable NAND flash access */
   bcma_cc_set32(b47n->cc, BCMA_CC_4706_FLASHSCFG, BCMA_CC_4706_FLASHSCFG_NF1);
   /* Configure wait counters */
   if (b47n->cc->status & BCMA_CC_CHIPST_4706_PKG_OPTION) {
     /* 400 MHz */
     freq = 400000000 / 4;
   } else {
     freq = bcma_chipco_pll_read(b47n->cc, 4);
     freq = (freq & 0xFFF) >> 3;
     /* Fixed reference clock 25 MHz and m = 2 */
     freq = (freq * 25000000 / 2) / 4;
   }
   clock = freq / 1000000;
   w0 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(15, clock);
   w1 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(20, clock);
   w2 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
   w3 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(10, clock);
   w4 = bcm47xxnflash_ops_bcm4706_ns_to_cycle(100, clock);
   bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_WAITCNT0, (w4 << 24 | w3 << 18 | w2 << 12 | w1 << 6 | w0));
   /* Scan NAND */
   err = nand_scan(&b47n->nand_chip, 1);
   if (err) {
     pr_err("Could not scan NAND flash: %d\n", err);
     goto exit;
   }
   /* Configure FLASH */
   chipsize = b47n->nand_chip.chipsize >> 20;
   tbits = ffs(chipsize); /* find first bit set */
   if (!tbits || tbits != fls(chipsize)) {
     pr_err("Invalid flash size: 0x%lX\n", chipsize);
     err = -ENOTSUPP;
     goto exit;
   }
   tbits += 19; /* Broadcom increases *index* by 20, we increase *pos* */
   col_bits = b47n->nand_chip.page_shift + 1;
   col_size = (col_bits + 7) / 8;
   row_bits = tbits - col_bits + 1;
   row_bsize = (row_bits + 7) / 8;
   val = ((row_bsize - 1) << 6) | ((col_size - 1) << 4) | 2;
   bcma_cc_write32(b47n->cc, BCMA_CC_NFLASH_CONF, val);
 exit:
   if (err) bcma_cc_mask32(b47n->cc, BCMA_CC_4706_FLASHSCFG, ~BCMA_CC_4706_FLASHSCFG_NF1);
   return err;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,77 +1,77 @@
 static int __init orion_nand_probe(struct platform_device *pdev) {
   struct orion_nand_info *info;
   struct mtd_info *mtd;
   struct nand_chip *nc;
   struct orion_nand_data *board;
   struct resource *res;
   void __iomem *io_base;
   int ret = 0;
   u32 val = 0;
   info = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_info), GFP_KERNEL);
   if (!info) return -ENOMEM;
   nc = &info->chip;
   mtd = nand_to_mtd(nc);
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   io_base = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(io_base)) return PTR_ERR(io_base);
   if (pdev->dev.of_node) {
     board = devm_kzalloc(&pdev->dev, sizeof(struct orion_nand_data), GFP_KERNEL);
     if (!board) return -ENOMEM;
     if (!of_property_read_u32(pdev->dev.of_node, "cle", &val))
       board->cle = (u8)val;
     else
       board->cle = 0;
     if (!of_property_read_u32(pdev->dev.of_node, "ale", &val))
       board->ale = (u8)val;
     else
       board->ale = 1;
     if (!of_property_read_u32(pdev->dev.of_node, "bank-width", &val))
       board->width = (u8)val * 8;
     else
       board->width = 8;
     if (!of_property_read_u32(pdev->dev.of_node, "chip-delay", &val)) board->chip_delay = (u8)val;
   } else {
     board = dev_get_platdata(&pdev->dev);
   }
   mtd->dev.parent = &pdev->dev;
   nand_set_controller_data(nc, board);
   nand_set_flash_node(nc, pdev->dev.of_node);
   nc->legacy.IO_ADDR_R = nc->legacy.IO_ADDR_W = io_base;
   nc->legacy.cmd_ctrl = orion_nand_cmd_ctrl;
   nc->legacy.read_buf = orion_nand_read_buf;
   nc->ecc.mode = NAND_ECC_SOFT;
   nc->ecc.algo = NAND_ECC_HAMMING;
-  if (board->chip_delay) nc->chip_delay = board->chip_delay;
+  if (board->chip_delay) nc->legacy.chip_delay = board->chip_delay;
   WARN(board->width > 16, "%d bit bus width out of range", board->width);
   if (board->width == 16) nc->options |= NAND_BUSWIDTH_16;
   platform_set_drvdata(pdev, info);
   /* Not all platforms can gate the clock, so it is not
      an error if the clock does not exists. */
   info->clk = devm_clk_get(&pdev->dev, NULL);
   if (IS_ERR(info->clk)) {
     ret = PTR_ERR(info->clk);
     if (ret == -ENOENT) {
       info->clk = NULL;
     } else {
       dev_err(&pdev->dev, "failed to get clock!\n");
       return ret;
     }
   }
   ret = clk_prepare_enable(info->clk);
   if (ret) {
     dev_err(&pdev->dev, "failed to prepare clock!\n");
     return ret;
   }
   ret = nand_scan(nc, 1);
   if (ret) goto no_dev;
   mtd->name = "orion_nand";
   ret = mtd_device_register(mtd, board->parts, board->nr_parts);
   if (ret) {
     nand_release(nc);
     goto no_dev;
   }
   return 0;
 no_dev:
   clk_disable_unprepare(info->clk);
   return ret;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,64 +1,64 @@
 static int oxnas_nand_probe(struct platform_device *pdev) {
   struct device_node *np = pdev->dev.of_node;
   struct device_node *nand_np;
   struct oxnas_nand_ctrl *oxnas;
   struct nand_chip *chip;
   struct mtd_info *mtd;
   struct resource *res;
   int nchips = 0;
   int count = 0;
   int err = 0;
   /* Allocate memory for the device structure (and zero it) */
   oxnas = devm_kzalloc(&pdev->dev, sizeof(*oxnas), GFP_KERNEL);
   if (!oxnas) return -ENOMEM;
   nand_controller_init(&oxnas->base);
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(oxnas->io_base)) return PTR_ERR(oxnas->io_base);
   oxnas->clk = devm_clk_get(&pdev->dev, NULL);
   if (IS_ERR(oxnas->clk)) oxnas->clk = NULL;
   /* Only a single chip node is supported */
   count = of_get_child_count(np);
   if (count > 1) return -EINVAL;
   err = clk_prepare_enable(oxnas->clk);
   if (err) return err;
   device_reset_optional(&pdev->dev);
   for_each_child_of_node(np, nand_np) {
     chip = devm_kzalloc(&pdev->dev, sizeof(struct nand_chip), GFP_KERNEL);
     if (!chip) {
       err = -ENOMEM;
       goto err_clk_unprepare;
     }
     chip->controller = &oxnas->base;
     nand_set_flash_node(chip, nand_np);
     nand_set_controller_data(chip, oxnas);
     mtd = nand_to_mtd(chip);
     mtd->dev.parent = &pdev->dev;
     mtd->priv = chip;
     chip->legacy.cmd_ctrl = oxnas_nand_cmd_ctrl;
     chip->legacy.read_buf = oxnas_nand_read_buf;
     chip->legacy.read_byte = oxnas_nand_read_byte;
     chip->legacy.write_buf = oxnas_nand_write_buf;
-    chip->chip_delay = 30;
+    chip->legacy.chip_delay = 30;
     /* Scan to find existence of the device */
     err = nand_scan(chip, 1);
     if (err) goto err_clk_unprepare;
     err = mtd_device_register(mtd, NULL, 0);
     if (err) {
       nand_release(chip);
       goto err_clk_unprepare;
     }
     oxnas->chips[nchips] = chip;
     ++nchips;
   }
   /* Exit if no chips found */
   if (!nchips) {
     err = -ENODEV;
     goto err_clk_unprepare;
   }
   platform_set_drvdata(pdev, oxnas);
   return 0;
 err_clk_unprepare:
   clk_disable_unprepare(oxnas->clk);
   return err;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,66 +1,66 @@
 static int pasemi_nand_probe(struct platform_device *ofdev) {
   struct device *dev = &ofdev->dev;
   struct pci_dev *pdev;
   struct device_node *np = dev->of_node;
   struct resource res;
   struct nand_chip *chip;
   int err = 0;
   err = of_address_to_resource(np, 0, &res);
   if (err) return -EINVAL;
   /* We only support one device at the moment */
   if (pasemi_nand_mtd) return -ENODEV;
   dev_dbg(dev, "pasemi_nand at %pR\n", &res);
   /* Allocate memory for MTD device structure and private data */
   chip = kzalloc(sizeof(struct nand_chip), GFP_KERNEL);
   if (!chip) {
     err = -ENOMEM;
     goto out;
   }
   pasemi_nand_mtd = nand_to_mtd(chip);
   /* Link the private data with the MTD structure */
   pasemi_nand_mtd->dev.parent = dev;
   chip->legacy.IO_ADDR_R = of_iomap(np, 0);
   chip->legacy.IO_ADDR_W = chip->legacy.IO_ADDR_R;
   if (!chip->legacy.IO_ADDR_R) {
     err = -EIO;
     goto out_mtd;
   }
   pdev = pci_get_device(PCI_VENDOR_ID_PASEMI, 0xa008, NULL);
   if (!pdev) {
     err = -ENODEV;
     goto out_ior;
   }
   lpcctl = pci_resource_start(pdev, 0);
   pci_dev_put(pdev);
   if (!request_region(lpcctl, 4, driver_name)) {
     err = -EBUSY;
     goto out_ior;
   }
   chip->legacy.cmd_ctrl = pasemi_hwcontrol;
   chip->legacy.dev_ready = pasemi_device_ready;
   chip->legacy.read_buf = pasemi_read_buf;
   chip->legacy.write_buf = pasemi_write_buf;
-  chip->chip_delay = 0;
+  chip->legacy.chip_delay = 0;
   chip->ecc.mode = NAND_ECC_SOFT;
   chip->ecc.algo = NAND_ECC_HAMMING;
   /* Enable the following for a flash based bad block table */
   chip->bbt_options = NAND_BBT_USE_FLASH;
   /* Scan to find existence of the device */
   err = nand_scan(chip, 1);
   if (err) goto out_lpc;
   if (mtd_device_register(pasemi_nand_mtd, NULL, 0)) {
     dev_err(dev, "Unable to register MTD device\n");
     err = -ENODEV;
     goto out_lpc;
   }
   dev_info(dev, "PA Semi NAND flash at %pR, control at I/O %x\n", &res, lpcctl);
   return 0;
 out_lpc:
   release_region(lpcctl, 4);
 out_ior:
   iounmap(chip->legacy.IO_ADDR_R);
 out_mtd:
   kfree(chip);
 out:
   return err;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,53 +1,53 @@
 static void s3c2410_nand_init_chip(struct s3c2410_nand_info *info, struct s3c2410_nand_mtd *nmtd, struct s3c2410_nand_set *set) {
   struct device_node *np = info->device->of_node;
   struct nand_chip *chip = &nmtd->chip;
   void __iomem *regs = info->regs;
   nand_set_flash_node(chip, set->of_node);
   chip->legacy.write_buf = s3c2410_nand_write_buf;
   chip->legacy.read_buf = s3c2410_nand_read_buf;
   chip->select_chip = s3c2410_nand_select_chip;
-  chip->chip_delay = 50;
+  chip->legacy.chip_delay = 50;
   nand_set_controller_data(chip, nmtd);
   chip->options = set->options;
   chip->controller = &info->controller;
   /*
    * let's keep behavior unchanged for legacy boards booting via pdata and
    * auto-detect timings only when booting with a device tree.
    */
   if (np) chip->setup_data_interface = s3c2410_nand_setup_data_interface;
   switch (info->cpu_type) {
   case TYPE_S3C2410:
     chip->legacy.IO_ADDR_W = regs + S3C2410_NFDATA;
     info->sel_reg = regs + S3C2410_NFCONF;
     info->sel_bit = S3C2410_NFCONF_nFCE;
     chip->legacy.cmd_ctrl = s3c2410_nand_hwcontrol;
     chip->legacy.dev_ready = s3c2410_nand_devready;
     break;
   case TYPE_S3C2440:
     chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA;
     info->sel_reg = regs + S3C2440_NFCONT;
     info->sel_bit = S3C2440_NFCONT_nFCE;
     chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol;
     chip->legacy.dev_ready = s3c2440_nand_devready;
     chip->legacy.read_buf = s3c2440_nand_read_buf;
     chip->legacy.write_buf = s3c2440_nand_write_buf;
     break;
   case TYPE_S3C2412:
     chip->legacy.IO_ADDR_W = regs + S3C2440_NFDATA;
     info->sel_reg = regs + S3C2440_NFCONT;
     info->sel_bit = S3C2412_NFCONT_nFCE0;
     chip->legacy.cmd_ctrl = s3c2440_nand_hwcontrol;
     chip->legacy.dev_ready = s3c2412_nand_devready;
     if (readl(regs + S3C2410_NFCONF) & S3C2412_NFCONF_NANDBOOT) dev_info(info->device, "System booted from NAND\n");
     break;
   }
   chip->legacy.IO_ADDR_R = chip->legacy.IO_ADDR_W;
   nmtd->info = info;
   nmtd->set = set;
   chip->ecc.mode = info->platform->ecc_mode;
   /*
    * If you use u-boot BBT creation code, specifying this flag will
    * let the kernel fish out the BBT from the NAND.
    */
   if (set->flash_bbt) chip->bbt_options |= NAND_BBT_USE_FLASH;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,69 +1,69 @@
 static int flctl_probe(struct platform_device *pdev) {
   struct resource *res;
   struct sh_flctl *flctl;
   struct mtd_info *flctl_mtd;
   struct nand_chip *nand;
   struct sh_flctl_platform_data *pdata;
   int ret;
   int irq;
   flctl = devm_kzalloc(&pdev->dev, sizeof(struct sh_flctl), GFP_KERNEL);
   if (!flctl) return -ENOMEM;
   res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   flctl->reg = devm_ioremap_resource(&pdev->dev, res);
   if (IS_ERR(flctl->reg)) return PTR_ERR(flctl->reg);
   flctl->fifo = res->start + 0x24; /* FLDTFIFO */
   irq = platform_get_irq(pdev, 0);
   if (irq < 0) {
     dev_err(&pdev->dev, "failed to get flste irq data: %d\n", irq);
     return irq;
   }
   ret = devm_request_irq(&pdev->dev, irq, flctl_handle_flste, IRQF_SHARED, "flste", flctl);
   if (ret) {
     dev_err(&pdev->dev, "request interrupt failed.\n");
     return ret;
   }
   if (pdev->dev.of_node)
     pdata = flctl_parse_dt(&pdev->dev);
   else
     pdata = dev_get_platdata(&pdev->dev);
   if (!pdata) {
     dev_err(&pdev->dev, "no setup data defined\n");
     return -EINVAL;
   }
   platform_set_drvdata(pdev, flctl);
   nand = &flctl->chip;
   flctl_mtd = nand_to_mtd(nand);
   nand_set_flash_node(nand, pdev->dev.of_node);
   flctl_mtd->dev.parent = &pdev->dev;
   flctl->pdev = pdev;
   flctl->hwecc = pdata->has_hwecc;
   flctl->holden = pdata->use_holden;
   flctl->flcmncr_base = pdata->flcmncr_val;
   flctl->flintdmacr_base = flctl->hwecc ? (STERINTE | ECERB) : STERINTE;
   /* Set address of hardware control function */
   /* 20 us command delay time */
-  nand->chip_delay = 20;
+  nand->legacy.chip_delay = 20;
   nand->legacy.read_byte = flctl_read_byte;
   nand->legacy.write_buf = flctl_write_buf;
   nand->legacy.read_buf = flctl_read_buf;
   nand->select_chip = flctl_select_chip;
   nand->legacy.cmdfunc = flctl_cmdfunc;
   nand->legacy.set_features = nand_get_set_features_notsupp;
   nand->legacy.get_features = nand_get_set_features_notsupp;
   if (pdata->flcmncr_val & SEL_16BIT) nand->options |= NAND_BUSWIDTH_16;
   pm_runtime_enable(&pdev->dev);
   pm_runtime_resume(&pdev->dev);
   flctl_setup_dma(flctl);
   nand->dummy_controller.ops = &flctl_nand_controller_ops;
   ret = nand_scan(nand, 1);
   if (ret) goto err_chip;
   ret = mtd_device_register(flctl_mtd, pdata->parts, pdata->nr_parts);
   if (ret) goto cleanup_nand;
   return 0;
 cleanup_nand:
   nand_cleanup(nand);
 err_chip:
   flctl_release_dma(flctl);
   pm_runtime_disable(&pdev->dev);
   return ret;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,73 +1,73 @@
 static int sharpsl_nand_probe(struct platform_device *pdev) {
   struct nand_chip *this;
   struct mtd_info *mtd;
   struct resource *r;
   int err = 0;
   struct sharpsl_nand *sharpsl;
   struct sharpsl_nand_platform_data *data = dev_get_platdata(&pdev->dev);
   if (!data) {
     dev_err(&pdev->dev, "no platform data!\n");
     return -EINVAL;
   }
   /* Allocate memory for MTD device structure and private data */
   sharpsl = kzalloc(sizeof(struct sharpsl_nand), GFP_KERNEL);
   if (!sharpsl) return -ENOMEM;
   r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   if (!r) {
     dev_err(&pdev->dev, "no io memory resource defined!\n");
     err = -ENODEV;
     goto err_get_res;
   }
   /* map physical address */
   sharpsl->io = ioremap(r->start, resource_size(r));
   if (!sharpsl->io) {
     dev_err(&pdev->dev, "ioremap to access Sharp SL NAND chip failed\n");
     err = -EIO;
     goto err_ioremap;
   }
   /* Get pointer to private data */
   this = (struct nand_chip *)(&sharpsl->chip);
   /* Link the private data with the MTD structure */
   mtd = nand_to_mtd(this);
   mtd->dev.parent = &pdev->dev;
   mtd_set_ooblayout(mtd, data->ecc_layout);
   platform_set_drvdata(pdev, sharpsl);
   /*
    * PXA initialize
    */
   writeb(readb(sharpsl->io + FLASHCTL) | FLWP, sharpsl->io + FLASHCTL);
   /* Set address of NAND IO lines */
   this->legacy.IO_ADDR_R = sharpsl->io + FLASHIO;
   this->legacy.IO_ADDR_W = sharpsl->io + FLASHIO;
   /* Set address of hardware control function */
   this->legacy.cmd_ctrl = sharpsl_nand_hwcontrol;
   this->legacy.dev_ready = sharpsl_nand_dev_ready;
   /* 15 us command delay time */
-  this->chip_delay = 15;
+  this->legacy.chip_delay = 15;
   /* set eccmode using hardware ECC */
   this->ecc.mode = NAND_ECC_HW;
   this->ecc.size = 256;
   this->ecc.bytes = 3;
   this->ecc.strength = 1;
   this->badblock_pattern = data->badblock_pattern;
   this->ecc.hwctl = sharpsl_nand_enable_hwecc;
   this->ecc.calculate = sharpsl_nand_calculate_ecc;
   this->ecc.correct = nand_correct_data;
   /* Scan to find existence of the device */
   err = nand_scan(this, 1);
   if (err) goto err_scan;
   /* Register the partitions */
   mtd->name = "sharpsl-nand";
   err = mtd_device_parse_register(mtd, data->part_parsers, NULL, data->partitions, data->nr_partitions);
   if (err) goto err_add;
   /* Return happy */
   return 0;
 err_add:
   nand_release(this);
 err_scan:
   iounmap(sharpsl->io);
 err_ioremap:
 err_get_res:
   kfree(sharpsl);
   return err;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay
--- initial
+++ final
@@ -1,40 +1,40 @@
 static int socrates_nand_probe(struct platform_device *ofdev) {
   struct socrates_nand_host *host;
   struct mtd_info *mtd;
   struct nand_chip *nand_chip;
   int res;
   /* Allocate memory for the device structure (and zero it) */
   host = devm_kzalloc(&ofdev->dev, sizeof(*host), GFP_KERNEL);
   if (!host) return -ENOMEM;
   host->io_base = of_iomap(ofdev->dev.of_node, 0);
   if (host->io_base == NULL) {
     dev_err(&ofdev->dev, "ioremap failed\n");
     return -EIO;
   }
   nand_chip = &host->nand_chip;
   mtd = nand_to_mtd(nand_chip);
   host->dev = &ofdev->dev;
   /* link the private data structures */
   nand_set_controller_data(nand_chip, host);
   nand_set_flash_node(nand_chip, ofdev->dev.of_node);
   mtd->name = "socrates_nand";
   mtd->dev.parent = &ofdev->dev;
   nand_chip->legacy.cmd_ctrl = socrates_nand_cmd_ctrl;
   nand_chip->legacy.read_byte = socrates_nand_read_byte;
   nand_chip->legacy.write_buf = socrates_nand_write_buf;
   nand_chip->legacy.read_buf = socrates_nand_read_buf;
   nand_chip->legacy.dev_ready = socrates_nand_device_ready;
   nand_chip->ecc.mode = NAND_ECC_SOFT; /* enable ECC */
   nand_chip->ecc.algo = NAND_ECC_HAMMING;
   /* TODO: I have no idea what real delay is. */
-  nand_chip->chip_delay = 20; /* 20us command delay time */
+  nand_chip->legacy.chip_delay = 20; /* 20us command delay time */
   dev_set_drvdata(&ofdev->dev, host);
   res = nand_scan(nand_chip, 1);
   if (res) goto out;
   res = mtd_device_register(mtd, NULL, 0);
   if (!res) return res;
   nand_release(nand_chip);
 out:
   iounmap(host->io_base);
   return res;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay