--- initial
+++ final
@@ -1,97 +1,97 @@
 static int lpc32xx_nand_probe(struct platform_device *pdev) {
   struct lpc32xx_nand_host *host;
   struct mtd_info *mtd;
   struct nand_chip *chip;
   struct resource *rc;
   int res;
   /* Allocate memory for the device structure (and zero it) */
   host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL);
   if (!host) return -ENOMEM;
   rc = platform_get_resource(pdev, IORESOURCE_MEM, 0);
   host->io_base = devm_ioremap_resource(&pdev->dev, rc);
   if (IS_ERR(host->io_base)) return PTR_ERR(host->io_base);
   host->io_base_dma = rc->start;
   if (pdev->dev.of_node) host->ncfg = lpc32xx_parse_dt(&pdev->dev);
   if (!host->ncfg) {
     dev_err(&pdev->dev, "Missing or bad NAND config from device tree\n");
     return -ENOENT;
   }
   if (host->ncfg->wp_gpio == -EPROBE_DEFER) return -EPROBE_DEFER;
   if (gpio_is_valid(host->ncfg->wp_gpio) && devm_gpio_request(&pdev->dev, host->ncfg->wp_gpio, "NAND WP")) {
     dev_err(&pdev->dev, "GPIO not available\n");
     return -EBUSY;
   }
   lpc32xx_wp_disable(host);
   host->pdata = dev_get_platdata(&pdev->dev);
   chip = &host->nand_chip;
   mtd = nand_to_mtd(chip);
   nand_set_controller_data(chip, host);
   nand_set_flash_node(chip, pdev->dev.of_node);
   mtd->owner = THIS_MODULE;
   mtd->dev.parent = &pdev->dev;
   /* Get NAND clock */
   host->clk = devm_clk_get(&pdev->dev, NULL);
   if (IS_ERR(host->clk)) {
     dev_err(&pdev->dev, "Clock failure\n");
     res = -ENOENT;
     goto enable_wp;
   }
   res = clk_prepare_enable(host->clk);
   if (res) goto enable_wp;
   /* Set NAND IO addresses and command/ready functions */
   chip->legacy.IO_ADDR_R = SLC_DATA(host->io_base);
   chip->legacy.IO_ADDR_W = SLC_DATA(host->io_base);
   chip->legacy.cmd_ctrl = lpc32xx_nand_cmd_ctrl;
   chip->legacy.dev_ready = lpc32xx_nand_device_ready;
-  chip->chip_delay = 20; /* 20us command delay time */
+  chip->legacy.chip_delay = 20; /* 20us command delay time */
   /* Init NAND controller */
   lpc32xx_nand_setup(host);
   platform_set_drvdata(pdev, host);
   /* NAND callbacks for LPC32xx SLC hardware */
   chip->ecc.mode = NAND_ECC_HW_SYNDROME;
   chip->legacy.read_byte = lpc32xx_nand_read_byte;
   chip->legacy.read_buf = lpc32xx_nand_read_buf;
   chip->legacy.write_buf = lpc32xx_nand_write_buf;
   chip->ecc.read_page_raw = lpc32xx_nand_read_page_raw_syndrome;
   chip->ecc.read_page = lpc32xx_nand_read_page_syndrome;
   chip->ecc.write_page_raw = lpc32xx_nand_write_page_raw_syndrome;
   chip->ecc.write_page = lpc32xx_nand_write_page_syndrome;
   chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
   chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
   chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
   chip->ecc.correct = nand_correct_data;
   chip->ecc.strength = 1;
   chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
   /*
    * Allocate a large enough buffer for a single huge page plus
    * extra space for the spare area and ECC storage area
    */
   host->dma_buf_len = LPC32XX_DMA_DATA_SIZE + LPC32XX_ECC_SAVE_SIZE;
   host->data_buf = devm_kzalloc(&pdev->dev, host->dma_buf_len, GFP_KERNEL);
   if (host->data_buf == NULL) {
     res = -ENOMEM;
     goto unprepare_clk;
   }
   res = lpc32xx_nand_dma_setup(host);
   if (res) {
     res = -EIO;
     goto unprepare_clk;
   }
   /* Find NAND device */
   chip->dummy_controller.ops = &lpc32xx_nand_controller_ops;
   res = nand_scan(chip, 1);
   if (res) goto release_dma;
   mtd->name = "nxp_lpc3220_slc";
   res = mtd_device_register(mtd, host->ncfg->parts, host->ncfg->num_parts);
   if (res) goto cleanup_nand;
   return 0;
 cleanup_nand:
   nand_cleanup(chip);
 release_dma:
   dma_release_channel(host->dma_chan);
 unprepare_clk:
   clk_disable_unprepare(host->clk);
 enable_wp:
   lpc32xx_wp_enable(host);
   return res;
 }<sep>@@
struct nand_chip *chip;
@@
- chip->chip_delay
+ chip->legacy.chip_delay