GitHub repository: yomnahisham/ts-verilog-simulator
Primary language: TypeScript
Created: 2025-04-28T21:29:54Z
Description: A web-based Verilog simulator for designing, running, and visualizing RTL code in-browser. Built with Next.js 14, TypeScript, Tailwind CSS, and Monaco Editor on the frontend, and FastAPI with a custom Python simulation engine on the backend with real-time simulation, interactive waveform viewing, multi-file support, and automated module detection.