GitHub repository: riscv/riscv-ras-eri
Primary language: TeX
Created: 2022-06-07T20:50:58Z
Description: The (RAS Error-record Register Interface) RERI provides a specification to augment RAS features in RISC-V SOC hardware to standardize reporting and logging of errors by means of a memory-mapped register interface to enable error detection, provide the facility to log the detected errors (including their severity, nature, and location), and configuring means to report the error to a handler component.