GitHub repository: riac1414/Cache-Memory-Hierarchy-Simulator
Primary language: C++
Created: 2020-09-16T17:06:10Z
Description: Developed a generic trace driven L1 and L2 cache simulator with WBWA Policy and Least Recently Used Replacement Policy.  Equipped L2 cache with decoupled sectored cache to improve hit rate by 25% and reduce architectural cost