GitHub repository: virtual-labs/exp-3-bit-even-parity-generator-circuit-nitk
Primary language: HTML
Created: 2022-08-09T06:44:24Z
Description: This experiment belongs to VLSI Design Verification and Testing Laboratory NITK.​​​​ Full Name: Detection of both SAO and SA1 faults on a VLSI circuit for 3-bit EVEN parity generator circuit.