GitHub repository: yeshwanthkattta/MIPS-Project
Created: 2024-02-22T19:22:57Z
Description: Design and verification of a 8-bit MIPS processor, integrating modules such as the Instruction Register, Control FSM, Register File, ALU, ALU Control, and Program Counter. Employed Verilog for RTL design , closely mirroring the functionalities and verification approaches to UVM environments. Crafted schematics and layouts with Virtuoso.