GitHub repository: victorlga/mips_pipeline_32bits
Primary language: VHDL
Created: 2023-11-23T17:14:34Z
Description: This project is a 5-stage pipeline MIPS CPU, which is implemented in VHDL. The CPU supports 18 MIPS instructions, including 32 general purpose registers, 32-bit ALU, 32-bit PC, 32-bit data memory, and 32-bit instruction memory. The CPU is tested by running a MIPS assembly program.