GitHub repository: suhasr1991/5-Stage-Pipelined-IEEE-Single-Precision-Floating-Point-Adder-Design
Primary language: Verilog
Created: 2018-03-06T18:23:36Z
Description: In this project a 32 bit Floating point adder was designed using Verilog HDL. This design was pipelined to reduce the computations in a single cycle.