GitHub repository: techvinodreddy/UART-IP-CORE16550A-Verification-UVM
Primary language: Verilog
Created: 2021-06-05T04:49:14Z
Description: The UART (Universal Asynchronous Receiver/Transmitter) core provides serial  communication capabilities, which allow communication with modem or other external  devices, like another computer using a serial cable and RS232 protocol. This core is  designed to be maximally compatible with the industry standard National  Semiconductors’ 16550A device.