GitHub repository: sourav-bhongade/Custom-8-Bit-CPU-in-Verilog-Minimal-RISC-Like-Architecture
Primary language: Verilog
Created: 2025-07-16T18:36:36Z
Description: A handcrafted 8-bit CPU designed and implemented from scratch in Verilog. Includes custom 3-2-3 instruction format, modular architecture, support for ALU, branching, and immediate logic. Ideal for educational CPU design, EDA Playground simulation, and architecture learning.