GitHub repository: riadhbenabdelhamid/BRISKI
Primary language: SystemVerilog
Created: 2024-06-14T12:15:52Z
Description: BRISKI ( Barrel RISC-V for Kilo-core Implementations ) is a fast and compact RISC-V barrel processor core that emphasize high throughput and compute density to increase the amount of cores in many-core design without sacrificing performance.