GitHub repository: kohiblancaj/Clock-With-Alarm-
Primary language: Verilog
Created: 2023-01-15T05:11:02Z
Description: HDL Project  Type the following on your terminal:  (1) iverilog -o Testbench.vvp Testbench.v  (2) vvp Testbench.vvp  (3) gtkwave