GitHub repository: openhwgroup/cve2
Primary language: SystemVerilog
Created: 2022-03-21T17:16:45Z
Description: The CORE-V CVE2 is a small 32 bit RISC-V CPU core (RV32IMC/EMC) with a two stage pipeline, based on the original zero-riscy work from ETH Zurich and Ibex work from lowRISC.