GitHub repository: kinzafatim/5-Stage-RV32I
Primary language: FIRRTL
Created: 2024-09-12T10:14:37Z
Description: Welcome to the 5-Stage Pipeline RV32I Processor repository! This project implements a RISC-V 32-bit processor with a classic 5-stage pipeline architecture using Chisel. The processor is designed to handle instruction fetch, decode, execute, memory access, and write-back stages efficiently.