GitHub repository: neeraj-1213/Router_1X3_RTL
Created: 2025-01-23T13:23:55Z
Description: This repository contains a Verilog HDL implementation of a 1x3 router. The router directs data packets to one of three output ports. It includes modules for FIFO, FSM, registers, synchronization, and a top-level module. Use Xilinx for synthesis and implementation.