GitHub repository: mmzeynalli/RISC-V
Primary language: SystemVerilog
Created: 2023-03-30T21:59:17Z
Description: A simple 32-bit 5-stage RISC-V processor in SystemVerilog based on the book Computer Organization and Design by Patterson & Hennesy. Inspired by https://github.com/masoud-ata/PH-RISC-V