GitHub repository: naksha2-2/-SoC-Verification-Using-SystemVerilog-
Primary language: Python
Created: 2025-05-06T14:35:54Z
Description: This project demonstrates the functional verification of a simplified System-on-Chip (SoC) design using **SystemVerilog**. The SoC includes an embedded processor and peripheral components, verified through simulation using **testbenches**, **assertions**, and **constrained-random verification** techniques.