GitHub repository: Diya-m4/Router1x3
Created: 2025-04-13T14:18:01Z
Description: Developed and verified a 1x3 Router using Verilog HDL. Integrated key components such as FIFO, Synchronizer, Register, and an FSM-based controller. Performed verification using UVM, employing constraint-random test cases, assertions, and functional coverage metrics. Tools utilized: Vivado and QuestaSim