GitHub repository: JayapreethaS/SEQUENCE-DETECTOR-USING-SYNOPSYS
Created: 2025-04-01T15:44:02Z
Description: A Sequence Detector identifies a specific bit pattern (e.g., 1011) in a serial input stream using an FSM. Designed using Synopsys Tools, it involves:  FSM Design – Defines states for detecting the sequence.  RTL Implementation – Written in Verilog/VHDL and synthesized using Design Compiler.  Simulation & Verification – Done with VCS