GitHub repository: AdamKeith1/LOROF
Primary language: SystemVerilog
Created: 2024-12-23T14:16:16Z
Description: Linux-on-RISCV-on-FPGA. Goal is to design, verify, and implement on FPGA a RISC-V RV32IMA_Zicsr_Zifencei implementation with supervisor and user mode support, successfully booting and running Linux with documentation, RTL code and UVM based testbenches.