GitHub repository: BillMrvica/SME309_FinalProj_ARM_v3
Primary language: Verilog
Description: In this project, you will implement a five-stage pipeline processor that Prof. Lin has shown in the lecture based on the single-cycle processor you’ve implemented in Lab2. The structure is shown below. Take care of data hazards (data forwarding, stall, flush) and control hazards (early BTA, flush).