GitHub repository: AseelZhour/32-bit-Five-Stage-Pipeline-MIPS-Design-and-Implementation
Created: 2024-05-04T21:12:04Z
Description: This project involves designing and implementing a **5-stage 32-bit pipeline MIPS architecture** using Verilog. The stages of the pipeline include instruction fetch, instruction decoding, execution, memory access, and write-back.