GitHub repository: AhseenGit/multicycle-cpu-architecture
Primary language: VHDL
Created: 2025-05-25T07:48:06Z
Description: This project implements a multicycle RISC processor architecture using VHDL. It was developed as part of the *Advanced CPU Architecture and Hardware Accelerators Lab* course, focusing on digital system design, datapath/control separation, and instruction-level execution over multiple clock cycles.