GitHub repository: D0745867/AES_proto
Primary language: Verilog
Created: 2023-10-21T06:57:47Z
Description: This project is referred to http://zongyue.top:8090/archives/aes%E5%92%8Csm4s%E7%9B%92%E5%A4%8D%E5%90%88%E5%9F%9F%E5%AE%9E%E7%8E%B0%E6%96%B9%E6%B3%95 AES verilog exercises made for the basics of S-box generation