GitHub repository: AlixYehia/Physical-Implementation-of-CORE-V-CV32E40P-RISC-V-IP
Primary language: Verilog
Created: 2025-04-28T19:00:21Z
Description: A complete ASIC implementation of the CV32E40P RISC-V core from OpenHW Group, covering RTL synthesis, floorplanning, placement, clock tree synthesis, routing, timing closure and DFT insertion