GitHub repository: Enanter/SimplePipelineCore
Primary language: SystemVerilog
Created: 2023-10-02T18:41:16Z
Description: Developing an out-of-order pipelined CPU microarchitecture which support RISC-V 32bit integer ISA. This digital design is going to be developed and simulated with systemverilog. It is going to be emulated on a PYNQ Z2 and Genesys 2 FPGA board.