GitHub repository: Ashwin-Rajesh/RiSC-16
Primary language: Assembly
Created: 2022-01-06T08:30:42Z
Description: RiSC 16 is a simple 16 bit instruction set with 8 instructions and 3 instruction formats. This is an RTL implementation in verilog, instruction set simulator and a random instruction generator in system verilog and a rudimetary assembler in python