GitHub repository: JonathanLiang6/RISC-V_SingleCycle_CPU
Primary language: Verilog
Description: 一个基于 RISC-V RV32I 指令集的单周期 CPU。使用 Verilog HDL 实现，支持核心的数据处理、内存访问和控制流指令，并通过板载七段数码管显示内部状态与结果。 A single-cycle CPU based on the RISC-V RV32I instruction set. Implemented in Verilog HDL, it supports core data processing, memory access, and control flow instructions, displaying internal states and results on an onboard 7-segment display.