GitHub repository: EngAhmed21/RISC-V-Processor-with-Pipelining
Primary language: Verilog
Created: 2024-02-09T18:02:43Z
Description: Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and multi cycle instructions, ALU unit works in parallel with a multiplication unit, and Reorder Buffer to guarantee in-order termination.