GitHub repository: Dilobutt/Single-Cycle-RiscV-Architecture
Created: 2024-12-29T05:07:53Z
Description: This project showcases the implementation of a RISC-V processor using a single-cycle architecture. Each instruction is executed in a single clock cycle, and the design incorporates Control and Status Registers (CSR) for effective system-level control and exception handling. The CSR trap mechanism is hard-wired to manage exceptions seamlessly.